From 95aa5d8b14bcc73a97dce20538c905431ca8404a Mon Sep 17 00:00:00 2001 From: Spurthy Mutturaj Date: Thu, 29 Aug 2024 10:38:33 -0700 Subject: [PATCH] ARM: dts: msm: add xo clock to sde_cesta node in sun target Add XO clock to sde_cesta node. This will help to vote XO freq for cesta idle vote for mdp-clk. Change-Id: I33b309ed9ac2d9013fee8f071c5f07938e651e5f Signed-off-by: Spurthy Mutturaj Signed-off-by: Sampurna Bolloju --- display/sun-sde.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f5dda611..f1e10426 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -226,12 +226,13 @@ reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; - clock-names = "branch_clk", "core_clk"; - clock-rate = <575000000 575000000>; - clock-max-rate = <575000000 575000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + clock-names = "branch_clk", "core_clk","xo"; + clock-rate = <575000000 575000000 19200000>; + clock-max-rate = <575000000 575000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,