ARM: dts: msm: add support to configure hw-fence ctl reg offset
This change adds support for configuring mdp hw-fence ctl register offset, as this value can change from target-to-target. Change-Id: I436bec0732473c21cf4753cb292204ce618de512 Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
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@@ -574,6 +574,8 @@ Optional properties:
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- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature.
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- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used
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for ipcc registers access.
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- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg
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offset.
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- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline
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rotation.
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- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin,
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@@ -916,6 +918,7 @@ Example:
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qcom,sde-soccp-controller = <&soccp_pas>;
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qcom,sde-ipcc-protocol-id = <0x2>;
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qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
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qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
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qcom,sde-vbif-off = <0 0>;
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qcom,sde-vbif-id = <0 1>;
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@@ -266,6 +266,7 @@
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qcom,sde-ipcc-protocol-id = <0x4>;
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qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
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qcom,sde-soccp-controller = <&soccp_pas>;
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qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-reg-dma-off = <0 0x800>;
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