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ARM: dts: msm: add support to configure hw-fence ctl reg offset

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This change adds support for configuring mdp hw-fence ctl
register offset, as this value can change from target-to-target.

Change-Id: I436bec0732473c21cf4753cb292204ce618de512
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This commit is contained in:
Christina Oliveira
2024-01-24 15:31:57 -08:00
parent febcd23b71
commit 945dccd0fd
2 changed files with 4 additions and 0 deletions
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display/sun-sde-common.dtsi
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@@ -266,6 +266,7 @@
qcom,sde-ipcc-protocol-id = <0x4>;
qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
qcom,sde-soccp-controller = <&soccp_pas>;
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0 0x800>;