ARM: dts: msm: enable display on kera trustedvm platforms
Enable display on kera trustedvm platforms. Change-Id: I76a769baa8726f24a391b612b6558d8322e96527 Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com> Signed-off-by: lnxdisplay <lnxdisplay@localhost>
This commit is contained in:
Abhinav Saurabh
committed by
Linux Display Service Account
Linux Display Service Account
parent
7d2f2106a6
commit
91808d9891
18
display/trustedvm-kera-sde-display-atp-overlay.dts
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18
display/trustedvm-kera-sde-display-atp-overlay.dts
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@@ -0,0 +1,18 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include "trustedvm-kera-sde.dtsi"
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#include "trustedvm-kera-sde-display-mtp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Kera SVM ATP";
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compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap",
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"qcom,atp";
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qcom,msm-id = <686 0x10000>, <659 0x10000>;
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qcom,board-id = <33 0>;
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};
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18
display/trustedvm-kera-sde-display-cdp-overlay.dts
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18
display/trustedvm-kera-sde-display-cdp-overlay.dts
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@@ -0,0 +1,18 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include "trustedvm-kera-sde.dtsi"
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#include "trustedvm-kera-sde-display-cdp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Kera SVM CDP";
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compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap",
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"qcom,cdp";
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qcom,msm-id = <686 0x10000>, <659 0x10000>;
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qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>;
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};
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156
display/trustedvm-kera-sde-display-cdp.dtsi
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156
display/trustedvm-kera-sde-display-cdp.dtsi
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@@ -0,0 +1,156 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "trustedvm-kera-sde-display.dtsi"
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&dsi_vtdr6130_amoled_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_120hz_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_120hz_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_90hz_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_90hz_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_60hz_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_60hz_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_qsync_144hz_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_qsync_144hz_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_sim_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_vid {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_dsc_375_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_dsc_10b_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_dual_sim_vid {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_dual_sim_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,bl-dsc-cmd-state = "dsi_lp_mode";
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};
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&dsi_dual_sim_dsc_375_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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};
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&dsi_sim_sec_hd_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <1>;
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qcom,mdss-dsi-bl-max-level = <1023>;
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};
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&sde_dsi {
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qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
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};
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19
display/trustedvm-kera-sde-display-mtp-overlay.dts
Normal file
19
display/trustedvm-kera-sde-display-mtp-overlay.dts
Normal file
@@ -0,0 +1,19 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include "trustedvm-kera-sde.dtsi"
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#include "trustedvm-kera-sde-display-mtp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Kera SVM MTP";
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compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
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"qcom,mtp";
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qcom,msm-id = <686 0x10000>, <659 0x10000>;
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qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>,
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<0x30008 1>;
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};
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156
display/trustedvm-kera-sde-display-mtp.dtsi
Normal file
156
display/trustedvm-kera-sde-display-mtp.dtsi
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@@ -0,0 +1,156 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "trustedvm-kera-sde-display.dtsi"
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&dsi_vtdr6130_amoled_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_120hz_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_120hz_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_90hz_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_90hz_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_60hz_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_60hz_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_qsync_144hz_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_vtdr6130_amoled_qsync_144hz_video {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
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qcom,mdss-dsi-bl-min-level = <10>;
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qcom,mdss-dsi-bl-max-level = <4095>;
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qcom,mdss-brightness-max-level = <8191>;
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qcom,mdss-dsi-bl-inverted-dbv;
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qcom,platform-reset-gpio = <&tlmm 12 0>;
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qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
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};
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&dsi_sim_cmd {
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
|
||||
};
|
||||
18
display/trustedvm-kera-sde-display-qrd-overlay.dts
Normal file
18
display/trustedvm-kera-sde-display-qrd-overlay.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-kera-sde.dtsi"
|
||||
#include "trustedvm-kera-sde-display-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera SVM QRD";
|
||||
compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap",
|
||||
"qcom,qrd";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>;
|
||||
};
|
||||
156
display/trustedvm-kera-sde-display-qrd.dtsi
Normal file
156
display/trustedvm-kera-sde-display-qrd.dtsi
Normal file
@@ -0,0 +1,156 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "trustedvm-kera-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_60hz_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_60hz_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 12 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 127 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
|
||||
};
|
||||
19
display/trustedvm-kera-sde-display-rcm-overlay.dts
Normal file
19
display/trustedvm-kera-sde-display-rcm-overlay.dts
Normal file
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-kera-sde.dtsi"
|
||||
#include "trustedvm-kera-sde-display-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera SVM RCM";
|
||||
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
|
||||
"qcom,rcm";
|
||||
qcom,msm-id = <686 0x10000>, <659 0x10000>;
|
||||
qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>,
|
||||
<0x30015 1>;
|
||||
};
|
||||
17
display/trustedvm-kera-sde-display-rumi-overlay.dts
Normal file
17
display/trustedvm-kera-sde-display-rumi-overlay.dts
Normal file
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-kera-sde.dtsi"
|
||||
#include "trustedvm-kera-sde-display-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera SVM RUMI";
|
||||
compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi";
|
||||
qcom,msm-id = <659 0x10000>;
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
10
display/trustedvm-kera-sde-display-rumi.dtsi
Normal file
10
display/trustedvm-kera-sde-display-rumi.dtsi
Normal file
@@ -0,0 +1,10 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "trustedvm-kera-sde-display.dtsi"
|
||||
|
||||
&mdss_mdp {
|
||||
qcom,sde-emulated-env;
|
||||
};
|
||||
28
display/trustedvm-kera-sde-display.dtsi
Normal file
28
display/trustedvm-kera-sde-display.dtsi
Normal file
@@ -0,0 +1,28 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "kera-sde-display-common.dtsi"
|
||||
|
||||
&sde_dsi {
|
||||
clocks = <&clock_cpucc 0>,
|
||||
<&clock_cpucc 1>,
|
||||
<&clock_cpucc 2>,
|
||||
<&clock_cpucc 3>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1";
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
clocks = <&clock_cpucc 0>,
|
||||
<&clock_cpucc 1>,
|
||||
<&clock_cpucc 2>,
|
||||
<&clock_cpucc 3>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1";
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
connectors = <&sde_dsi &sde_dsi1>;
|
||||
};
|
||||
44
display/trustedvm-kera-sde.dtsi
Normal file
44
display/trustedvm-kera-sde.dtsi
Normal file
@@ -0,0 +1,44 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-kera.h>
|
||||
#include "kera-sde-common.dtsi"
|
||||
|
||||
&soc {
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
};
|
||||
|
||||
&mdss_dsi_phy0 {
|
||||
qcom,dsi-pll-in-trusted-vm;
|
||||
};
|
||||
|
||||
&mdss_dsi_phy1 {
|
||||
qcom,dsi-pll-in-trusted-vm;
|
||||
};
|
||||
Reference in New Issue
Block a user