From 91808d9891afdd2cb946203ca8bb88af87280d27 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 5 Nov 2024 07:41:22 +0530 Subject: [PATCH] ARM: dts: msm: enable display on kera trustedvm platforms Enable display on kera trustedvm platforms. Change-Id: I76a769baa8726f24a391b612b6558d8322e96527 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- ...trustedvm-kera-sde-display-atp-overlay.dts | 18 ++ ...trustedvm-kera-sde-display-cdp-overlay.dts | 18 ++ display/trustedvm-kera-sde-display-cdp.dtsi | 156 ++++++++++++++++++ ...trustedvm-kera-sde-display-mtp-overlay.dts | 19 +++ display/trustedvm-kera-sde-display-mtp.dtsi | 156 ++++++++++++++++++ ...trustedvm-kera-sde-display-qrd-overlay.dts | 18 ++ display/trustedvm-kera-sde-display-qrd.dtsi | 156 ++++++++++++++++++ ...trustedvm-kera-sde-display-rcm-overlay.dts | 19 +++ ...rustedvm-kera-sde-display-rumi-overlay.dts | 17 ++ display/trustedvm-kera-sde-display-rumi.dtsi | 10 ++ display/trustedvm-kera-sde-display.dtsi | 28 ++++ display/trustedvm-kera-sde.dtsi | 44 +++++ 12 files changed, 659 insertions(+) create mode 100644 display/trustedvm-kera-sde-display-atp-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-cdp-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-cdp.dtsi create mode 100644 display/trustedvm-kera-sde-display-mtp-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-mtp.dtsi create mode 100644 display/trustedvm-kera-sde-display-qrd-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-qrd.dtsi create mode 100644 display/trustedvm-kera-sde-display-rcm-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-rumi-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-rumi.dtsi create mode 100644 display/trustedvm-kera-sde-display.dtsi create mode 100644 display/trustedvm-kera-sde.dtsi diff --git a/display/trustedvm-kera-sde-display-atp-overlay.dts b/display/trustedvm-kera-sde-display-atp-overlay.dts new file mode 100644 index 00000000..362e7d57 --- /dev/null +++ b/display/trustedvm-kera-sde-display-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM ATP"; + compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap", + "qcom,atp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/trustedvm-kera-sde-display-cdp-overlay.dts b/display/trustedvm-kera-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..07e44da0 --- /dev/null +++ b/display/trustedvm-kera-sde-display-cdp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM CDP"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; +}; diff --git a/display/trustedvm-kera-sde-display-cdp.dtsi b/display/trustedvm-kera-sde-display-cdp.dtsi new file mode 100644 index 00000000..77b43890 --- /dev/null +++ b/display/trustedvm-kera-sde-display-cdp.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/trustedvm-kera-sde-display-mtp-overlay.dts b/display/trustedvm-kera-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..073f3342 --- /dev/null +++ b/display/trustedvm-kera-sde-display-mtp-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM MTP"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, + <0x30008 1>; +}; diff --git a/display/trustedvm-kera-sde-display-mtp.dtsi b/display/trustedvm-kera-sde-display-mtp.dtsi new file mode 100644 index 00000000..77b43890 --- /dev/null +++ b/display/trustedvm-kera-sde-display-mtp.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/trustedvm-kera-sde-display-qrd-overlay.dts b/display/trustedvm-kera-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..e2f6b39c --- /dev/null +++ b/display/trustedvm-kera-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM QRD"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/display/trustedvm-kera-sde-display-qrd.dtsi b/display/trustedvm-kera-sde-display-qrd.dtsi new file mode 100644 index 00000000..77b43890 --- /dev/null +++ b/display/trustedvm-kera-sde-display-qrd.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/trustedvm-kera-sde-display-rcm-overlay.dts b/display/trustedvm-kera-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..20c01be8 --- /dev/null +++ b/display/trustedvm-kera-sde-display-rcm-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RCM"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, + <0x30015 1>; +}; diff --git a/display/trustedvm-kera-sde-display-rumi-overlay.dts b/display/trustedvm-kera-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..0374cc20 --- /dev/null +++ b/display/trustedvm-kera-sde-display-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,msm-id = <659 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/trustedvm-kera-sde-display-rumi.dtsi b/display/trustedvm-kera-sde-display-rumi.dtsi new file mode 100644 index 00000000..6bf94fae --- /dev/null +++ b/display/trustedvm-kera-sde-display-rumi.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; diff --git a/display/trustedvm-kera-sde-display.dtsi b/display/trustedvm-kera-sde-display.dtsi new file mode 100644 index 00000000..e6420a52 --- /dev/null +++ b/display/trustedvm-kera-sde-display.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&sde_dsi1 { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; +}; diff --git a/display/trustedvm-kera-sde.dtsi b/display/trustedvm-kera-sde.dtsi new file mode 100644 index 00000000..9b88fd38 --- /dev/null +++ b/display/trustedvm-kera-sde.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "kera-sde-common.dtsi" + +&soc { +}; + +&mdss_mdp { +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +};