samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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Merge commit 'cf9561dbd68ba8950b3db10ccde96dbff27901dd' into kernel.lnx.6.6.r1-rel

Browse Source 
Signed-off-by: Niranjan Reddy Dumbala <quic_dnreddy@quicinc.com>
This commit is contained in:
Niranjan Reddy Dumbala
2024-12-15 17:02:02 +05:30
parent 3a10187308 cf9561dbd6
commit 85557b97d2
144 changed files with 11003 additions and 479 deletions
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25
bindings/arm/msm/msm.yaml
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@@ -156,8 +156,33 @@ properties:
- enum:
- qcom,kera-rumi
- qcom,rumi
- qcom,kera-atp
- qcom,atp
- qcom,kera-cdp
- qcom,cdp
- qcom,kera-mtp
- qcom,mtp
- qcom,kera-qrd
- qcom,qrd
- qcom,kera-rcm
- qcom,rcm
- const: qcom,kera
- description: Qualcomm Technologies, Inc. KERAP
items:
- enum:
- qcom,kerap-atp
- qcom,atp
- qcom,kerap-cdp
- qcom,cdp
- qcom,kerap-mtp
- qcom,mtp
- qcom,kerap-qrd
- qcom,qrd
- qcom,kerap-rcm
- qcom,rcm
- const: qcom,kerap
- description: Qualcomm Technologies, Inc. MONACO
items:
- enum:

1
bindings/arm/msm/qcom,llcc.yaml
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@@ -37,6 +37,7 @@ properties:
- qcom,sun-llcc
- qcom,sdxpinn-llcc
- qcom,tuna-llcc
- qcom,tuna7-llcc
- qcom,kera-llcc
- qcom,x1e80100-llcc

1
bindings/clock/qcom,dispcc-sm8x50.yaml
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@@ -31,6 +31,7 @@ properties:
- qcom,pineapple-dispcc
- qcom,sun-dispcc
- qcom,tuna-dispcc
- qcom,tuna-dispcc-v1
clocks:
items:

1
bindings/clock/qcom,gcc-sun.yaml
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@@ -23,6 +23,7 @@ properties:
- qcom,gcc-sun
- qcom,tuna-gcc
- qcom,kera-gcc
- qcom,tuna-gcc-v1
clocks:
items:

3
bindings/thermal/qcom-bcl-pmic5.yaml
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@@ -23,10 +23,11 @@ description: |
properties:
compatible:
description: msm battery state of charge device
description: msm battery current limiting device
items:
- const: qcom,bcl-v5
- const: qcom,pm8550-bcl-v5
- const: qcom,pmiv010x-bcl-v5
reg:
maxItems: 1

1
bindings/ufs/qcom,ufs.yaml
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@@ -37,6 +37,7 @@ properties:
- qcom,ufs-phy-qmp-v4-pineapple
- qcom,ufs-phy-qmp-v4-waipio
- qcom,ufs-phy-qmp-v4-sun
- qcom,ufs-phy-qmp-v4-niobe
- const: qcom,ufshc
- const: jedec,ufs-2.0

6
bindings/usb/qcom,dwc-usb3-msm.yaml
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@@ -61,6 +61,11 @@ properties:
USB3_GDSC-supply:
description: USB GDSC supply.
vbus_dwc3-supply:
description: Regulator supply for the VBUS 5V power for USB host mode.
This is typically used when VBUS is controlled by a GPIO-based
regulator to enable/disable USB port power.
clock-names:
minItems: 1
items:
@@ -168,6 +173,7 @@ examples:
ranges;
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
vbus_dwc3-supply = <&usb0_vbus_reg>;
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,

52
qcom/Makefile
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@@ -53,7 +53,8 @@ sun-dtb-$(CONFIG_ARCH_SUN) += \
sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_BASE_DTB) $(SUN_APQ_BASE_DTB)
TUNA_BASE_DTB += tuna.dtb tuna7.dtb
NOAPQ_TUNA_BOARDS += \
TUNA_APQ_BASE_DTB += tunap.dtb
TUNA_BOARDS += \
tuna-atp-overlay.dtbo \
tuna-cdp-overlay.dtbo \
tuna-mtp-kiwi-harmonium-overlay.dtbo \
@@ -64,21 +65,48 @@ NOAPQ_TUNA_BOARDS += \
tuna-mtp-kiwi-pmd802x-overlay.dtbo \
tuna-qrd-overlay.dtbo \
tuna-rcm-kiwi-overlay.dtbo \
tuna-rcm-overlay.dtbo \
tuna-rcm-overlay.dtbo
NOAPQ_TUNA_BOARDS += \
tuna-rumi-overlay.dtbo
sun-dtb-$(CONFIG_ARCH_TUNA) += \
$(call add-overlays, $(NOAPQ_TUNA_BOARDS),$(TUNA_BASE_DTB))
sun-overlays-dtb-$(CONFIG_ARCH_TUNA) += $(NOAPQ_TUNA_BOARDS) $(TUNA_BASE_DTB)
$(call add-overlays, $(TUNA_BOARDS) $(NOAPQ_TUNA_BOARDS),$(TUNA_BASE_DTB)) \
$(call add-overlays, $(TUNA_BOARDS) $(APQ_TUNA_BOARDS),$(TUNA_APQ_BASE_DTB))
sun-overlays-dtb-$(CONFIG_ARCH_TUNA) += $(TUNA_BOARDS) $(NOAPQ_TUNA_BOARDS) $(TUNA_BASE_DTB) $(TUNA_APQ_BASE_DTB)
dtb-y += $(sun-dtb-y)
KERA_BASE_DTB += kera.dtb
KERA_APQ_BASE_DTB += kerap.dtb
KERA_BOARDS += \
kera-atp-overlay.dtbo \
kera-mtp-qca6750-ufs4-overlay.dtbo \
kera-mtp-qca6750-ufs3-overlay.dtbo \
kera-mtp-qca6750-qmp1000-overlay.dtbo \
kera-mtp-wcn7750-qmp1000-overlay.dtbo \
kera-mtp-wcn7750-ufs4-overlay.dtbo \
kera-mtp-wcn7750-ufs3-overlay.dtbo \
kera-cdp-qca6750-ufs2-overlay.dtbo \
kera-cdp-qca6750-ufs3-overlay.dtbo \
kera-cdp-qca6750-ufs4-overlay.dtbo \
kera-qrd-wcn7750-ufs4-overlay.dtbo \
kera-qrd-wcn7750-ufs2-overlay.dtbo \
kera-qrd-wcn7750-ufs3-overlay.dtbo \
kera-rcm-qca6750-ufs4-overlay.dtbo \
kera-rcm-qca6750-ufs2-overlay.dtbo \
kera-rcm-qca6750-ufs3-overlay.dtbo \
kera-rcm-wcn7750-ufs2-overlay.dtbo \
kera-rcm-wcn7750-ufs3-overlay.dtbo \
kera-rcm-wcn7750-ufs4-overlay.dtbo
NOAPQ_KERA_BOARDS += \
kera-rumi-overlay.dtbo
sun-dtb-$(CONFIG_ARCH_KERA) += \
$(call add-overlays, $(NOAPQ_KERA_BOARDS),$(KERA_BASE_DTB))
sun-overlays-dtb-$(CONFIG_ARCH_KERA) += $(NOAPQ_KERA_BOARDS) $(KERA_BASE_DTB)
$(call add-overlays, $(KERA_BOARDS) $(NOAPQ_KERA_BOARDS),$(KERA_BASE_DTB)) \
$(call add-overlays, $(KERA_BOARDS) $(APQ_KERA_BOARDS),$(KERA_APQ_BASE_DTB))
sun-overlays-dtb-$(CONFIG_ARCH_KERA) += $(KERA_BOARDS) $(NOAPQ_KERA_BOARDS) $(KERA_BASE_DTB) $(KERA_APQ_BASE_DTB)
dtb-y += $(sun-dtb-y)
PINEAPPLE_BASE_DTB += pineapple.dtb pineapple-v2.dtb
@@ -240,7 +268,17 @@ endif
ifeq ($(CONFIG_ARCH_KERA), y)
ifeq ($(CONFIG_ARCH_QTI_VM), y)
kera_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += kera-vm-rumi.dtb \
kera-oemvm-rumi.dtb
kera-vm-atp.dtb \
kera-vm-cdp.dtb \
kera-vm-mtp.dtb \
kera-vm-qrd.dtb \
kera-vm-rcm.dtb \
kera-oemvm-rumi.dtb \
kera-oemvm-atp.dtb \
kera-oemvm-cdp.dtb \
kera-oemvm-mtp.dtb \
kera-oemvm-qrd.dtb \
kera-oemvm-rcm.dtb
dtb-y += $(kera_tuivm-dtb-y)
endif
endif

19
qcom/kera-atp-overlay.dts Normal file
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@@ -0,0 +1,19 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-pm7550ba.dtsi"
#include "kera-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera ATP";
compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap",
"qcom,atp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <33 0>;
};

33
qcom/kera-atp.dtsi Normal file
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@@ -0,0 +1,33 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976270>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
qcom,uses_level_shifter;
status = "ok";
};
&pmic_glink_debug {
status = "disabled";
};
&pmic_glink_adc {
status = "disabled";
};

19
qcom/kera-cdp-qca6750-ufs2-overlay.dts Normal file
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@@ -0,0 +1,19 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-cdp-qca6750-ufs2.dtsi"
#include "kera-pmiv0102.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera CDP + QCA6750 + UFS2";
compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap",
"qcom,cdp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x30001 0>;
};

7
qcom/kera-cdp-qca6750-ufs2.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-cdp.dtsi"
#include "kera_ufs2.dtsi"

19
qcom/kera-cdp-qca6750-ufs3-overlay.dts Normal file
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@@ -0,0 +1,19 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-cdp-qca6750-ufs3.dtsi"
#include "kera-pmiv0102.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera CDP + QCA6750 + UFS3";
compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap",
"qcom,cdp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x20001 0>;
};

7
qcom/kera-cdp-qca6750-ufs3.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-cdp.dtsi"
#include "kera_ufs3.dtsi"

19
qcom/kera-cdp-qca6750-ufs4-overlay.dts Normal file
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@@ -0,0 +1,19 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-cdp-qca6750-ufs4.dtsi"
#include "kera-pmiv0102.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera CDP + QCA6750 + UFS4";
compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap",
"qcom,cdp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x10001 0>, <0x40001 0>;
};

7
qcom/kera-cdp-qca6750-ufs4.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-cdp.dtsi"
#include "kera_ufs4.dtsi"

66
qcom/kera-cdp.dtsi Normal file
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@@ -0,0 +1,66 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976270>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
qcom,uses_level_shifter;
status = "ok";
};
&qupv3_se8_spi {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,touch-active = "goodix,gt9916S";
qcom,la-vm;
goodix-berlin@0 {
compatible = "goodix,gt9916S";
reg = <0>;
spi-max-frequency = <1000000>;
interrupt-parent = <&tlmm>;
interrupts = <13 0x2008>;
goodix,reset-gpio = <&tlmm 16 0x00>;
goodix,irq-gpio = <&tlmm 13 0x2008>;
goodix,irq-flags = <2>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,firmware-name = "goodix_firmware_spi.bin";
goodix,config-name = "goodix_cfg_group_spi.bin";
goodix,avdd-name = "avdd";
goodix,iovdd-name = "iovdd";
avdd-supply = <&L22B>;
iovdd-supply = <&L8B>;
goodix,touch-type = "primary";
goodix,qts_en;
qts,trusted-touch-mode = "vm_mode";
qts,touch-environment = "pvm";
qts,trusted-touch-type = "primary";
qts,trusted-touch-spi-irq = <653>;
qts,trusted-touch-io-bases = <0xa90000>;
qts,trusted-touch-io-sizes = <0x1000>;
qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0
&tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>;
};
};

19
qcom/kera-dma-heaps.dtsi
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@@ -10,10 +10,29 @@
compatible = "qcom,dma-heaps";
depends-on-supply = <&qcom_scm>;
qcom,display {
qcom,dma-heap-name = "qcom,display";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
qcom,max-align = <9>;
memory-region = <&non_secure_display_memory>;
};
qcom,secure_cdsp {
qcom,dma-heap-name = "qcom,cma-secure-cdsp";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&cdsp_secure_heap_cma>;
};
qcom,qseecom {
qcom,dma-heap-name = "qcom,qseecom";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_mem>;
};
qcom,qseecom_ta {
qcom,dma-heap-name = "qcom,qseecom-ta";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_ta_mem>;
};
};
};

18
qcom/kera-mtp-qca6750-qmp1000-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-mtp-qca6750-qmp1000.dtsi"
#include "kera-pm7550ba.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera MTP + QCA6750 + QMP1000 + UFS3";
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
"qcom,mtp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x30008 0>;
};

7
qcom/kera-mtp-qca6750-qmp1000.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-mtp.dtsi"
#include "kera_ufs3.dtsi"

18
qcom/kera-mtp-qca6750-ufs3-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-mtp-qca6750-ufs3.dtsi"
#include "kera-pm7550ba.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera MTP + QCA6750 + UFS3";
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
"qcom,mtp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x20008 0>;
};

7
qcom/kera-mtp-qca6750-ufs3.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-mtp.dtsi"
#include "kera_ufs3.dtsi"

18
qcom/kera-mtp-qca6750-ufs4-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-mtp-qca6750-ufs4.dtsi"
#include "kera-pm7550ba.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera MTP + QCA6750 + UFS4";
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
"qcom,mtp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x10008 0>;
};

7
qcom/kera-mtp-qca6750-ufs4.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-mtp.dtsi"
#include "kera_ufs4.dtsi"

18
qcom/kera-mtp-wcn7750-qmp1000-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-mtp-wcn7750-qmp1000.dtsi"
#include "kera-pm7550ba.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera MTP + WCN7750 + QMP1000 + UFS3";
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
"qcom,mtp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x30008 1>;
};

7
qcom/kera-mtp-wcn7750-qmp1000.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-mtp.dtsi"
#include "kera_ufs3.dtsi"

18
qcom/kera-mtp-wcn7750-ufs3-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-mtp-wcn7750-ufs3.dtsi"
#include "kera-pm7550ba.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera MTP + WCN7750 + UFS3";
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
"qcom,mtp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x20008 1>;
};

7
qcom/kera-mtp-wcn7750-ufs3.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-mtp.dtsi"
#include "kera_ufs3.dtsi"

19
qcom/kera-mtp-wcn7750-ufs4-overlay.dts Normal file
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@@ -0,0 +1,19 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-mtp-wcn7750-ufs4.dtsi"
#include "kera-pm7550ba.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera MTP + WCN7750 + UFS4";
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
"qcom,mtp";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x10008 1>;
};

7
qcom/kera-mtp-wcn7750-ufs4.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-mtp.dtsi"
#include "kera_ufs4.dtsi"

79
qcom/kera-mtp.dtsi Normal file
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@@ -0,0 +1,79 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/qcom,gcc-kera.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include "pmk8550.dtsi"
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976270>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
qcom,uses_level_shifter;
status = "ok";
};
&wcd_usbss {
interrupt-parent = <&spmi_bus>;
interrupts = <0x0 0xb6 0x1 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "usb_wcd";
nvmem-cells = <&usb_mode>;
nvmem-cell-names = "usb_mode";
};
&qupv3_se8_spi {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,touch-active = "goodix,gt9916S";
qcom,la-vm;
goodix-berlin@0 {
compatible = "goodix,gt9916S";
reg = <0>;
spi-max-frequency = <1000000>;
interrupt-parent = <&tlmm>;
interrupts = <13 0x2008>;
goodix,reset-gpio = <&tlmm 16 0x00>;
goodix,irq-gpio = <&tlmm 13 0x2008>;
goodix,irq-flags = <2>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,firmware-name = "goodix_firmware_spi.bin";
goodix,config-name = "goodix_cfg_group_spi.bin";
goodix,avdd-name = "avdd";
goodix,iovdd-name = "iovdd";
avdd-supply = <&L22B>;
iovdd-supply = <&L8B>;
goodix,touch-type = "primary";
goodix,qts_en;
qts,trusted-touch-mode = "vm_mode";
qts,touch-environment = "pvm";
qts,trusted-touch-type = "primary";
qts,trusted-touch-spi-irq = <653>;
qts,trusted-touch-io-bases = <0xa90000>;
qts,trusted-touch-io-sizes = <0x1000>;
qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0
&tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>;
};
};

17
qcom/kera-oemvm-atp.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kera-oemvm.dtsi"
#include "kera-oemvm-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera OEMVM ATP";
compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap",
"qcom,atp";
qcom,board-id = <33 0>;
};

7
qcom/kera-oemvm-atp.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
};

17
qcom/kera-oemvm-cdp.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kera-oemvm.dtsi"
#include "kera-oemvm-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera OEMVM CDP";
compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap",
"qcom,cdp";
qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>;
};

7
qcom/kera-oemvm-cdp.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
};

16
qcom/kera-oemvm-mtp.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kera-oemvm.dtsi"
#include "kera-oemvm-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera OEMVM MTP";
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
"qcom,mtp";
qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, <0x30008 1>;
};

7
qcom/kera-oemvm-mtp.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
};

16
qcom/kera-oemvm-qrd.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kera-oemvm.dtsi"
#include "kera-oemvm-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera OEMVM QRD";
compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap",
"qcom,qrd";
qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>;
};

7
qcom/kera-oemvm-qrd.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
};

16
qcom/kera-oemvm-rcm.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kera-oemvm.dtsi"
#include "kera-oemvm-rcm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera OEMVM RCM";
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
"qcom,rcm";
qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, <0x30015 1>;
};

7
qcom/kera-oemvm-rcm.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
};

128
qcom/kera-oemvm.dtsi
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@@ -8,7 +8,7 @@
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
qcom,msm-id = <659 0x10000>;
qcom,msm-id = <659 0x10000>, <686 0x10000>;
interrupt-parent = <&vgic>;
chosen {
@@ -163,6 +163,67 @@
allocate-base;
};
mem-buf-message-queue-pair {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/membuf-msgq-pair";
message-size = <0x000000f0>;
queue-depth = <0x00000008>;
peer-default;
qcom,label = <0x000000C>;
};
test-dbl-oemvm {
vdevice-type = "doorbell";
generate = "/hypervisor/test-dbl-oemvm";
qcom,label = <0x5>;
peer-default;
};
test-dbl-oemvm-source {
vdevice-type = "doorbell-source";
generate = "/hypervisor/test-dbl-oemvm-source";
qcom,label = <0x5>;
peer-default;
};
test-msgq-oemvm {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/test-msgq-oemvm-pair";
message-size = <0xf0>;
queue-depth = <0x8>;
qcom,label = <0x5>;
peer-default;
};
test-large-dmabuf-oemvm {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/test-large-dmabuf-oemvm-pair";
message-size = <0xf0>;
queue-depth = <0x8>;
qcom,label = <0xe>;
peer-default;
};
msgqsock-msgq-pair {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/msgqsock-msgq-pair";
message-size = <0xf0>;
queue-depth = <0x8>;
peer = "vm-name:qcom,trustedvm";
qcom,label = <0x3>;
};
qrtr-shm {
vdevice-type = "shm-doorbell";
generate = "/hypervisor/qrtr-shm";
push-compatible = "qcom,qrtr-gunyah-gen";
peer-default;
memory {
qcom,label = <0x8>;
allocate-base;
};
};
};
};
@@ -206,10 +267,75 @@
clock-frequency = <19200000>;
};
qcom,mem-buf {
compatible = "qcom,mem-buf";
qcom,mem-buf-capabilities = "consumer";
qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */
qcom,vmid = <49>;
};
qcom,mem-buf-msgq {
compatible = "qcom,mem-buf-msgq";
qcom,msgq-names = "oem_vm";
};
virtio_mem_device {
compatible = "qcom,virtio-mem";
/* Must be memory_block_size_bytes() aligned */
qcom,max-size = <0x0 0x10000000>;
qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
qcom,block-size = <0x400000>;
};
qcom,test-dbl-oemvm {
compatible = "qcom,gh-dbl";
qcom,label = <0x5>;
};
qcom,test-msgq-oemvm {
compatible = "qcom,gh-msgq-test";
gunyah-label = <0x5>;
affinity = <0>;
};
qcom,test-large-dmabuf-oemvm {
compatible = "qcom,gh-large-dmabuf-test";
gunyah-label = <0xe>;
};
qcom,gh-qtimer@1742b000 {
compatible = "qcom,gh-qtmr";
reg = <0x1742b000 0x1000>;
reg-names = "qtmr-base";
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qcom,qtmr-intr";
qcom,secondary;
};
qcom_smcinvoke {
compatible = "qcom,smcinvoke";
};
qcom_mem_object {
compatible = "qcom,mem-object";
};
qmsgq-gunyah {
compatible = "qcom,qmsgq-gh";
msgq-label = <3>;
};
qcom,qrtr {
compatible = "qcom,qrtr";
qcom,node-id = <21>;
};
qrtr-gunyah {
compatible = "qcom,qrtr-gunyah";
gunyah-label = <8>;
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
qcom,custom-bridge-size = <512>;

1935
qcom/kera-pinctrl.dtsi
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67
qcom/kera-pm7550ba.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-pm7550ba.dtsi"
&pmic_glink_debug {
/delete-node/ i2c@104;
/delete-node/ spmi@200;
i2c@104 {
reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1500@69 {
compatible = "qcom,i2c-pmic";
reg = <0x69>;
qcom,can-sleep;
};
qcom,smb1500@68 {
compatible = "qcom,i2c-pmic";
reg = <0x68>;
qcom,can-sleep;
};
};
};
&pmic_glink_adc {
/delete-node/ smb1398_1_iin;
/delete-node/ smb1398_1_ichg;
/delete-node/ smb1398_1_die_temp;
smb1500_1_iin {
reg = <0x1046901>;
label = "smb1393_1_iin";
};
smb1500_1_ichg {
reg = <0x1046902>;
label = "smb1393_1_ichg";
};
smb1500_1_die_temp {
reg = <0x1046903>;
label = "smb1393_1_die_temp";
};
smb1500_2_iin {
reg = <0x1046801>;
label = "smb1393_2_iin";
};
smb1500_2_ichg {
reg = <0x1046802>;
label = "smb1393_2_ichg";
};
smb1500_2_die_temp {
reg = <0x1046803>;
label = "smb1393_2_die_temp";
};
};

25
qcom/kera-pmic-overlay.dtsi Normal file
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@@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-pmic-overlay.dtsi"
&pm8550ve_f {
status = "disabled";
};
&pm8550ve_f_temp_alarm {
status = "disabled";
};
&pm8550ve_f_tz {
status = "disabled";
};
&pmk8550_sdam_1 {
ufs_dev: ufs_dev@af {
reg = <0xaf 0x1>;
bits = <0 0>;
};
};

4
qcom/kera-pmiv0102.dtsi
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@@ -10,7 +10,5 @@
};
&pmiv010x_amoled_ecm {
status = "ok"
status = "ok";
};

17
qcom/kera-qrd-wcn7750-ufs2-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-qrd-wcn7750-ufs2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera QRD + WCN7750 + UFS2";
compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap",
"qcom,qrd";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x3000B 0>;
};

7
qcom/kera-qrd-wcn7750-ufs2.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-qrd.dtsi"
#include "kera_ufs2.dtsi"

17
qcom/kera-qrd-wcn7750-ufs3-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-qrd-wcn7750-ufs3.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera QRD + WCN7750 + UFS3";
compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap",
"qcom,qrd";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x2000B 0>;
};

7
qcom/kera-qrd-wcn7750-ufs3.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-qrd.dtsi"
#include "kera_ufs3.dtsi"

18
qcom/kera-qrd-wcn7750-ufs4-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-qrd-wcn7750-ufs4.dtsi"
#include "kera-pmiv0102.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera QRD + WCN7750 + UFS4";
compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap",
"qcom,qrd";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x1000B 0>;
};

7
qcom/kera-qrd-wcn7750-ufs4.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-qrd.dtsi"
#include "kera_ufs4.dtsi"

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@@ -0,0 +1,108 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976270>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
qcom,uses_level_shifter;
status = "ok";
};
&qupv3_se7_i2c {
status = "ok";
fsa4480: fsa4480@42 {
compatible = "qcom,fsa4480-i2c";
reg = <0x42>;
};
};
&qupv3_se8_spi {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,touch-active = "goodix,gt9916S";
qcom,la-vm;
goodix-berlin@0 {
compatible = "goodix,gt9916S";
reg = <0>;
spi-max-frequency = <1000000>;
interrupt-parent = <&tlmm>;
interrupts = <13 0x2008>;
goodix,reset-gpio = <&tlmm 16 0x00>;
goodix,irq-gpio = <&tlmm 13 0x2008>;
goodix,irq-flags = <2>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,firmware-name = "goodix_firmware_spi.bin";
goodix,config-name = "goodix_cfg_group_spi.bin";
goodix,avdd-name = "avdd";
goodix,iovdd-name = "iovdd";
avdd-supply = <&L22B>;
iovdd-supply = <&L8B>;
goodix,touch-type = "primary";
goodix,qts_en;
qts,trusted-touch-mode = "vm_mode";
qts,touch-environment = "pvm";
qts,trusted-touch-type = "primary";
qts,trusted-touch-spi-irq = <653>;
qts,trusted-touch-io-bases = <0xa90000>;
qts,trusted-touch-io-sizes = <0x1000>;
qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0
&tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>;
};
};
&pmic_glink_debug {
i2c@104 {
reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1393@34 {
compatible = "qcom,i2c-pmic";
reg = <0x34>;
qcom,can-sleep;
};
};
};
&pmic_glink_adc {
status = "ok";
smb1393_1_iin {
reg = <0x1043401>;
label = "smb1393_1_iin";
};
smb1393_1_ichg {
reg = <0x1043402>;
label = "smb1393_1_ichg";
};
smb1393_1_die_temp {
reg = <0x1043403>;
label = "smb1393_1_die_temp";
};
};

788
qcom/kera-qupv3.dtsi
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@@ -4,8 +4,452 @@
*/
&soc {
/* QUPv3_2 Wrapper Instance */
qupv3_2: qcom,qupv3_1_geni_se@8c0000 {
/* QUPv3 SE Instances
* Qup1 0: SE 0
* Qup1 1: SE 1
* Qup1 2: SE 2
* Qup1 3: SE 3
* Qup1 4: SE 4
* Qup1 5: SE 5
* Qup1 6: SE 6
* Qup1 7: SE 7
* Qup2 0: SE 8
* Qup2 1: SE 9
* Qup2 2: SE 10
* Qup2 3: SE 11
* Qup2 4: SE 12
* Qup2 5: SE 13
* Qup2 6: SE 14
* Qup2 7: SE 15
*/
qup1_gpi_iommu_region: qup1_gpi_iommu_region {
iommu-addresses = <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xFFE00000>;
};
/* GPI Instance */
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
reg = <0xa00000 0x60000>;
#dma-cells = <5>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0xb6 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x1e>;
qcom,ev-factor = <1>;
memory-region = <&qup1_gpi_iommu_region>;
qcom,gpi-ee-offset = <0x10000>;
dma-coherent;
status = "ok";
};
qup1_se_iommu_region: qup1_se_iommu_region {
iommu-addresses = <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>;
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0xa3 0x0>;
memory-region = <&qup1_se_iommu_region>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
ranges;
status = "ok";
qupv3_se0_i2c: i2c@a80000 {
compatible = "qcom,i2c-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
dmas = <&gpi_dma1 0 0 3 64 2>,
<&gpi_dma1 1 0 3 64 2>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se0_spi: spi@a80000 {
compatible = "qcom,spi-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
pinctrl-1 = <&qupv3_se0_spi_sleep>;
dmas = <&gpi_dma1 0 0 1 64 2>,
<&gpi_dma1 1 0 1 64 2>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se1_i2c: i2c@a84000 {
compatible = "qcom,i2c-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
dmas = <&gpi_dma1 0 1 3 64 0>,
<&gpi_dma1 1 1 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se1_spi: spi@a84000 {
compatible = "qcom,spi-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
dmas = <&gpi_dma1 0 1 1 64 0>,
<&gpi_dma1 1 1 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se2_i2c: i2c@a88000 {
compatible = "qcom,i2c-geni";
reg = <0xa88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
dmas = <&gpi_dma1 0 2 3 64 0>,
<&gpi_dma1 1 2 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se2_spi: spi@a88000 {
compatible = "qcom,spi-geni";
reg = <0xa88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
pinctrl-1 = <&qupv3_se2_spi_sleep>;
dmas = <&gpi_dma1 0 2 1 64 0>,
<&gpi_dma1 1 2 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se3_i2c: i2c@a8c000 {
compatible = "qcom,i2c-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
dmas = <&gpi_dma1 0 3 3 64 0>,
<&gpi_dma1 1 3 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se3_spi: spi@a8c000 {
compatible = "qcom,spi-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
<&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
pinctrl-1 = <&qupv3_se3_spi_sleep>;
dmas = <&gpi_dma1 0 3 1 64 0>,
<&gpi_dma1 1 3 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se4_i2c: i2c@a90000 {
compatible = "qcom,i2c-geni";
reg = <0xa90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
dmas = <&gpi_dma1 0 4 3 1024 0>,
<&gpi_dma1 1 4 3 1024 0>;
dma-names = "tx", "rx";
qcom,shared;
status = "disabled";
};
/* HS UART Instance */
qupv3_se5_4uart: qcom,qup_uart@a94000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0xa94000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 135 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
pinctrl-1 = <&qupv3_se5_cts>, <&qupv3_se5_rts>,
<&qupv3_se5_tx>, <&qupv3_se5_rx_active>;
pinctrl-2 = <&qupv3_se5_cts>, <&qupv3_se5_rts>,
<&qupv3_se5_tx>, <&qupv3_se5_rx_wake>;
pinctrl-3 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
qcom,wakeup-byte = <0xFD>;
qcom,suspend-ignore-children;
status = "disabled";
};
qupv3_se6_i2c: i2c@a98000 {
compatible = "qcom,i2c-geni";
reg = <0xa98000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
dmas = <&gpi_dma1 0 6 3 64 0>,
<&gpi_dma1 1 6 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se6_spi: spi@a98000 {
compatible = "qcom,spi-geni";
reg = <0xa98000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
pinctrl-1 = <&qupv3_se6_spi_sleep>;
dmas = <&gpi_dma1 0 6 1 64 0>,
<&gpi_dma1 1 6 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se7_i2c: i2c@a9c000 {
compatible = "qcom,i2c-geni";
reg = <0xa9c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>;
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
dmas = <&gpi_dma1 0 7 3 64 0>,
<&gpi_dma1 1 7 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se7_spi: spi@a9c000 {
compatible = "qcom,spi-geni";
reg = <0xa9c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>,
<&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>;
pinctrl-1 = <&qupv3_se7_spi_sleep>;
dmas = <&gpi_dma1 0 7 1 64 0>,
<&gpi_dma1 1 7 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
};
qup2_gpi_iommu_region: qup2_gpi_iommu_region {
iommu-addresses = <&gpi_dma2 0x0 0x100000>, <&gpi_dma2 0x200000 0xFFE00000>;
};
/* GPI Instance */
gpi_dma2: qcom,gpi-dma@800000 {
compatible = "qcom,gpi-dma";
reg = <0x800000 0x60000>;
#dma-cells = <5>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x436 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x1e>;
qcom,ev-factor = <1>;
memory-region = <&qup2_gpi_iommu_region>;
qcom,gpi-ee-offset = <0x10000>;
dma-coherent;
status = "ok";
};
qup2_se_iommu_region: qup2_se_iommu_region {
iommu-addresses = <&qupv3_2 0x0 0x40000000>, <&qupv3_2 0x50000000 0xb0000000>;
};
/* QUPv3_2 wrapper instance */
qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x8c0000 0x2000>;
#address-cells = <1>;
@@ -13,9 +457,250 @@
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x423 0x0>;
memory-region = <&qup2_se_iommu_region>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
ranges;
status = "ok";
qupv3_se8_i2c: i2c@880000 {
compatible = "qcom,i2c-geni";
reg = <0x880000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
dmas = <&gpi_dma2 0 0 3 64 2>,
<&gpi_dma2 1 0 3 64 2>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se8_spi: spi@880000 {
compatible = "qcom,spi-geni";
reg = <0x880000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
pinctrl-1 = <&qupv3_se8_spi_sleep>;
dmas = <&gpi_dma2 0 0 1 64 2>,
<&gpi_dma2 1 0 1 64 2>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se9_i2c: i2c@884000 {
compatible = "qcom,i2c-geni";
reg = <0x884000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
dmas = <&gpi_dma2 0 1 3 64 0>,
<&gpi_dma2 1 1 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se9_spi: spi@884000 {
compatible = "qcom,spi-geni";
reg = <0x884000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
<&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>;
pinctrl-1 = <&qupv3_se9_spi_sleep>;
dmas = <&gpi_dma2 0 1 1 64 0>,
<&gpi_dma2 1 1 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se10_i2c: i2c@888000 {
compatible = "qcom,i2c-geni";
reg = <0x888000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_i2c_sda_active>, <&qupv3_se10_i2c_scl_active>;
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
dmas = <&gpi_dma2 0 2 3 64 0>,
<&gpi_dma2 1 2 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se10_spi: spi@888000 {
compatible = "qcom,spi-geni";
reg = <0x888000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se10_spi_mosi_active>, <&qupv3_se10_spi_miso_active>,
<&qupv3_se10_spi_clk_active>, <&qupv3_se10_spi_cs_active>;
pinctrl-1 = <&qupv3_se10_spi_sleep>;
dmas = <&gpi_dma2 0 2 1 64 0>,
<&gpi_dma2 1 2 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se11_i2c: i2c@88c000 {
compatible = "qcom,i2c-geni";
reg = <0x88c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se11_i2c_sda_active>, <&qupv3_se11_i2c_scl_active>;
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
dmas = <&gpi_dma2 0 3 3 64 0>,
<&gpi_dma2 1 3 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se11_spi: spi@88c000 {
compatible = "qcom,spi-geni";
reg = <0x88c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se11_spi_mosi_active>, <&qupv3_se11_spi_miso_active>,
<&qupv3_se11_spi_clk_active>, <&qupv3_se11_spi_cs_active>;
pinctrl-1 = <&qupv3_se11_spi_sleep>;
dmas = <&gpi_dma2 0 3 1 64 0>,
<&gpi_dma2 1 3 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se12_i2c: i2c@890000 {
compatible = "qcom,i2c-geni";
reg = <0x890000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_i2c_sda_active>, <&qupv3_se12_i2c_scl_active>;
pinctrl-1 = <&qupv3_se12_i2c_sleep>;
dmas = <&gpi_dma2 0 4 3 64 0>,
<&gpi_dma2 1 4 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se12_spi: spi@890000 {
compatible = "qcom,spi-geni";
reg = <0x890000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se12_spi_mosi_active>, <&qupv3_se12_spi_miso_active>,
<&qupv3_se12_spi_clk_active>, <&qupv3_se12_spi_cs_active>;
pinctrl-1 = <&qupv3_se12_spi_sleep>;
dmas = <&gpi_dma2 0 4 1 64 0>,
<&gpi_dma2 1 4 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
/* Debug UART Instance */
qupv3_se13_2uart: qcom,qup_uart@894000 {
compatible = "qcom,geni-debug-uart";
@@ -24,10 +709,109 @@
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se13_2uart_tx_active>, <&qupv3_se13_2uart_rx_active>;
pinctrl-1 = <&qupv3_se13_2uart_sleep>;
status = "disabled";
};
qupv3_se14_i2c: i2c@898000 {
compatible = "qcom,i2c-geni";
reg = <0x898000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se14_i2c_sda_active>, <&qupv3_se14_i2c_scl_active>;
pinctrl-1 = <&qupv3_se14_i2c_sleep>;
dmas = <&gpi_dma2 0 6 3 64 0>,
<&gpi_dma2 1 6 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se14_spi: spi@898000 {
compatible = "qcom,spi-geni";
reg = <0x898000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se14_spi_mosi_active>, <&qupv3_se14_spi_miso_active>,
<&qupv3_se14_spi_clk_active>, <&qupv3_se14_spi_cs_active>;
pinctrl-1 = <&qupv3_se14_spi_sleep>;
dmas = <&gpi_dma2 0 6 1 64 0>,
<&gpi_dma2 1 6 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se15_i2c: i2c@89c000 {
compatible = "qcom,i2c-geni";
reg = <0x89c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>;
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
dmas = <&gpi_dma2 0 7 3 64 0>,
<&gpi_dma2 1 7 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se15_spi: spi@89c000 {
compatible = "qcom,spi-geni";
reg = <0x89c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>,
<&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>;
pinctrl-1 = <&qupv3_se15_spi_sleep>;
dmas = <&gpi_dma2 0 7 1 64 0>,
<&gpi_dma2 1 7 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
};
};

18
qcom/kera-rcm-qca6750-ufs2-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-rcm-qca6750-ufs2.dtsi"
#include "kera-pmiv0102.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera RCM + QCA6750 + UFS2";
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
"qcom,rcm";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x30015 0>;
};

7
qcom/kera-rcm-qca6750-ufs2.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-rcm.dtsi"
#include "kera_ufs2.dtsi"

18
qcom/kera-rcm-qca6750-ufs3-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-rcm-qca6750-ufs3.dtsi"
#include "kera-pmiv0102.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera RCM + QCA6750 + UFS3";
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
"qcom,rcm";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x20015 0>;
};

7
qcom/kera-rcm-qca6750-ufs3.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-rcm.dtsi"
#include "kera_ufs3.dtsi"

18
qcom/kera-rcm-qca6750-ufs4-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-rcm-qca6750-ufs4.dtsi"
#include "kera-pmiv0102.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera RCM + QCA6750 + UFS4";
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
"qcom,rcm";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x10015 0>;
};

7
qcom/kera-rcm-qca6750-ufs4.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-rcm.dtsi"
#include "kera_ufs4.dtsi"

18
qcom/kera-rcm-wcn7750-ufs2-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-rcm-wcn7750-ufs2.dtsi"
#include "kera-pmiv0102.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera RCM + WCN7750 + UFS2";
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
"qcom,rcm";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x30015 1>;
};

7
qcom/kera-rcm-wcn7750-ufs2.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-rcm.dtsi"
#include "kera_ufs2.dtsi"

18
qcom/kera-rcm-wcn7750-ufs3-overlay.dts Normal file
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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-rcm-wcn7750-ufs3.dtsi"
#include "kera-pmiv0102.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KERA RCM + WCN7750 + UFS3";
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
"qcom,rcm";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x20015 1>;
};

7
qcom/kera-rcm-wcn7750-ufs3.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-rcm.dtsi"
#include "kera_ufs3.dtsi"

17
qcom/kera-rcm-wcn7750-ufs4-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "kera-rcm-wcn7750-ufs4.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera RCM + WCN7750 + UFS4";
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
"qcom,rcm";
qcom,msm-id = <686 0x10000>, <659 0x10000>;
qcom,board-id = <0x10015 1>;
};

7
qcom/kera-rcm-wcn7750-ufs4.dtsi Normal file
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera-rcm.dtsi"
#include "kera_ufs4.dtsi"

25
qcom/kera-rcm.dtsi Normal file
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@@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976270>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
qcom,uses_level_shifter;
status = "ok";
};

1160
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File diff suppressed because it is too large Load Diff

4
qcom/kera-rumi.dtsi
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@@ -19,10 +19,6 @@
};
&soc {
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
usb_emuphy: phy@a784000 {
compatible = "qcom,usb-emu-phy";
reg = <0x0a784000 0x9500>;

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305
qcom/kera-usb.dtsi
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@@ -3,14 +3,19 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-kera.h>
#include <dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h>
&soc {
usb0: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0xa600000 0x100000>;
reg-names = "core_base";
reg = <0xa600000 0x100000>,
<0x1fc6000 0x4>;
reg-names = "core_base",
"tcsr_dyn_en_dis";
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
@@ -25,23 +30,50 @@
resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event_irq";
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_RISING>,
<&pdc 15 IRQ_TYPE_EDGE_RISING>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event_irq", "dp_hs_phy_irq",
"dm_hs_phy_irq", "ss_phy_irq";
qcom,dis-sending-cm-l1-quirk;
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,core-clk-rate-disconnected = <133333333>;
dwc3@a600000 {
qcom,use-pdc-interrupts;
qcom,use-eusb2-phy;
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
qcom,num-gsi-evt-buffs = <0x3>;
qcom,gsi-reg-offset =
<0x0fc /* GSI_GENERAL_CFG */
0x110 /* GSI_DBL_ADDR_L */
0x120 /* GSI_DBL_ADDR_H */
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
dummy-supply = <&apps_smmu>;
dwc3_0: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xd93c>;
reg = <0x0 0xa600000 0x0 0xd93c>;
iommus = <&apps_smmu 0x40 0x0>;
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
memory-region = <&dwc3_mem_region>;
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb_nop_phy>, <&usb_qmp_dp_phy>;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
@@ -51,10 +83,261 @@
snps,dis_u2_susphy_quirk;
snps,ssp-u3-u0-quirk;
tx-fifo-resize;
dr_mode = "otg";
maximum-speed = "high-speed";
dr_mode = "peripheral";
maximum-speed = "super-speed-plus";
usb-role-switch;
};
};
dwc3_mem_region: dwc3_mem_region {
iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>,
<&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>;
};
/* USB port related High Speed PHY */
eusb2_phy0: hsphy@88e3000 {
compatible = "qcom,usb-snps-eusb2-phy";
reg = <0x88e3000 0x154>,
<0x088e2000 0x4>,
<0x0c278000 0x4>;
reg-names = "eusb2_phy_base",
"eud_enable_reg",
"eud_detect_reg";
vdd-supply = <&L7K>;
qcom,vdd-voltage-level = <0 880000 880000>;
vdda12-supply = <&L4B>;
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
<&tcsrcc TCSR_USB2_CLKREF_EN>;
clock-names = "ref_clk_src", "ref_clk";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
/* USB port related QMP USB DP Combo PHY */
usb_qmp_dp_phy: ssphy@88e8000 {
compatible = "qcom,usb-ssphy-qmp-dp-combo";
reg = <0x88e8000 0x3000>;
reg-names = "qmp_phy_base";
vdd-supply = <&L7K>;
qcom,vdd-voltage-level = <0 880000 880000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&L4B>;
usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
<&rpmhcc RPMH_CXO_PAD_CLK>,
<&tcsrcc TCSR_USB3_CLKREF_EN>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
"pipe_clk_ext_src", "ref_clk_src",
"ref_clk", "com_aux_clk";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "global_phy_reset", "phy_reset";
qcom,qmp-phy-reg-offset =
<USB3_DP_PCS_PCS_STATUS1
USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
USB3_DP_PCS_POWER_DOWN_CONTROL
USB3_DP_PCS_SW_RESET
USB3_DP_PCS_START_CONTROL
0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
USB3_DP_COM_POWER_DOWN_CTRL
USB3_DP_COM_SW_RESET
USB3_DP_COM_RESET_OVRD_CTRL
USB3_DP_COM_PHY_MODE_CTRL
USB3_DP_COM_TYPEC_CTRL
USB3_DP_PCS_AON_CLAMP_ENABLE>;
qcom,qmp-phy-init-seq =
/* <reg_offset, value> based on tsmcn3e_USB3_Gen2_Seq v1.6 */
<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xC0
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x01
USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x02
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x04
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x16
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x41
USB3_DP_QSERDES_COM_DEC_START_MODE1 0x41
USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x00
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x55
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x75
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x01
USB3_DP_QSERDES_COM_HSCLK_SEL_1 0x01
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x25
USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x5C
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x0F
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x5C
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x0F
USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xC0
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x01
USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x02
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x08
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x1A
USB3_DP_QSERDES_COM_DEC_START_MODE0 0x41
USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x00
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x75
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x01
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x25
USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x02
USB3_DP_QSERDES_COM_BG_TIMER 0x0A
USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
USB3_DP_QSERDES_COM_SSC_PER1 0x62
USB3_DP_QSERDES_COM_SSC_PER2 0x02
USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0C
USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x14
USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x04
USB3_DP_QSERDES_COM_CORE_CLK_EN 0x20
USB3_DP_QSERDES_COM_CMN_CONFIG_1 0x16
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0xB6
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x4B
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x37
USB3_DP_QSERDES_COM_ADDITIONAL_MISC 0x0C
USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09
USB3_DP_QSERDES_TXA_LANE_MODE_1 0xF5
USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F
USB3_DP_QSERDES_TXA_LANE_MODE_4 0x3F
USB3_DP_QSERDES_TXA_LANE_MODE_5 0x5F
USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A
USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x06
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x0A
USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
USB3_DP_QSERDES_RXA_GM_CAL 0x13
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x07
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x3F
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xFF
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xDF
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xED
USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x5C
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x9C
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x1D
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x09
USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
USB3_DP_QSERDES_RXA_VTH_CODE 0x10
USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1 0x14
USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM 0x08
USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09
USB3_DP_QSERDES_TXB_LANE_MODE_1 0xF5
USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F
USB3_DP_QSERDES_TXB_LANE_MODE_4 0x3F
USB3_DP_QSERDES_TXB_LANE_MODE_5 0x5F
USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x05
USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A
USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x06
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x0A
USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
USB3_DP_QSERDES_RXB_GM_CAL 0x13
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x07
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xDF
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xFD
USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x5C
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x9C
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x1D
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x09
USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
USB3_DP_QSERDES_RXB_VTH_CODE 0x10
USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1 0x14
USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM 0x08
USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4
USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89
USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
USB3_DP_PCS_RX_SIGDET_LVL 0x99
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
USB3_DP_PCS_CDR_RESET_TIME 0x0A
USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
USB3_DP_PCS_EQ_CONFIG1 0x4B
USB3_DP_PCS_EQ_CONFIG5 0x10
USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x68
USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00>;
};
usb_audio_qmi_dev {
compatible = "qcom,usb-audio-qmi-dev";
iommus = <&apps_smmu 0x100b 0x0>;
qcom,iommu-dma = "disabled";
qcom,usb-audio-stream-id = <0xb>;
qcom,usb-audio-intr-num = <2>;
};
};

17
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kera-vm.dtsi"
#include "kera-vm-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera SVM ATP";
compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap",
"qcom,atp";
qcom,board-id = <33 0>;
};

7
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
};

17
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kera-vm.dtsi"
#include "kera-vm-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera SVM CDP";
compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap",
"qcom,cdp";
qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>;
};

7
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
};

72
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@@ -0,0 +1,72 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
&soc {
qcom,dma-heaps {
compatible = "qcom,dma-heaps";
depends-on-supply = <&qcom_scm>;
qcom,tui {
qcom,dma-heap-name = "qcom,tui";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,tui_demura {
qcom,dma-heap-name = "qcom,tui_demura";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms1 {
qcom,dma-heap-name = "qcom,ms1";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms2 {
qcom,dma-heap-name = "qcom,ms2";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms3 {
qcom,dma-heap-name = "qcom,ms3";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms4 {
qcom,dma-heap-name = "qcom,ms4";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms5 {
qcom,dma-heap-name = "qcom,ms5";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms6 {
qcom,dma-heap-name = "qcom,ms6";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms7 {
qcom,dma-heap-name = "qcom,ms7";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,tui_test {
qcom,dma-heap-name = "qcom,tui_test";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
};
};

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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kera-vm.dtsi"
#include "kera-vm-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera SVM MTP";
compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap",
"qcom,mtp";
qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, <0x30008 1>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
};

16
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kera-vm.dtsi"
#include "kera-vm-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera SVM QRD";
compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap",
"qcom,qrd";
qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>;
};

7
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@@ -0,0 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
};

16
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kera-vm.dtsi"
#include "kera-vm-rcm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Kera SVM RCM";
compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap",
"qcom,rcm";
qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, <0x30015 1>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
};

462
qcom/kera-vm.dtsi
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@@ -5,15 +5,16 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-kera.h>
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
qcom,msm-id = <659 0x10000>;
qcom,msm-id = <659 0x10000>, <686 0x10000>;
interrupt-parent = <&vgic>;
chosen {
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force rcupdate.rcu_expedited=1 rcu_nocbs=0-1";
};
cpus {
@@ -52,6 +53,29 @@
};
};
dmesg-dump {
compatible = "qcom,dmesg-dump";
gunyah-label = <7>;
ddump-pubkey-size = <270>;
ddump-pubkey = /bits/ 8 <0x30 0x82 0x01 0x0a 0x02 0x82 0x01 0x01 0x00 0xe6 0x4b 0x31 0x82 0x61 0x14 0xf2
0xbe 0xd1 0xe4 0xde 0xe7 0xed 0xba 0x8f 0x3b 0x23 0x5f 0x7a 0xb8 0x16 0x40 0x96
0xae 0x77 0x5e 0x1b 0xf0 0x3f 0x39 0xab 0x69 0x90 0xb1 0xd4 0x70 0xcb 0x66 0xbc
0x41 0x08 0x1d 0x37 0xdb 0x49 0xc8 0x49 0x5b 0x99 0x5c 0x32 0xbe 0x62 0xd5 0xa7
0x3c 0x0f 0xa4 0x4b 0x43 0x49 0xdb 0x54 0x69 0x06 0x0c 0xe5 0x99 0xe5 0xf9 0x1e
0x25 0x84 0x17 0x47 0x62 0x2b 0x5d 0x0d 0xec 0x5e 0xc6 0xb5 0x86 0xb9 0x75 0x6d
0xfe 0x7d 0x35 0x4f 0x35 0xc1 0x48 0x10 0x75 0x4c 0x57 0x6b 0x46 0x4b 0xff 0x5b
0x52 0x22 0x40 0x2c 0xb0 0x47 0xe1 0x47 0xc4 0xe5 0x47 0x0c 0x56 0xe8 0x17 0xd0
0x7e 0xc3 0x4d 0x9f 0xea 0xd0 0xea 0x87 0xe5 0x51 0x39 0xe8 0x45 0x4c 0x54 0x27
0x9c 0x50 0x38 0xb7 0x72 0x93 0x12 0x0b 0xa1 0x2f 0x9e 0x04 0x92 0x20 0x6e 0x31
0x42 0x87 0xe1 0xfe 0x88 0x3f 0xe5 0x09 0xe1 0xf9 0xbe 0x44 0xc6 0xbf 0x10 0x79
0x36 0x47 0x7b 0xa0 0x8e 0x27 0x31 0xa3 0x70 0x69 0x01 0x54 0x92 0xf4 0x42 0xbd
0xcd 0x7e 0x79 0x2b 0x2c 0xe1 0xd4 0xba 0x6e 0x34 0xc6 0xe6 0xc6 0x5c 0x63 0xd0
0x7f 0x39 0x1f 0xe8 0x8d 0x67 0xe6 0x27 0x67 0x0d 0x16 0x57 0x94 0xd1 0xfb 0xdf
0xce 0xaf 0xfd 0x43 0xb3 0xbe 0x5d 0x83 0x4b 0x93 0x05 0xe8 0xdf 0x04 0xad 0xac
0xeb 0xa6 0x81 0xa7 0xd5 0x04 0x63 0xbf 0x83 0xb8 0x0c 0xbc 0x20 0x18 0xb5 0x50
0xd7 0x61 0x84 0x11 0xca 0x2d 0x22 0xb3 0x29 0x02 0x03 0x01 0x00 0x01>;
};
qcom,vm-config {
compatible = "qcom,vm-1.0";
vm-type = "aarch64-guest";
@@ -71,6 +95,10 @@
vm-attrs = "context-dump", "crash-restart";
iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0
0x0 0x407000 0x0 0x407000 0x0 0x1000 0x0>;
/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
* QUP1_SE4: GPII5 : IRQ_316
* QUP2_SE7: GPII5 : IRQ_625
@@ -187,6 +215,100 @@
allocate-base;
};
qrtr-shm {
vdevice-type = "shm-doorbell";
generate = "/hypervisor/qrtr-shm";
push-compatible = "qcom,qrtr-gunyah-gen";
peer-default;
memory {
qcom,label = <0x3>;
allocate-base;
};
};
msgqsock-msgq {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/msgqsock-msgq-pair";
message-size = <0xf0>;
queue-depth = <0x8>;
peer = "vm-name:qcom,oemvm";
qcom,label = <0x3>;
};
mem-buf-message-queue-pair {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/membuf-msgq-pair";
message-size = <0x000000f0>;
queue-depth = <0x00000008>;
peer-default;
qcom,label = <0x0000001>;
};
ddump-shm {
vdevice-type = "shm-doorbell";
generate = "/hypervisor/ddump-shm";
push-compatible = "qcom,ddump-gunyah-gen";
peer-default;
memory {
qcom,label = <0x7>;
allocate-base;
};
};
gunyah-panic-notifier-shm {
vdevice-type = "shm-doorbell";
generate = "/hypervisor/gpn-shm";
push-compatible = "qcom,gunyah-panic-gen";
peer-default;
memory {
qcom,label = <0x9>;
allocate-base;
};
};
gpiomem0 {
vdevice-type = "iomem";
patch = "/soc/tlmm-vm-mem-access";
push-compatible = "qcom,tlmm-vm-mem-access";
peer-default;
memory {
qcom,label = <0x8>;
qcom,mem-info-tag = <0x3>;
allocate-base;
};
};
test-dbl-tuivm {
vdevice-type = "doorbell";
generate = "/hypervisor/test-dbl-tuivm";
qcom,label = <0x4>;
peer-default;
};
test-dbl-tuivm-source {
vdevice-type = "doorbell-source";
generate = "/hypervisor/test-dbl-tuivm-source";
qcom,label = <0x4>;
peer-default;
};
test-msgq-tuivm {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/test-msgq-tuivm-pair";
message-size = <0xf0>;
queue-depth = <0x8>;
qcom,label = <0x4>;
peer-default;
};
test-large-dmabuf-tuivm {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/test-large-dmabuf-tuivm-pair";
message-size = <0xf0>;
queue-depth = <0x8>;
qcom,label = <0xd>;
peer-default;
};
};
};
@@ -216,11 +338,83 @@
wakeup-source;
};
vm_tlmm_irq: vm-tlmm-irq@0 {
compatible = "qcom,tlmm-vm-irq";
reg = <0x0 0x0>;
interrupt-controller;
#interrupt-cells = <2>;
};
tlmm: pinctrl@f000000 {
compatible = "qcom,kera-vm-tlmm";
reg = <0x0F000000 0x1000000>;
interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
/* Valid pins */
gpios = /bits/ 16 <17 121 12 127 0 1 2 3 16 13 28 29 30 31>;
};
tlmm-vm-mem-access {
compatible = "qcom,tlmm-vm-mem-access";
tlmm-vm-gpio-list = <&tlmm 17 0 &tlmm 121 0 &tlmm 12 0 &tlmm 127 0 &tlmm 0 0 &tlmm 1 0
&tlmm 2 0 &tlmm 3 0 &tlmm 16 0 &tlmm 13 0 &tlmm 28 0 &tlmm 29 0 &tlmm 30 0 &tlmm 31 0>;
};
tlmm-vm-test {
compatible = "qcom,tlmm-vm-test";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&qupv3_se1_7i2c_active>;
pinctrl-1 = <&qupv3_se1_7i2c_sleep>;
tlmm-vm-gpio-list = <&tlmm 17 0 &tlmm 121 0 &tlmm 12 0 &tlmm 127 0 &tlmm 0 0 &tlmm 1 0
&tlmm 2 0 &tlmm 3 0 &tlmm 16 0 &tlmm 13 0 &tlmm 28 0 &tlmm 29 0 &tlmm 30 0 &tlmm 31 0>;
};
pinctrl@f000000 {
qupv3_se1_7i2c_pins: qupv3_se1_7i2c_pins {
qupv3_se1_7i2c_active: qupv3_se1_7i2c_active {
mux {
pins = "gpio28";
function = "qup1_se0_l0";
};
config {
pins = "gpio28";
drive-strength = <2>;
bias-pull-up;
};
};
qupv3_se1_7i2c_sleep: qupv3_se1_7i2c_sleep {
mux {
pins = "gpio28";
function = "gpio";
};
config {
pins = "gpio28";
drive-strength = <2>;
};
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
ipcc_mproc_ns1: qcom,ipcc@407000 {
compatible = "qcom,ipcc";
reg = <0x407000 0x1000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
vgic: interrupt-controller@17100000 {
compatible = "arm,gic-v3";
interrupt-controller;
@@ -245,11 +439,275 @@
compatible = "qcom,smcinvoke";
};
qcom_mem_object {
compatible = "qcom,mem-object";
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
qcom,custom-bridge-size = <64>;
qcom,support-hypervisor;
};
qcom,gunyah-panic-notifier {
compatible = "qcom,gh-panic-notifier";
gunyah-label = <9>;
};
qcom,test-dbl-tuivm {
compatible = "qcom,gh-dbl";
qcom,label = <0x4>;
};
qcom,test-msgq-tuivm {
compatible = "qcom,gh-msgq-test";
gunyah-label = <0x4>;
affinity = <0>;
};
qcom,test-large-dmabuf-tuivm {
compatible = "qcom,gh-large-dmabuf-test";
gunyah-label = <0xd>;
};
qcom,gh-qtimer@1742b000 {
compatible = "qcom,gh-qtmr";
reg = <0x1742b000 0x1000>;
reg-names = "qtmr-base";
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qcom,qtmr-intr";
qcom,secondary;
};
qcom,mem-buf {
compatible = "qcom,mem-buf";
qcom,mem-buf-capabilities = "consumer";
qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */
qcom,vmid = <45>;
};
mem_buf_msgq: qcom,mem-buf-msgq {
compatible = "qcom,mem-buf-msgq";
qcom,msgq-names = "trusted_vm";
};
qmsgq-gunyah {
compatible = "qcom,qmsgq-gh";
msgq-label = <3>;
};
qrtr-gunyah {
compatible = "qcom,qrtr-gunyah";
gunyah-label = <3>;
};
virtio_mem_device {
compatible = "qcom,virtio-mem";
depends-on-supply = <&mem_buf_msgq>;
/* Must be memory_block_size_bytes() aligned */
qcom,max-size = <0x0 0x18000000>;
qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
qcom,block-size = <0x400000>;
qcom,initial-movable-zone-size = <0x2000000>;
};
/*
* QUP1 : SE0 - Secondary touch
* QUP2 : SE0 - Primary touch
*/
qup_iommu_group: qup_common_iommu_group {
iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>,
<&qupv3_1 0x00000000 0x00020000>,
<&gpi_dma2 0x00000000 0x00020000>,
<&qupv3_2 0x00000000 0x00020000>;
};
/* GPI Instance */
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
reg = <0xa00000 0x60000>;
#dma-cells = <5>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,static-gpii-mask = <0x20>;
qcom,gpii-mask = <0x0>;
qcom,ev-factor = <1>;
qcom,gpi-ee-offset = <0x10000>;
qcom,le-vm;
status = "ok";
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
ranges;
status = "ok";
/* Secondary Tounch */
qupv3_se0_i2c: i2c@a80000 {
compatible = "qcom,i2c-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma1 0 0 3 64 0xc>,
<&gpi_dma1 1 0 3 64 0xc>;
dma-names = "tx", "rx";
qcom,le-vm;
status = "disabled";
};
/* Secondary Touch */
qupv3_se0_spi: spi@a80000 {
compatible = "qcom,spi-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
dmas = <&gpi_dma1 0 0 1 64 0xc>,
<&gpi_dma1 1 0 1 64 0xc>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,le-vm;
status = "disabled";
};
};
/* GPI Instance */
gpi_dma2: qcom,gpi-dma@800000 {
compatible = "qcom,gpi-dma";
reg = <0x800000 0x60000>;
#dma-cells = <5>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,static-gpii-mask = <0x20>;
qcom,gpii-mask = <0x0>;
qcom,ev-factor = <1>;
qcom,gpi-ee-offset = <0x10000>;
qcom,le-vm;
status = "ok";
};
/* QUPv3_2 wrapper instance */
qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x8c0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
ranges;
status = "ok";
/* Touchscreen I2C Instance */
qupv3_se8_i2c: i2c@880000 {
compatible = "qcom,i2c-geni";
reg = <0x880000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma2 0 0 3 64 0xc>,
<&gpi_dma2 1 0 3 64 0xc>;
dma-names = "tx", "rx";
qcom,le-vm;
status = "disabled";
};
/* Touchscreen SPI Instance */
qupv3_se8_spi: spi@880000 {
compatible = "qcom,spi-geni";
reg = <0x880000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
dmas = <&gpi_dma2 0 0 1 64 0xc>,
<&gpi_dma2 1 0 1 64 0xc>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,le-vm;
status = "disabled";
};
};
qti,smmu-proxy {
compatible = "smmu-proxy-receiver";
};
qti,smmu-proxy-camera-cb {
compatible = "smmu-proxy-cb";
qti,cb-id = <QTI_SMMU_PROXY_CAMERA_CB>;
qcom,iommu-defer-smr-config;
iommus = <&apps_smmu 0x1810 0x20>,
<&apps_smmu 0x1C10 0x0>,
<&apps_smmu 0x18F0 0x0>;
dma-coherent;
};
qti,smmu-proxy-display-cb {
compatible = "smmu-proxy-cb";
qti,cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
qcom,iommu-defer-smr-config;
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
iommus = <&apps_smmu 0x801 0x0>;
dma-coherent;
};
qti,smmu-proxy-eva-cb {
compatible = "smmu-proxy-cb";
qti,cb-id = <QTI_SMMU_PROXY_EVA_CB>;
qcom,iommu-defer-smr-config;
qcom,iommu-dma-addr-pool = <0x00000000 0xffffffff>;
iommus = <&apps_smmu 0x1927 0x0>;
dma-coherent;
};
};
#include "msm-arm-smmu-kera-vm.dtsi"
#include "kera-vm-dma-heaps.dtsi"

22
qcom/kera-walt.dtsi Normal file
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@@ -0,0 +1,22 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
walt {
#address-cells = <1>;
#size-cells = <1>;
ranges;
cycle-cntr@17d91000 {
compatible = "qcom,epss";
reg = <0x17D91000 0x1000>,
<0x17D92000 0x1000>,
<0x17D93000 0x1000>;
reg-names = "freq-domain0",
"freq-domain1",
"freq-domain2";
};
};
};

1048
qcom/kera.dtsi
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File diff suppressed because it is too large Load Diff

44
qcom/kera_ufs2.dtsi Normal file
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@@ -0,0 +1,44 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-niobe";
/* VDDA_UFS_CORE */
vdda-phy-supply = <&L6B>;
vdda-phy-max-microamp = <211860>;
/* VDDA_UFS_0_1P2 */
vdda-pll-supply = <&L4B>;
vdda-pll-max-microamp = <18330>;
/* Phy GDSC for VDD_MX, always on */
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
/* Qref power supply, Refer Qref diagram */
vdda-qref-supply = <&L2B>;
vdda-qref-max-microamp = <1890>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L12B>;
vcc-max-microamp = <800000>;
vccq2-supply = <&L1D>;
vccq2-max-microamp = <750000>;
/* VDD_PX10 is voted for the ufs_reset_n */
qcom,vddp-ref-clk-supply = <&L3G>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq2-parent-supply = <&S1B>;
qcom,vccq2-parent-max-microamp = <210000>;
status = "ok";
};

44
qcom/kera_ufs3.dtsi Normal file
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@@ -0,0 +1,44 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-niobe";
/* VDDA_UFS_CORE */
vdda-phy-supply = <&L6B>;
vdda-phy-max-microamp = <211860>;
/* VDDA_UFS_0_1P2 */
vdda-pll-supply = <&L4B>;
vdda-pll-max-microamp = <18330>;
/* Phy GDSC for VDD_MX, always on */
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
/* Qref power supply, Refer Qref diagram */
vdda-qref-supply = <&L2B>;
vdda-qref-max-microamp = <1890>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L12B>;
vcc-max-microamp = <800000>;
vccq-supply = <&L1D>;
vccq-max-microamp = <750000>;
/* VDD_PX10 is voted for the ufs_reset_n */
qcom,vddp-ref-clk-supply = <&L3G>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&S2B>;
qcom,vccq-parent-max-microamp = <210000>;
status = "ok";
};

49
qcom/kera_ufs4.dtsi Normal file
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@@ -0,0 +1,49 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-niobe";
/* VDDA_UFS_CORE */
vdda-phy-supply = <&L6B>;
vdda-phy-max-microamp = <211860>;
/*
* Platforms supporting Gear 5 && Rate B require a different
* voltage supply. Check the Power Grid document.
*/
vdda-phy-min-microvolt = <912000>;
/* VDDA_UFS_0_1P2 */
vdda-pll-supply = <&L4B>;
vdda-pll-max-microamp = <18330>;
/* Phy GDSC for VDD_MX, always on */
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
/* Qref power supply, Refer Qref diagram */
vdda-qref-supply = <&L2B>;
vdda-qref-max-microamp = <1890>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L12B>;
vcc-max-microamp = <1200000>;
vccq-supply = <&L1D>;
vccq-max-microamp = <1200000>;
/* VDD_PX10 is voted for the ufs_reset_n */
qcom,vddp-ref-clk-supply = <&L3G>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&S2B>;
qcom,vccq-parent-max-microamp = <210000>;
status = "ok";
};

14
qcom/kerap.dts Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "kerap.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KeraP SoC";
compatible = "qcom,kerap";
qcom,board-id = <0 0>;
};

12
qcom/kerap.dtsi Normal file
View File

@@ -0,0 +1,12 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kera.dtsi"
/ {
model = "Qualcomm Technologies, Inc. KeraP SoC";
compatible = "qcom,kerap";
qcom,msm-id = <686 0x10000>;
};

1
qcom/monaco-qupv3.dtsi
View File

@@ -101,6 +101,7 @@
pinctrl-3 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
qcom,wakeup-byte = <0xFD>;
qcom,suspend-ignore-children;
status = "disabled";
};

2
qcom/parrot.dtsi
View File

@@ -29,7 +29,7 @@
chosen: chosen {
stdout-path = "/soc/qcom,qup_uart@98c000:115200n8";
bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on cgroup_disable=pressure";
bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on cgroup_disable=pressure fw_devlink.strict=1";
};
memory { device_type = "memory"; reg = <0 0 0 0>; };

48
qcom/platform_map.bzl
View File

@@ -77,6 +77,10 @@ _platform_map = {
"dtb_list": [
{"name": "tuna.dtb"},
{"name": "tuna7.dtb"},
{
"name": "tunap.dtb",
"apq": True,
},
],
"dtbo_list": [
{
@@ -87,6 +91,7 @@ _platform_map = {
{"name": "tuna-cdp-overlay.dtbo"},
{"name": "tuna-mtp-kiwi-harmonium-overlay.dtbo"},
{"name": "tuna-mtp-kiwi-overlay.dtbo"},
{"name": "tuna-mtp-kiwi-pmd802x-overlay.dtbo"},
{"name": "tuna-mtp-nfc-overlay.dtbo"},
{"name": "tuna-mtp-overlay.dtbo"},
{"name": "tuna-mtp-qmp1000-overlay.dtbo"},
@@ -98,12 +103,35 @@ _platform_map = {
"kera": {
"dtb_list": [
{"name": "kera.dtb"},
{
"name": "kerap.dtb",
"apq": True,
},
],
"dtbo_list": [
{
"name": "kera-rumi-overlay.dtbo",
"apq": False,
},
{"name": "kera-atp-overlay.dtbo"},
{"name": "kera-mtp-qca6750-ufs4-overlay.dtbo"},
{"name": "kera-mtp-qca6750-ufs3-overlay.dtbo"},
{"name": "kera-mtp-qca6750-qmp1000-overlay.dtbo"},
{"name": "kera-mtp-wcn7750-qmp1000-overlay.dtbo"},
{"name": "kera-mtp-wcn7750-ufs3-overlay.dtbo"},
{"name": "kera-mtp-wcn7750-ufs4-overlay.dtbo"},
{"name": "kera-cdp-qca6750-ufs2-overlay.dtbo"},
{"name": "kera-cdp-qca6750-ufs3-overlay.dtbo"},
{"name": "kera-cdp-qca6750-ufs4-overlay.dtbo"},
{"name": "kera-qrd-wcn7750-ufs4-overlay.dtbo"},
{"name": "kera-qrd-wcn7750-ufs2-overlay.dtbo"},
{"name": "kera-qrd-wcn7750-ufs3-overlay.dtbo"},
{"name": "kera-rcm-qca6750-ufs4-overlay.dtbo"},
{"name": "kera-rcm-qca6750-ufs2-overlay.dtbo"},
{"name": "kera-rcm-qca6750-ufs3-overlay.dtbo"},
{"name": "kera-rcm-wcn7750-ufs2-overlay.dtbo"},
{"name": "kera-rcm-wcn7750-ufs3-overlay.dtbo"},
{"name": "kera-rcm-wcn7750-ufs4-overlay.dtbo"},
],
},
"parrot-tuivm": {
@@ -215,14 +243,34 @@ _platform_map = {
"kera-tuivm": {
"dtb_list": [
# keep sorted
{"name": "kera-oemvm-atp.dtb"},
{"name": "kera-oemvm-cdp.dtb"},
{"name": "kera-oemvm-mtp.dtb"},
{"name": "kera-oemvm-qrd.dtb"},
{"name": "kera-oemvm-rcm.dtb"},
{"name": "kera-oemvm-rumi.dtb"},
{"name": "kera-vm-atp.dtb"},
{"name": "kera-vm-cdp.dtb"},
{"name": "kera-vm-mtp.dtb"},
{"name": "kera-vm-qrd.dtb"},
{"name": "kera-vm-rcm.dtb"},
{"name": "kera-vm-rumi.dtb"},
],
},
"kera-oemvm": {
"dtb_list": [
# keep sorted
{"name": "kera-oemvm-atp.dtb"},
{"name": "kera-oemvm-cdp.dtb"},
{"name": "kera-oemvm-mtp.dtb"},
{"name": "kera-oemvm-qrd.dtb"},
{"name": "kera-oemvm-rcm.dtb"},
{"name": "kera-oemvm-rumi.dtb"},
{"name": "kera-vm-atp.dtb"},
{"name": "kera-vm-cdp.dtb"},
{"name": "kera-vm-mtp.dtb"},
{"name": "kera-vm-qrd.dtb"},
{"name": "kera-vm-rcm.dtb"},
{"name": "kera-vm-rumi.dtb"},
],
},

26
qcom/pm7550ba.dtsi
View File

@@ -195,6 +195,32 @@
};
};
vbat {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm7550ba_bcl 2>;
trips {
vbat_lvl0:vbat-lvl0 {
temperature = <2800>;
hysteresis = <100>;
type = "passive";
};
vbat_lvl1:vbat-lvl1 {
temperature = <2600>;
hysteresis = <100>;
type = "passive";
};
vbat_lvl2:vbat-lvl2 {
temperature = <2300>;
hysteresis = <100>;
type = "passive";
};
};
};
pm7550ba-bcl-lvl0 {
polling-delay-passive = <50>;
polling-delay = <0>;

176
qcom/pmiv010x.dtsi
View File

@@ -97,6 +97,24 @@
<0x7 0x7d 0x1 IRQ_TYPE_EDGE_RISING>,
<0x7 0x98 0x1 IRQ_TYPE_EDGE_RISING>;
};
pmiv010x_bcl: bcl@4700 {
compatible = "qcom,pmiv010x-bcl-v5";
reg = <0x4700 0x100>;
interrupts = <0x7 0x47 0x0 IRQ_TYPE_NONE>,
<0x7 0x47 0x1 IRQ_TYPE_NONE>,
<0x7 0x47 0x2 IRQ_TYPE_NONE>;
interrupt-names = "bcl-lvl0",
"bcl-lvl1",
"bcl-lvl2";
qcom,pmic7-threshold;
#thermal-sensor-cells = <1>;
};
bcl_soc:bcl-soc {
compatible = "qcom,msm-bcl-soc";
#thermal-sensor-cells = <0>;
};
};
};
@@ -126,4 +144,162 @@
};
};
};
pmiv010x-ibat-lvl0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmiv010x_bcl 0>;
trips {
ibat_lvl0:ibat-lvl0 {
temperature = <7000>;
hysteresis = <200>;
type = "passive";
};
};
};
pmiv010x-ibat-lvl1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmiv010x_bcl 1>;
trips {
ibat_lvl1:ibat-lvl1 {
temperature = <9000>;
hysteresis = <200>;
type = "passive";
};
};
};
pmiv010x-bcl-lvl0 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmiv010x_bcl 5>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl0: b-bcl-lvl0 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pmiv010x-bcl-lvl1 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmiv010x_bcl 6>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl1: b-bcl-lvl1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pmiv010x-bcl-lvl2 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmiv010x_bcl 7>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl2: b-bcl-lvl2 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
socd {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&bcl_soc>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
socd_trip:socd-trip {
temperature = <90>;
hysteresis = <0>;
type = "passive";
};
};
};
vbat {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmiv010x_bcl 2>;
trips {
vbat_lvl0:vbat-lvl0 {
temperature = <2800>;
hysteresis = <100>;
type = "passive";
};
vbat_lvl1:vbat-lvl1 {
temperature = <2600>;
hysteresis = <100>;
type = "passive";
};
vbat_lvl2:vbat-lvl2 {
temperature = <2300>;
hysteresis = <100>;
type = "passive";
};
};
};
};

2
qcom/pmxr2230.dtsi
View File

@@ -170,7 +170,7 @@
};
pmxr2230_bcl: bcl@4700 {
compatible = "qcom,bcl-v5";
compatible = "qcom,pm8550-bcl-v5";
reg = <0x4700 0x100>;
interrupts = <0x1 0x47 0x0 IRQ_TYPE_NONE>,
<0x1 0x47 0x1 IRQ_TYPE_NONE>,

8
qcom/ravelin-pinctrl.dtsi
View File

@@ -468,7 +468,7 @@
qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active {
mux {
pins = "gpio8";
function = "qup0_se4_l0_mira";
function = "qup0_se4_l0";
};
config {
@@ -481,7 +481,7 @@
qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active {
mux {
pins = "gpio9";
function = "qup0_se4_l1_mira";
function = "qup0_se4_l1";
};
config {
@@ -509,7 +509,7 @@
qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active {
mux {
pins = "gpio8";
function = "qup0_se4_l0_mira";
function = "qup0_se4_l0";
};
config {
@@ -522,7 +522,7 @@
qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active {
mux {
pins = "gpio9";
function = "qup0_se4_l1_mira";
function = "qup0_se4_l1";
};
config {

2
qcom/ravelin-vm.dtsi
View File

@@ -103,7 +103,7 @@
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,static-gpii-mask = <0x40>;
qcom,static-gpii-mask = <0x20>;
qcom,gpii-mask = <0x0>;
qcom,ev-factor = <2>;
qcom,gpi-ee-offset = <0x10000>;

2
qcom/ravelin.dtsi
View File

@@ -28,7 +28,7 @@
chosen: chosen {
stdout-path = "/soc/qcom,qup_uart@a88000:115200n8";
bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat";
bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat fw_devlink.strict=1";
};
memory { device_type = "memory"; reg = <0 0 0 0>; };

1
qcom/sdxkova-idp-m2.dts
View File

@@ -13,5 +13,6 @@
model = "Qualcomm Technologies, Inc. SDXKOVA IDP M2";
compatible = "qcom,sdxkova-idp",
"qcom,sdxkova", "qcom,idp";
qcom,msm-id = <556 0x10000>, <580 0x10000>, <609 0x10000>, <610 0x10000>;
qcom,board-id = <0x4020022 0x304>;
};

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