8e85f11afa
The vbus_dwc3-supply property in the device tree manages the 5V for USB host mode. It is designed for platforms with hardware VBUS detection based on a GPIO regulator, allowing the system to control the USB port power supply, enabling or disabling it in suspend/resume cases. Change-Id: Ic33147b08a8efd3a3fa015e6847e2874a83b386b Signed-off-by: Rajashekar kuruva <quic_kuruva@quicinc.com>
231 lines
6.5 KiB
YAML
231 lines
6.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/qcom,dwc-usb3-msm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SuperSpeed DWC3 USB SoC Controller Glue
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maintainers:
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- Wesley Cheng <quic_wcheng@quicinc.com>
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properties:
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compatible:
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items:
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- enum:
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- qcom,dwc-usb3-msm
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reg:
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description: Address and length of the register set for the device.
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minItems: 1
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maxItems: 2
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reg-names:
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minItems: 1
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items:
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- const: core_base
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- const: tcsr_dyn_en_dis
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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ranges: true
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interrupts:
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minItems: 1
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maxItems: 4
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interrupt-names:
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minItems: 1
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items:
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- const: pwr_event_irq
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- const: dp_hs_phy_irq
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- const: dm_hs_phy_irq
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- const: ss_phy_irq
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clocks:
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description: |
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A list of phandles to the controller clocks::
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- core_clk:: Master/Core Clock, >= 125 MHz for SS operation and
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>= 60MHz for HS operation.
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- iface_clk:: System bus AXI clock.
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- bus_aggr_clk:: Bus Aggregator clock.
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- utmi_clk:: Mock utmi clocks needed for ITP/SOF generation in host mode.
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- sleep_clk:: SLeep clock, used for wakeup when USB3 core goes to LPM(U3).
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minItems: 1
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maxItems: 9
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USB3_GDSC-supply:
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description: USB GDSC supply.
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vbus_dwc3-supply:
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description: Regulator supply for the VBUS 5V power for USB host mode.
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This is typically used when VBUS is controlled by a GPIO-based
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regulator to enable/disable USB port power.
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clock-names:
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minItems: 1
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items:
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- const: core_clk
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- const: iface_clk
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- const: bus_aggr_clk
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- const: utmi_clk
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- const: sleep_clk
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: core_reset
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interconnects:
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maxItems: 3
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interconnect-names:
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items:
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- const: usb-ddr
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- const: usb-ipa
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- const: ddr-usb
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qcom,use-pdc-interrupts:
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description: If present, interrupts used will be pdc based.
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type: boolean
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qcom,use-eusb2-phy:
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description: Indication of platform using eusb2 phys.
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type: boolean
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extcon:
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description: Phandles to external connector devices.
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Generally used to notify VBUS/ID/EUD state change.
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minItems: 1
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maxItems: 3
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qcom,dis-sending-cm-l1-quirk:
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description: disable cm l1.
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type: boolean
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qcom,sleep-clk-bcr:
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description: If present, use additional delay after BCR.
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type: boolean
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qcom,core-clk-rate:
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description: Core/Master clock rate.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,core-clk-rate-hs:
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description: Core/Master clock rate in HS.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,core-clk-rate-disconnected:
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description: Disconnected master/core clock rate.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,pm-qos-latency:
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description: QOS voting for usb.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,num-gsi-evt-buffs:
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description: Number of event buffers required for GSI.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,gsi-reg-offset:
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description: GSI register offsets.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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usb-role-switch:
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description: Indicator showing the Glue driver supports role switch.
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type: boolean
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# Required child node:
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patternProperties:
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"^usb@[0-9a-f]+$":
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$ref: snps,dwc3.yaml#
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unevaluatedProperties: false
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additionalProperties: false
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# Example MSM USB3.0 controller device node :
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/qcom,gcc-kalama.h>
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#include <dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h>
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#include <dt-bindings/interconnect/qcom,kalama.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xa600000 0x100000>,
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<0x1fc6000 0x4>;
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reg-names = "core_base", "tcsr_dyn_en_dis";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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vbus_dwc3-supply = <&usb0_vbus_reg>;
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 14 IRQ_TYPE_EDGE_RISING>,
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<&pdc 15 IRQ_TYPE_EDGE_RISING>,
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<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq", "dp_hs_phy_irq",
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"dm_hs_phy_irq", "ss_phy_irq";
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qcom,use-pdc-interrupts;
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qcom,use-eusb2-phy;
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qcom,dis-sending-cm-l1-quirk;
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,core-clk-rate-disconnected = <133333333>;
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qcom,pm-qos-latency = <2>;
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extcon = <&eud>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
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interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
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<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
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usb@a600000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a600000 0 0xcd00>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x740 0>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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};
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