6ee4081682
1. The high speed phy is required for USB to support HS usecases. Add eusb node on tuna which includes the necessary resources for the eusb phy to work. 2. Adds interconnects on KERA USB. 3. QMP phy is used for SS/SSP usb usecases as well as DP use cases in a target. This change adds the basic resources required along with the init sequence for functionality. 4. Adding the necessary audio node providing the necessary resources of the qmi audio to get probed. 5. The GSI event buffers are required for the various GSI related usecases which are excercised from the dwc3 glue driver. Add the number of event buffers along with the register offsets defined. 6. Adding a 4-byte register entry for tcsr_dyn-en-dis to enable/disable USB dynamically from dwc3-msm-core. Change-Id: Ia45a09d8d2a54e29ecd0811e97d71c6dd8eaecee Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
157 lines
2.8 KiB
Plaintext
157 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,gcc-kera.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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&arch_timer {
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clock-frequency = <500000>;
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};
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&memtimer {
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clock-frequency = <500000>;
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};
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&disp_rsc {
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status = "disabled";
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};
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&soc {
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usb_emuphy: phy@a784000 {
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compatible = "qcom,usb-emu-phy";
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reg = <0x0a784000 0x9500>;
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qcom,emu-init-seq = <0xfffff 0x4
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0xffff0 0x4
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0x100000 0x20
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0x0 0x20
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0x000101F0 0x20
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0x00100000 0x3c
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0x0 0x3c
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0x0 0x4>;
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};
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};
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qrbtc-sdm845";
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/* VDDA_UFS_CORE */
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vdda-phy-supply = <&L6B>;
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vdda-phy-max-microamp = <211860>;
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/*
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* Platforms supporting Gear 5 && Rate B require a different
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* voltage supply. Check the Power Grid document.
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*/
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vdda-phy-min-microvolt = <912000>;
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/* VDDA_UFS_0_1P2 */
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vdda-pll-supply = <&L4B>;
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vdda-pll-max-microamp = <18330>;
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/* Phy GDSC for VDD_MX, always on */
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vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
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/* Qref power supply, Refer Qref diagram */
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vdda-qref-supply = <&L2B>;
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vdda-qref-max-microamp = <1890>;
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/* Detect whether RH132 card based sequences to be used */
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qcom,soc_emulation_type_addr = <0x1fc8004>;
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qcom,soc_emulation_type_bits = <32>;
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status = "ok";
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};
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&ufshc_mem {
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limit-tx-hs-gear = <1>;
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limit-rx-hs-gear = <1>;
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limit-rate = <2>; /* HS Rate-B */
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rpm-level = <0>;
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spm-level = <0>;
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vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
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vcc-supply = <&L12B>;
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vcc-max-microamp = <800000>;
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vccq-supply = <&L1D>;
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vccq-max-microamp = <750000>;
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qcom,vddp-ref-clk-supply = <&L3G>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vccq-parent-supply = <&S2B>;
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qcom,vccq-parent-max-microamp = <210000>;
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clock-names =
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"core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"core_clk_ice",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks =
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<&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
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<&rpmhcc RPMH_CXO_PAD_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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qcom,disable-lpm;
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status = "ok";
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};
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&usb0 {
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dwc3@a600000 {
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usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
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dr_mode = "peripheral";
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maximum-speed = "high-speed";
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};
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};
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&SILVER_OFF {
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status = "disabled";
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};
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&SILVER_RAIL_OFF {
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status = "disabled";
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};
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&GOLD_OFF {
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status = "disabled";
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};
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&GOLD_RAIL_OFF {
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status = "disabled";
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};
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&GOLD_PLUS_OFF {
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status = "disabled";
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};
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&GOLD_PLUS_RAIL_OFF {
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status = "disabled";
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};
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&CLUSTER_PWR_DN {
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status = "disabled";
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};
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&CX_RET {
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status = "disabled";
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};
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&APSS_OFF {
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status = "disabled";
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};
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