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Change-Id: I5477b88116252c866905874c87551d3ee2d4ca2d
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Linux Build Service Account
2024-06-20 02:09:09 -07:00
parent 94d63d5d5e d8f258e96f
commit 812aff9c19
137 changed files with 21380 additions and 793 deletions
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2
bindings/clock/qcom,debugcc.yaml
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@@ -19,6 +19,8 @@ properties:
- qcom,pineapple-debugcc
- qcom,sun-debugcc
- qcom,parrot-debugcc
- qcom,sm4450-debugcc
- qcom,monaco-debugcc
clocks:
items:

75
bindings/clock/qcom,dispcc-monaco.yaml Normal file
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@@ -0,0 +1,75 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-monaco.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Display Clock & Reset Controller
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm Technologies, Inc. display clock control module which supports the clocks and
power domains on Monaco.
See also:
dt-bindings/clock/qcom,dispcc-monaco.h
properties:
compatible:
enum:
- qcom,monaco-dispcc
clocks:
items:
- description: Brard XO source
- description: Brard XO_AO source
- description: Sleep clock source
- description: GPLL0 OUT MAIN clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
- const: gpll0_out_main
vdd_cx-supply:
description: Phandle pointer to the vdd_cx logic rail supply
vdd_mxa-supply:
description: Phandle pointer to the vdd_mxa logic rail supply
'#clock-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-monaco.h>
dispcc: clock-controller@5f00000 {
compatible = "qcom,monaco-dispcc", "syscon";
reg = <0x05f00000 0x20000>;
reg-names = "cc_base";
clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main",
"sleep_clk";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&gcc GPLL0>, <&sleep_clk>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...

69
bindings/clock/qcom,gcc-monaco.yaml Normal file
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@@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-monaco.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Global Clock & Reset Controller
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Global clock control module which supports the clocks, resets and
power domains on Monaco.
See also:
- dt-bindings/clock/qcom,gcc-monaco.h
properties:
compatible:
const: qcom,monaco-gcc
clocks:
items:
- description: Board XO source
- description: Board XO_AO source
- description: Sleep clock source
minItems: 2
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
minItems: 2
vdd_cx-supply:
description: Phandle pointer to the vdd_cx logic rail supply
vdd_mxa-supply:
description: Phandle pointer to the vdd_mxa logic rail supply
required:
- compatible
- clocks
- clock-names
allOf:
- $ref: "qcom,gcc.yaml#"
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
gcc: clock-controller@1410000 {
compatible = "qcom,monaco-gcc", "syscon";
reg = <0x1400000 0x1e0000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
...

7
bindings/clock/qcom,gcc-sun.yaml
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@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sun.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Global Clock & Reset Controller Binding for SUN
title: Qualcomm Technologies, Inc. Global Clock & Reset Controller
maintainers:
- Xubin Bai <quic_xubibai@quicinc.com>
@@ -15,10 +15,13 @@ description: |
See also:
- dt-bindings/clock/qcom,gcc-sun.h
- dt-bindings/clock/qcom,gcc-tuna.h
properties:
compatible:
const: qcom,gcc-sun
enum:
- qcom,gcc-sun
- qcom,tuna-gcc
clocks:
items:

4
bindings/clock/qcom,gpucc.yaml
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@@ -18,12 +18,14 @@ description: |
dt-bindings/clock/qcom,gpucc-sc7180.h
dt-bindings/clock/qcom,gpucc-sc7280.h
dt-bindings/clock/qcom,gpucc-sc8280xp.h
dt-bindings/clock/qcom,sm4450-gpucc.h
dt-bindings/clock/qcom,gpucc-sm6350.h
dt-bindings/clock/qcom,gpucc-sm8150.h
dt-bindings/clock/qcom,gpucc-sm8250.h
dt-bindings/clock/qcom,gpucc-pineapple.h
dt-bindings/clock/qcom,gpucc-sun.h
dt-bindings/clock/qcom,gpucc-parrot.h
dt-bindings/clock/qcom,gpucc-monaco.h
properties:
compatible:
@@ -33,12 +35,14 @@ properties:
- qcom,sc7280-gpucc
- qcom,sc8180x-gpucc
- qcom,sc8280xp-gpucc
- qcom,sm4450-gpucc
- qcom,sm6350-gpucc
- qcom,sm8150-gpucc
- qcom,sm8250-gpucc
- qcom,pineapple-gpucc
- qcom,sun-gpucc
- qcom,parrot-gpucc
- qcom,monaco-gpucc
clocks:
items:

3
bindings/clock/qcom,rpmcc.yaml
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@@ -45,6 +45,9 @@ properties:
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125
- qcom,rpmcc-sm6375
- qcom,rpmcc-holi
- qcom,rpmcc-khaje
- qcom,rpmcc-monaco
- const: qcom,rpmcc
'#clock-cells':

1
bindings/clock/qcom,rpmhcc.yaml
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@@ -25,6 +25,7 @@ properties:
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
- qcom,sm4450-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk

63
bindings/clock/qcom,sm4450-camcc.yaml Normal file
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@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm Technologies, Inc. camera clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h
properties:
compatible:
const: qcom,sm4450-camcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Camera AHB clock source from GCC
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@ade0000 {
compatible = "qcom,sm4450-camcc";
reg = <0x0ade0000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

71
bindings/clock/qcom,sm4450-dispcc.yaml Normal file
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@@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Display Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm Technologies, Inc. display clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h
properties:
compatible:
const: qcom,sm4450-dispcc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Display AHB clock source from GCC
- description: sleep clock source
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
clock-controller@af00000 {
compatible = "qcom,sm4450-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy_pll_out_byteclk>,
<&dsi0_phy_pll_out_dsiclk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

55
bindings/clock/qcom,sm4450-gcc.yaml Normal file
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@@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on SM4450
maintainers:
- Ajit Pandey <quic_ajipan@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm Technologies, Inc. global clock control module provides the clocks, resets and power
domains on SM4450
See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h
properties:
compatible:
const: qcom,sm4450-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm4450-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&ufs_mem_phy 0>, <&ufs_mem_phy 1>,
<&ufs_mem_phy 2>, <&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

3
bindings/clock/qcom,tcsrcc.yaml
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@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,tcsrcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Top-Level CSR Clock & Reset Controller Binding
title: Qualcomm Technologies, Inc. Top-Level CSR Clock & Reset Controller
maintainers:
- Xubin Bai <quic_xubibai@quicinc.com>
@@ -21,6 +21,7 @@ properties:
enum:
- qcom,pineapple-tcsrcc
- qcom,sun-tcsrcc
- qcom,tuna-tcsrcc
required:
- compatible

1
bindings/crypto/qcom,prng.yaml
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@@ -15,6 +15,7 @@ properties:
- enum:
- qcom,prng # 8916 etc.
- qcom,prng-ee # 8996 and later using EE
- qcom,msm-rng # parrot
- items:
- enum:
- qcom,sm8450-trng

323
bindings/input/qcom,qpnp-power-on.yaml
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@@ -9,7 +9,7 @@ title: Qualcomm Technologies, Inc. QPNP Power-on PMIC Peripheral
maintainers:
- David Collins <quic_collinsd@quicinc.com>
description: >
description: |
qpnp-power-on devices support the power-on (PON) peripheral found on
Qualcomm Technologies, Inc. PMICs. The supported functionality includes power
on/off reason, kerelease detection, PMIC reset configurations and other
@@ -22,117 +22,102 @@ properties:
const: qcom,qpnp-power-on
reg:
description: Specifies the SPMI base address for this
PON (power-on) peripheral. For PMICs that have
PON peripheral (GEN3) split into PON_HLOS and
PON_PBS, this can hold addresses of both.
PON_PBS base address needs to be specified for
such devices if "qcom,kdpwr-sw-debounce" is specified.
description: |
Specifies the SPMI base address for this PON (power-on) peripheral.
For PMICs that have PON peripheral (GEN3) split into PON_HLOS and
PON_PBS, this can hold addresses of both. PON_PBS base address needs
to be specified for such devices if "qcom,kdpwr-sw-debounce" is specified.
reg-names:
description: For PON GEN1 and GEN2, it should be "pon".
and for PON GEN3, it should include "pon_hlos" and
optionally "pon_pbs".
description: |
For PON GEN1 and GEN2, it should be "pon". and for PON GEN3, it should
include "pon_hlos" and optionally "pon_pbs".
interrupts:
description: Specifies the interrupts associated with PON.
description: |
Specifies the interrupts associated with PON.
interrupt-names:
description: Specifies the interrupt names associated with
the interrupts property. Must be a subset of
"kpdpwr", "kpdpwr-bark", "resin", "resin-bark",
"cblpwr", "kpdpwr-resin-bark", and
"pmic-wd-bark". Bark interrupts are associated
with system reset configuration to allow default
reset configuration to be activated. If system
reset configuration is not supported then bark
interrupts are nops. Additionally, the
"pmic-wd-bark" interrupt can be added if the
system needs to handle PMIC watchdog barks.
description: |
Specifies the interrupt names associated with the interrupts property.
Must be a subset of "kpdpwr", "kpdpwr-bark", "resin", "resin-bark",
"cblpwr", "kpdpwr-resin-bark", and "pmic-wd-bark". Bark interrupts are
associated with system reset configuration to allow default reset
configuration to be activated. If system reset configuration is not supported
then bark interrupts are nops. Additionally, the "pmic-wd-bark" interrupt
can be added if the system needs to handle PMIC watchdog barks.
qcom,pon-dbc-delay:
description: The debounce delay for the power-key interrupt
specified in us.
Possible values for GEN1 PON are
15625, 31250, 62500, 125000, 250000, 500000,
1000000 and 2000000.
Possible values for GEN2 PON are
62, 123, 245, 489, 977, 1954, 3907, 7813,
15625, 31250, 62500, 125000 and 250000.
Intermediate value is rounded down to the
nearest valid value.
description: |
The debounce delay for the power-key interrupt specified in us.
Possible values for GEN1 PON are 15625, 31250, 62500, 125000, 250000, 500000,
1000000 and 2000000. Possible values for GEN2 PON are 62, 123, 245, 489, 977,
1954, 3907, 7813, 15625, 31250, 62500, 125000 and 250000.
Intermediate value is rounded down to the nearest valid value.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,system-reset:
description: Boolean which specifies that this PON peripheral
can be used to reset the system. This property
can only be used by one device on the system. It
is an error to include it more than once.
description: |
Boolean which specifies that this PON peripheral can be used to reset the system.
This property can only be used by one device on the system. It is an error to
include it more than once.
type: boolean
qcom,modem-reset:
description: Boolean which specifies that this PON peripheral
can be used to reset the attached modem chip.
This property can only be used by one PON device
on the system. qcom,modem-reset and
qcom,system-reset cannot be specified for the
same PON device.
description: |
Boolean which specifies that this PON peripheral can be used to reset the attached
modem chip. This property can only be used by one PON device on the system.
qcom,modem-reset and qcom,system-reset cannot be specified for the same PON device.
type: boolean
qcom,s3-debounce:
description: The debounce delay for stage 3 reset trigger in
secs. The values range from 0 to 128.
description: |
The debounce delay for stage 3 reset trigger in secs. The values range from 0 to 128.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,s3-src:
description: The source for stage 3 reset. It can be one of
"kpdpwr", "resin", "kpdpwr-or-resin" or
"kpdpwr-and-resin".
description: |
The source for stage 3 reset. It can be one of "kpdpwr", "resin", "kpdpwr-or-resin" or
"kpdpwr-and-resin".
$ref: /schemas/types.yaml#/definitions/uint32
qcom,clear-warm-reset:
description: Boolean which specifies that the WARM_RESET
reason registers need to be cleared for this
target. The property is used for the targets
which have a hardware feature to catch resets
which aren't triggered by the application
processor. In such cases clearing WARM_REASON
registers across processor resets keeps the
registers in a useful state.
description: |
Boolean which specifies that the WARM_RESET reason registers need to be cleared for this
target. The property is used for the targets which have a hardware feature to catch resets
which aren't triggered by the application processor. In such cases clearing WARM_REASON
registers across processor resets keeps the registers in a useful state.
type: boolean
qcom,secondary-pon-reset:
description: Boolean property which indicates that the PON
peripheral is a secondary PON device which
needs to be configured during reset in addition
to the primary PON device that is configured
for system reset through qcom,system-reset
property.
This should not be defined along with the
qcom,system-reset or qcom,modem-reset property.
description: |
Boolean property which indicates that the PON peripheral is a secondary PON device which
needs to be configured during reset in addition to the primary PON device that is configured
for system reset through qcom,system-reset property.
This should not be defined along with the qcom,system-reset or qcom,modem-reset property.
type: boolean
qcom,store-hard-reset-reason:
description: Boolean property which if set will store the
hardware reset reason to SOFT_RB_SPARE register
of the core PMIC PON peripheral.
description: |
Boolean property which if set will store the hardware reset reason to SOFT_RB_SPARE
register of the core PMIC PON peripheral.
type: boolean
qcom,hard-reset-poweroff-type:
description: Same description as
qcom,warm-reset-poweroff-type but this applies
for the system hard reset case.
description: |
Same description as qcom,warm-reset-poweroff-type but this applies for the system
hard reset case.
type: boolean
qcom,kpdpwr-sw-debounce:
description: Boolean property to enable the debounce logic
on the KPDPWR_N rising edge.
description: |
Boolean property to enable the debounce logic on the KPDPWR_N rising edge.
type: boolean
qcom,pon_X:
description: These PON child nodes correspond to features
supported by the PON peripheral including reset
configurations, pushbutton keys, and regulators.
description: |
These PON child nodes correspond to features supported by the PON peripheral
including reset configurations, pushbutton keys, and regulators.
type: boolean
required:
@@ -140,29 +125,31 @@ required:
- reg
patternProperties:
"^pon-[0-9]+$":
'^qcom,pon_[0-9]$':
type: object
$ref: input.yaml#
unevaluatedProperties: false
properties:
regulator-name:
description: Regulator name for the PON regulator that is being configured.
description: |
Regulator name for the PON regulator that is being configured.
qcom,pon-spare-reg-addr:
description: Register offset from the base address of the
PON peripheral that needs to be configured for
the regulator being controlled.
description: |
Register offset from the base address of the PON peripheral that needs to be
configured for the regulator being controlled.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,pon-spare-reg-bit:
description: Bit position in the specified register that
needs to be configured for the regulator being
controlled.
description: |
Bit position in the specified register that needs to be configured for the
regulator being controlled.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,pon-type:
description: The type of PON/RESET source. Supported values are
description: |
The type of PON/RESET source. Supported values are
0 = KPDPWR
1 = RESIN
2 = CBLPWR
@@ -172,12 +159,13 @@ patternProperties:
$ref: /schemas/types.yaml#/definitions/uint32
qcom,pull-up:
description: Boolean flag indicating if a pull-up resistor
should be enabled for the input.
description: |
Boolean flag indicating if a pull-up resistor should be enabled for the input.
type: boolean
qcom,support-reset:
description: Indicates if this PON source supports
description: |
Indicates if this PON source supports
reset functionality.
0 = Not supported
1 = Supported
@@ -186,33 +174,32 @@ patternProperties:
type: boolean
qcom,use-bark:
description: Specify if this PON type needs to handle a bark
interrupt.
description: |
Specify if this PON type needs to handle a bark interrupt.
type: boolean
linux,code:
description: The input key-code associated with the reset
source. The reset source in its default
configuration can be used to support standard keys.
description: |
The input key-code associated with the reset source. The reset source in its
default configuration can be used to support standard keys.
qcom,s1-timer:
description: The debounce timer for the BARK interrupt for
the reset source. Value is specified in ms.
Supported values are
0, 32, 56, 80, 128, 184, 272, 408, 608, 904,
1352, 2048, 3072, 4480, 6720, 10256
description: |
The debounce timer for the BARK interrupt for the reset source. Value is
specified in ms. Supported values are 0, 32, 56, 80, 128, 184, 272, 408, 608, 904,
1352, 2048, 3072, 4480, 6720, 10256
type: boolean
qcom,s2-timer:
description: The debounce timer for the S2 reset specified
in ms. On the expiry of this timer, the PMIC
executes the reset sequence.
Supported values are
0, 10, 50, 100, 250, 500, 1000, 2000
description: |
The debounce timer for the S2 reset specified in ms. On the expiry of this timer,
the PMIC executes the reset sequence. Supported values are 0, 10, 50, 100, 250,
500, 1000, 2000
type: boolean
qcom,s2-type:
description: The type of reset associated with this source.
description: |
The type of reset associated with this source.
Supported values
0 = SOFT_RESET (legacy)
1 = WARM_RESET
@@ -242,76 +229,84 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/input/qcom,qpnp-power-on.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
qcom,power-on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x8 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x8 0x5 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "kpdpwr", "resin", "resin-bark",
"kpdpwr-resin-bark";
qcom,pon-dbc-delay = <15625>;
qcom,system-reset;
qcom,s3-debounce = <32>;
qcom,s3-src = "resin";
qcom,clear-warm-reset;
qcom,store-hard-reset-reason;
qcom,pon_1 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
qcom,pull-up;
linux,code = <KEY_POWER>;
};
qcom,pon_2 {
qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
qcom,support-reset = <1>;
qcom,pull-up;
qcom,s1-timer = <0>;
qcom,s2-timer = <2000>;
qcom,s2-type = <PON_POWER_OFF_TYPE_WARM_RESET>;
linux,code = <KEY_VOLUMEDOWN>;
qcom,use-bark;
};
qcom,pon_3 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR_RESIN>;
qcom,support-reset = <1>;
qcom,s1-timer = <6720>;
qcom,s2-timer = <2000>;
qcom,s2-type = <PON_POWER_OFF_TYPE_HARD_RESET>;
qcom,pull-up;
qcom,use-bark;
};
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x8 0x4 IRQ_TYPE_EDGE_RISING>,
<0x0 0x8 0x5 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "kpdpwr", "resin", "resin-bark",
"kpdpwr-resin-bark";
qcom,pon-dbc-delay = <15625>;
qcom,system-reset;
qcom,s3-debounce = <32>;
qcom,s3-src = "resin";
qcom,clear-warm-reset;
qcom,store-hard-reset-reason;
qcom,pon_1 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
qcom,pull-up = <1>;
linux,code = <KEY_POWER>;
};
qcom,pon_2 {
qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
qcom,support-reset = <1>;
qcom,pull-up;
qcom,s1-timer = <0>;
qcom,s2-timer = <2000>;
qcom,s2-type = <PON_POWER_OFF_TYPE_WARM_RESET>;
linux,code = <KEY_VOLUMEDOWN>;
qcom,use-bark;
};
qcom,pon_3 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR_RESIN>;
qcom,support-reset = <1>;
qcom,s1-timer = <6720>;
qcom,s2-timer = <2000>;
qcom,s2-type = <PON_POWER_OFF_TYPE_HARD_RESET>;
qcom,pull-up;
qcom,use-bark;
};
};
- |
qcom,power-on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
qcom,secondary-pon-reset;
qcom,hard-reset-poweroff-type = <PON_POWER_OFF_TYPE_SHUTDOWN>;
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
qcom,secondary-pon-reset;
qcom,hard-reset-poweroff-type = <PON_POWER_OFF_TYPE_SHUTDOWN>;
pon_perph_reg:qcom,pon_perph_reg {
regulator-name = "pon_spare_reg";
qcom,pon-spare-reg-addr = <0x8c>;
qcom,pon-spare-reg-bit = <1>;
};
pon_perph_reg:qcom,pon_perph_reg {
regulator-name = "pon_spare_reg";
qcom,pon-spare-reg-addr = <0x8c>;
qcom,pon-spare-reg-bit = <1>;
};
};
- |
pon_hlos@1300 {
compatible = "qcom,qpnp-power-on";
reg = <0x1300>, <0x800>;
reg-names = "pon_hlos", "pon_pbs";
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>
<0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "kpdpwr", "resin";
qcom,kpdpwr-sw-debounce;
compatible = "qcom,qpnp-power-on";
reg = <0x1300>, <0x800>;
reg-names = "pon_hlos", "pon_pbs";
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "kpdpwr", "resin";
qcom,kpdpwr-sw-debounce;
qcom,pon_1 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
linux,code = <KEY_POWER>;
};
qcom,pon_2 {
qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
linux,code = <KEY_VOLUMEDOWN>;
};
qcom,pon_1 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
linux,code = <KEY_POWER>;
};
qcom,pon_2 {
qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
...

107
bindings/input/touchscreen/focaltech,fts_ts.yaml Normal file
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@@ -0,0 +1,107 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/focaltech,fts_ts.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FocalTech touch controller DTB
maintainers:
- Maulik Shah <quic_mkshah@quicinc.com>
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
enum:
- focaltech,fts_ts
reg:
maxItems: 1
interrupts:
maxItems: 1
description: irq gpio
focaltech,reset-gpio:
maxItems: 1
focaltech,irq-gpio:
description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin
as output to reset the device.
irq-flags:
description: IRQ trigger type config.
1 - rising edge,
2 - falling edge,
4 - high level,
5 - low level.
focaltech,max-touch-number:
description: maximum number of touches support
$ref: /schemas/types.yaml#/definitions/uint32
focaltech,display-coords:
description: display resolution in pixels. A four tuple consisting of minX, minY, maxX and maxY.
$ref: /schemas/types.yaml#/definitions/uint32
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- focaltech,irq-gpio
- focaltech,reset-gpio
- focaltech,max-touch-number
- focaltech,display-coords
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c@f9927000 {
#address-cells = <1>;
#size-cells = <0>;
focaltech@38 {
compatible = "focaltech,fts_ts";
reg = <0x38>;
interrupt-parent = <&msm_gpio>;
interrupts = <13 0x02>;
focaltech,reset-gpio = <&msm_gpio 12 0x01>;
focaltech,irq-gpio = <&msm_gpio 13 0x02>;
focaltech,max-touch-number = <10>;
focaltech,display-coords = <0 0 1080 1920>;
pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
/*
focaltech,have-key;
focaltech,key-number = <3>;
focaltech,keys = <139 102 158>;
focaltech,key-x-coords = <200 600 800>;
focaltech,key-y-coords = <2000 2000 2000>;
*/
};
};
spi@78b9000 {
focaltech@0 {
compatible = "focaltech,fts_ts";
reg = <0x0>;
spi-max-frequency = <6000000>;
interrupt-parent = <&msm_gpio>;
interrupts = <13 0x2>;
focaltech,reset-gpio = <&msm_gpio 12 0x01>;
focaltech,irq-gpio = <&msm_gpio 13 0x02>;
focaltech,max-touch-number = <10>;
focaltech,display-coords = <0 0 1080 1920>;
pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
};
};

78
bindings/input/touchscreen/goodix_ts_i2c.yaml Normal file
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@@ -0,0 +1,78 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/goodix_ts_i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ChipOne ICN8318 Touchscreen Controller DTB
maintainers:
- Maulik Shah <quic_mkshah@quicinc.com>
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
enum:
- goodix,gt9916
- goodix,gt9966
reg:
maxItems: 1
reset-gpios:
maxItems: 1
irq-gpio:
description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin
as output to reset the device.
irq-flags:
description: IRQ trigger type config.
1 - rising edge,
2 - falling edge,
4 - high level,
5 - low level.
interrupts:
maxItems: 1
vdd-supply:
description: Power supply regulator for the chip
vddio-supply:
description: Power supply regulator for the I2C bus
unevaluatedProperties: false
required:
- compatible
- reg
- reset-gpios
- irq-gpio
- irq-flags
- interrupts
- touchscreen-size-x
- touchscreen-size-y
- touchscreen-size-w
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@5d {
compatible = "goodix,gt9916";
reg = <0x5d>;
reset-gpio = <&msm_gpio 12 0x0>;
irq-gpio = <&msm_gpio 13 0x2800>;
irq-flags = <2>; /* 1:trigger rising, 2:trigger falling;*/
touchscreen-max-x = <720>;
touchscreen-max-y = <1280>;
touchscreen-max-w = <255>;
};
};

71
bindings/input/touchscreen/novatek_nt36xxx.yaml Normal file
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@@ -0,0 +1,71 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/touchscreen/novatek_nt36xxx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Novatek nt36xxx touch controller DTB
maintainers:
- Maulik Shah <quic_mkshah@quicinc.com>
allOf:
- $ref: touchscreen.yaml#
properties:
compatible:
enum:
- novatek,NVT-ts
reg:
maxItems: 1
novatek,reset-gpios:
maxItems: 1
novatek,irq-gpio:
description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin
as output to reset the device.
irq-flags:
description: IRQ trigger type config.
1 - rising edge,
2 - falling edge,
4 - high level,
5 - low level.
vdd-supply:
description: digital voltage power supply needed to power device.
avdd-supply:
description: analog voltage power supply needed to power device
unevaluatedProperties: false
required:
- compatible
- reg
- vdd-supply
- avdd-supply
- reset-gpios
- irq-gpio
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c_1 {
#address-cells = <1>;
#size-cells = <0>;
/* Novatek device tree node */
novatek@62 {
compatible = "novatek,NVT-ts";
reg = <0x62>;
status = "ok";
vdd-supply = <&pm8994_lvs2>;
avdd-supply = <&pm8994_l22>;
novatek,reset-gpio = <&msm_gpio 102 0x00>;
novatek,irq-gpio = <&msm_gpio 65 0x2001>;
};
};

1
bindings/interrupt-controller/qcom,pdc.yaml
View File

@@ -36,6 +36,7 @@ properties:
- qcom,sun-pdc
- qcom,parrot-pdc
- qcom,ravelin-pdc
- qcom,tuna-pdc
- const: qcom,pdc
reg:

338
bindings/leds/qcom,leds-qpnp-flash-v2.yaml Normal file
View File

@@ -0,0 +1,338 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/qcom,leds-qpnp-flash-v2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies Inc. Plug-N-Play v2 Flash LED
maintainers:
- Rakesh Kota <quic_kotarake@quicinc.com>
- Subbaraman Narayanamurthy <subbaram@quicinc.com>
- Kamal Wadhwa <quic_kamalw@quicinc.com>
description: |
QPNP (Qualcomm Technologies Inc. Plug N Play) Flash LED (Light
Emitting Diode) driver v2 is used to provide illumination to
camera sensor when background light is dim to capture good
picture. It can also be used for flashlight/torch application.
It is part of PMIC on Qualcomm Technologies Inc. reference platforms.
properties:
compatible:
enum:
- qcom,pm6150l-flash-led-v2
- qcom,pmi632-flash-led-v2
reg:
description: |
Base address and size for flash LED modules
maxItems: 1
interrupts:
description: |
Specifies the interrupts associated with this device.
interrupt-names:
description: |
Specify the interrupt names associated with interrupts.
items:
- const: led-fault-irq
- const: mitigation-irq
- const: flash-timer-exp-irq
- const: all-ramp-down-done-irq
- const: all-ramp-up-done-irq
- const: led3-ramp-up-done-irq
- const: led2-ramp-up-done-irq
- const: led1-ramp-up-done-irq
qcom,hdrm-auto-mode:
description: |
Boolean type to select headroom auto mode enabled or not
type: boolean
qcom,isc-delay-us:
description: |
Integer type to specify short circuit delay. Valid values are 32, 64,
128, 192. Unit is uS.
maxItems: 1
patternProperties:
'^switch[0-9]-supply$':
description: |
phandle of the regulator that needs to be used
as a supply for flash switch_X device.
'^qcom,flash_[0-9]$':
type: object
properties:
label:
$ref: /schemas/types.yaml#/definitions/string-array
description: |
Specifies type of LED that will be used.
const: flash
qcom,led-name:
description: |
Name of the LED.
$ref: /schemas/types.yaml#/definitions/string
qcom,id:
description: |
Specifies the LED channel number for flash device.
It depends on hardware and starts with an index 0.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1, 2 ]
qcom,default-led-trigger:
description: |
Trigger for camera flash device.
$ref: /schemas/types.yaml#/definitions/string
qcom,max-current:
description: |
Maximum current allowed on this LED. Valid values should be
integer from 0 to 1500 inclusive. Flash 2 should have maximum current of
750 per hardware requirement. Unit is mA.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1500
qcom,duration-ms:
description: |
Default time duration for flash LED device. Unit is ms.
minimum: 10
maximum: 1280
qcom,ires-ua:
description: |
Current resolution for flash LED device. Unit is uA.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 5000, 12500 ]
required:
- label
- qcom,led-name
- qcom,default-led-trigger
- qcom,id
- qcom,max-current
- qcom,duration-ms
'^qcom,torch_[0-9]$':
type: object
properties:
label:
description: |
Specifies type of LED that will be used.
$ref: /schemas/types.yaml#/definitions/string-array
const: torch
qcom,led-name:
description: |
Name of the LED.
$ref: /schemas/types.yaml#/definitions/string
qcom,id:
description: |
Specifies the LED channel number for torch device.
It depends on hardware and starts with an index 0.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1, 2, 3 ]
qcom,default-led-trigger:
description: |
Trigger for torch device.
$ref: /schemas/types.yaml#/definitions/string
qcom,max-current:
description: |
Maximum current allowed for torch device. Unit is mA.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 500
default: 500
qcom,ires-ua:
description: |
Current resolution for torch device. Unit is uA.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 5000, 12500 ]
required:
- label
- qcom,led-name
- qcom,default-led-trigger
- qcom,id
- qcom,max-current
'^qcom,switch_[0-9]$':
type: object
properties:
label:
description: |
Specifies type of LED that will be used.
$ref: /schemas/types.yaml#/definitions/string-array
const: switch
qcom,led-name:
description: |
Name of the LED.
$ref: /schemas/types.yaml#/definitions/string
qcom,default-led-trigger:
description: |
Trigger for switch device.
$ref: /schemas/types.yaml#/definitions/string
qcom,led-mask:
description: |
Required property for switch nodes. Bitmask to indicate which leds are
controlled by this switch node. Accepted values are in the range 1 to 7,
inclusive. Example qcom,led-mask = <4>;
$ref: /schemas/types.yaml#/definitions/uint32
qcom,symmetry-en:
description: |
Boolean property to specify if the flash LEDs under a
switch node are controlled symmetrically. This needs
to be specified if a group of flash LED channels are
connected to a single LED.
type: boolean
required:
- label
- qcom,led-name
- qcom,default-led-trigger
- qcom,led-mask
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
qcom,leds@d300 {
compatible = "qcom,pm6150l-flash-led-v2";
status = "okay";
reg = <0xd300 0x100>;
interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x1 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x2 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x3 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x5 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x6 IRQ_TYPE_EDGE_BOTH>,
<0x3 0xd3 0x7 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "led-fault-irq",
"mitigation-irq",
"flash-timer-exp-irq",
"all-ramp-down-done-irq",
"all-ramp-up-done-irq",
"led3-ramp-up-done-irq",
"led2-ramp-up-done-irq",
"led1-ramp-up-done-irq";
qcom,hdrm-auto-mode;
qcom,isc-delay-us = <192>;
switch0-supply = <&pmi8998_bob>;
qcom,flash_0 {
label = "flash";
qcom,led-name = "led:flash_0";
qcom,max-current = <1500>;
qcom,default-led-trigger = "flash0_trigger";
qcom,id = <0>;
qcom,current = <1000>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
qcom,flash_1 {
label = "flash";
qcom,led-name = "led:flash_1";
qcom,max-current = <1500>;
qcom,default-led-trigger = "flash1_trigger";
qcom,id = <1>;
qcom,current = <1000>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
qcom,flash_2 {
label = "flash";
qcom,led-name = "led:flash_2";
qcom,max-current = <750>;
qcom,default-led-trigger = "flash2_trigger";
qcom,id = <2>;
qcom,current = <500>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
pinctrl-names = "led_enable","led_disable";
pinctrl-0 = <&led_enable>;
pinctrl-1 = <&led_disable>;
};
qcom,torch_0 {
label = "torch";
qcom,led-name = "led:torch_0";
qcom,max-current = <500>;
qcom,default-led-trigger = "torch0_trigger";
qcom,id = <0>;
qcom,current = <300>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
qcom,torch_1 {
label = "torch";
qcom,led-name = "led:torch_1";
qcom,max-current = <500>;
qcom,default-led-trigger = "torch1_trigger";
qcom,id = <1>;
qcom,current = <300>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
qcom,torch_2 {
label = "torch";
qcom,led-name = "led:torch_2";
qcom,max-current = <500>;
qcom,default-led-trigger = "torch2_trigger";
qcom,id = <2>;
qcom,current = <300>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <325>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
pinctrl-names = "led_enable","led_disable";
pinctrl-0 = <&led_enable>;
pinctrl-1 = <&led_disable>;
};
qcom,switch_0 {
label = "switch";
qcom,led-name = "led:switch_0";
qcom,led-mask = <3>;
qcom,default-led-trigger = "switch0_trigger";
qcom,symmetry-en;
};
qcom,switch_1 {
label = "switch";
qcom,led-name = "led:switch_1";
qcom,led-mask = <4>;
qcom,default-led-trigger = "switch1_trigger";
};
};
...

38
bindings/leds/qcom,leds-qti-tri-led.yaml
View File

@@ -27,25 +27,33 @@ properties:
nvmem:
description: Phandle of the nvmem device name to access SDAM to do PBS
trigger. This is required only for HR_LEDs.
patternProperties:
"^led@[0-9a-z]+$":
type: object
$ref: common.yaml#
unevaluatedProperties: false
pwms:
description: The PWM device (phandle) used for controlling LED.
properties:
pwms:
description: The PWM device (phandle) used for controlling LED.
led-sources:
description: see Documentation/devicetree/bindings/leds/common.txt;
led-sources:
description: see Documentation/devicetree/bindings/leds/common.txt;
Device current output identifiers are 0 - LED1_EN,
1 - LED2_EN, 2 - LED3_EN.
label:
description: see Documentation/devicetree/bindings/leds/common.txt;
label:
description: see Documentation/devicetree/bindings/leds/common.txt;
linux,default-trigger:
description: see Documentation/devicetree/bindings/leds/common.txt;
linux,default-trigger:
description: see Documentation/devicetree/bindings/leds/common.txt;
required:
- pwms
- led-sources
required:
- compatible
- reg
- pwms
- led-sources
allOf:
- $ref: common.yaml#
@@ -54,21 +62,23 @@ additionalProperties: false
examples:
- |
pmi8998_rgb: tri-led@d000{
#include <dt-bindings/interrupt-controller/irq.h>
pmi8998_rgb: tri-led@d000 {
compatible = "qcom,tri-led";
reg = <0xd000>;
red {
led@1 {
label = "red";
pwms = <&pmi8998_lpg 4 1000000>;
led-sources = <0>;
};
green {
led@2 {
label = "green";
pwms = <&pmi8998_lpg 3 1000000>;
led-sources = <1>;
};
blue {
led@3 {
label = "blue";
pwms = <&pmi8998_lpg 2 1000000>;
led-sources = <2>;

0
Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml → bindings/pinctrl/qcom,x1e80100-tlmm.yaml
View File

2
bindings/pwm/qcom,pwm-qti-lpg.yaml
View File

@@ -280,7 +280,7 @@ examples:
qcom,lut-patterns = <0 14 28 42 56 70 84 100
100 84 70 56 42 28 14 0>;
lpg@1 {
qcom,lpg-sdam-base = <0x48>:
qcom,lpg-sdam-base = <0x48>;
qcom,lpg-chan-id = <1>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;

143
bindings/qseecom/qcom,qseecom.yaml Normal file
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@@ -0,0 +1,143 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/qseecom/qcom,qseecom.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: "QSEECOM driver to provide transport between TZ and Linux."
description: |
The QSEECOM driver facilitates the communication and data transfer between
Trust Zone and Linux OS.
maintainers:
- Vikas Kumar Sharma <quic_vksharma@quicinc.com>
properties:
compatible:
const: qcom,qseecom
reg:
description: "Should contain memory region address reserved for loading secure apps."
maxItems: 2
qcom,disk-encrypt-pipe-pair:
description: "Indicates what CE HW pipe pair is used for disk encryption."
$ref: "/schemas/types.yaml#/definitions/uint32"
qcom,file-encrypt-pipe-pair:
description: "Indicates what CE HW pipe pair is used for file encryption."
$ref: "/schemas/types.yaml#/definitions/uint32"
qcom,support-multiple-ce-hw-instance:
description: "Indicates if multicore CE support is supported."
type: boolean
qcom,hlos-num-ce-hw-instances:
description: "Indicates number of CE HW instances hlos can use."
$ref: "/schemas/types.yaml#/definitions/uint32"
qcom,qsee-ce-hw-instance:
description: "Indicates what CE HW is used by secure domain (TZ) crypto driver."
$ref: "/schemas/types.yaml#/definitions/uint32"
qcom,msm_bus,name:
description: "Should be 'qseecom-noc'."
const: "qseecom-noc"
qcom,msm_bus,num_cases:
description: "Depends on the use cases for bus scaling."
$ref: "/schemas/types.yaml#/definitions/uint32"
qcom,msm_bus,num_paths:
description: "The paths for source and destination ports."
$ref: "/schemas/types.yaml#/definitions/uint32"
qcom,msm_bus,vectors:
description: "Vectors for bus topology."
$ref: "/schemas/types.yaml#/definitions/uint32-array"
qcom,ce-opp-freq:
description: "Indicates the CE operating frequency in Hz, changes from target to target."
$ref: "/schemas/types.yaml#/definitions/uint32"
qcom,full-disk-encrypt-info:
description: "Vectors defining full disk encryption unit, crypto engine, pipe pair configuration in <unit#, ce#, pipe-pair#>."
$ref: "/schemas/types.yaml#/definitions/uint32-array"
qcom,per-file-encrypt-info:
description: "Vectors defining per file encryption unit, crypto engine, pipe pair configuration in <unit#, ce#, pipe-pair#>."
$ref: "/schemas/types.yaml#/definitions/uint32-array"
qcom,support-bus-scaling:
description: "Indicates if driver supports scaling the bus for crypto operation."
type: boolean
qcom,support-fde:
description: "Indicates if driver supports key managing for full disk encryption feature."
type: boolean
qcom,support-pfe:
description: "Indicates if driver supports key managing for per file encryption feature."
type: boolean
qcom,no-clock-support:
description: "Indicates clocks are not handled by qseecom (could be handled by RPM)."
type: boolean
qcom,appsbl-qseecom-support:
description: "Indicates if there is qseecom support in apps bootloader."
type: boolean
qcom,qsee-reentrancy-support:
description: "Indicates the qsee reentrancy phase supported by the target."
type: boolean
qcom,commonlib64-loaded-by-uefi:
description: "Indicates commonlib64 is loaded by UEFI already."
type: boolean
qcom,fde-key-size:
description: "Indicates which FDE key size is used in device."
type: boolean
required:
- compatible
- reg
- qcom,disk-encrypt-pipe-pair
- qcom,file-encrypt-pipe-pair
- qcom,support-multiple-ce-hw-instance
- qcom,hlos-num-ce-hw-instances
- qcom,qsee-ce-hw-instance
- qcom,msm_bus,name
- qcom,msm_bus,num_cases
- qcom,msm_bus,num_paths
- qcom,msm_bus,vectors
- qcom,ce-opp-freq
- qcom,full-disk-encrypt-info
- qcom,per-file-encrypt-info
additionalProperties: false
examples:
- |
qcom,qseecom@7f00000:
compatible: "qcom,qseecom"
reg: <0x7f00000 0x500000>
reg-names: "secapp-region"
qcom,disk-encrypt-pipe-pair: <2>
qcom,file-encrypt-pipe-pair: <0>
qcom,support-multiple-ce-hw-instance: true
qcom,hlos-num-ce-hw-instances: <2>
qcom,qsee-ce-hw-instance: <0>
qcom,support-fde: true
qcom,support-pfe: true
qcom,msm_bus,name: "qseecom-noc"
qcom,msm_bus,num_cases: <4>
qcom,msm_bus,active_only: <0>
qcom,msm_bus,num_paths: <1>
qcom,no-clock-support: true
qcom,appsbl-qseecom-support: true
qcom,fde-key-size: true
qcom,msm_bus,vectors: [<55, 512, 0, 0>, <55, 512, 3936000000, 393600000>, <55, 512, 3936000000, 393600000>, <55, 512, 3936000000, 393600000>]
qcom,ce-opp-freq: <100000000>
vdd-hba-supply: "&gdsc_ufs"

67
bindings/regulator/qcom,pm8008-chip.yaml Normal file
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@@ -0,0 +1,67 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/qcom,pm8008-chip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. PM8008 Regulator's top-level chip
maintainers:
- Umang Chheda <quic_uchheda@quicinc.com>
description: |
PM8008 is an I2C based PMIC regulator chip.
properties:
compatible:
const: qcom,pm8008-chip
reg:
description:
Base address of the device.
maxItems: 1
patternProperties:
"^qcom,pm8008-chip-en+$":
type: object
$ref: /schemas/regulator/regulator.yaml#
description: |
Chip enable regulator device to control chip enable functionality.
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pm8008i_chip: pm8008i@8 {
compatible = "qcom,i2c-pmic";
reg = <0x8>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pm8008i_active>;
pm8008-chip@900 {
compatible = "qcom,pm8008-chip";
reg = <0x900>;
PM8008I_EN: qcom,pm8008-chip-en {
regulator-name = "pm8008i-chip-en";
};
};
};
};
...

185
bindings/regulator/qcom,pm8008-regulator.yaml Normal file
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@@ -0,0 +1,185 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/qcom,pm8008-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. PM8008 Regulator
maintainers:
- Umang Chheda <quic_uchheda@quicinc.com>
description: |
PM8008 chips contain 7 LDO regulators along with a top-level chip sleep feature.
properties:
compatible:
enum:
- qcom,pm8008-regulator
- qcom,pm8010-regulator
'#address-cells':
const: 1
'#size-cells':
const: 0
pm8008_en-supply:
description:
Reference to PM8008 chip enable regulator, which manages
chip enable functionlity of PM8008.
vdd_l1_l2-supply:
description:
Parent supply for LDO1/LDO2 of PM8008.
vdd_l3_l4-supply:
description:
Parent supply for LDO3/LDO4 of PM8008.
vdd_l5-supply:
description:
Parent supply for LDO5 of PM8008.
vdd_l6-supply:
description:
Parent supply for LDO6 of PM8008.
vdd_l7-supply:
description:
Parent supply for LDO7 of PM8008.
patternProperties:
"^regulator@[0-9a-f]+$":
type: object
$ref: /schemas/regulator/regulator.yaml#
description: |
Individual regulator devices under PM8008 chip.
properties:
reg:
maxItems: 1
description: |
Base address of individual LDO.
qcom,hpm-min-load:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Load current in uA which corresponds to the minimum load
which requires the regulator to be in high power mode.
qcom,min-dropout-voltage:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specifies the minimum voltage in microvolts that the parent
supply regulator must output above the output of this
regulator. It is only meaningful if the corresponding parent
supply property has been specified in the first level node.
qcom,init-voltage:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specifies the initial voltage in microvolts to for a regulator.
required:
- reg
required:
- compatible
- pm8008_en-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pm8008i_ldo: pm8008i@9 {
compatible = "qcom,i2c-pmic";
reg = <0x9>;
#address-cells = <1>;
#size-cells = <0>;
qcom,pm8008i-regulator {
compatible = "qcom,pm8008-regulator";
#address-cells = <1>;
#size-cells = <0>;
pm8008_en-supply = <&PM8008I_EN>;
vdd_l1_l2-supply = <&vreg_s8b_1p2>;
vdd_l3_l4-supply = <&vreg_bob>;
vdd_l5-supply = <&vreg_s1b_1p8>;
vdd_l6-supply = <&vreg_bob>;
vdd_l7-supply = <&vreg_bob>;
L1I: pm8008i_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8008i_l1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1200000>;
qcom,min-dropout-voltage = <160000>;
qcom,hpm-min-load = <30000>;
};
L2I: pm8008i_l2: regulator@4100 {
reg = <0x4100>;
regulator-name = "pm8008i_l2";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,min-dropout-voltage = <128000>;
qcom,hpm-min-load = <30000>;
};
L3I: pm8008i_l3: regulator@4200 {
reg = <0x4200>;
regulator-name = "pm8008i_l3";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3000000>;
qcom,min-dropout-voltage = <144000>;
};
L4I: pm8008i_l4: regulator@4300 {
reg = <0x4300>;
regulator-name = "pm8008i_l4";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
qcom,min-dropout-voltage = <128000>;
};
L5I: pm8008i_l5: regulator@4400 {
reg = <0x4400>;
regulator-name = "pm8008i_l5";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
qcom,min-dropout-voltage = <136000>;
};
L6I: pm8008i_l6: regulator@4500 {
reg = <0x4500>;
regulator-name = "pm8008i_l6";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
qcom,min-dropout-voltage = <128000>;
};
L7I: pm8008i_l7: regulator@4600 {
reg = <0x4600>;
regulator-name = "pm8008i_l7";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3000000>;
qcom,min-dropout-voltage = <312000>;
};
};
};
};
...

548
bindings/regulator/rpm-smd-regulator.yaml Normal file
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@@ -0,0 +1,548 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/rpm-smd-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. RPM Regulators
maintainers:
- David Collins <quic_collinsd@quicinc.com>
- Kamal Wadhwa <quic_kamalw@quicinc.com>
- Jishnu Prakash <quic_jprakash@quicinc.com>
description: |
rpm-regulator-smd is a regulator driver which supports regulators inside of
PMICs which are controlled by the RPM processor. Communication with the RPM
processor takes place over SMD.
Required Node Structure:
RPM regulators must be described in two levels of devices nodes. The first
level describes the interface with the RPM. The second level describes
properties of one regulator framework interface (of potentially many) to
the regulator.
properties:
compatible:
const: qcom,rpm-smd-regulator-resource
qcom,resource-name:
description: |
Resource name string for this regulator to be used in RPM
transactions. Length is 4 characters max.
$ref: /schemas/types.yaml#/definitions/string
qcom,resource-id:
description: |
Resource instance ID for this regulator to be used in RPM
transactions.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,regulator-type:
description: |
Type of this regulator. Supported values are 0 = LDO, 1 = SMPS
2 = VS, 3 = NCP, 4 = Buck or Boost (BoB)
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 4
qcom,allow-atomic:
description: |
Boolean flag specifying if atomic access is allowed for this
regulator.
$ref: /schemas/types.yaml#/definitions/flag
qcom,enable-time:
description:
Time in us to delay after enabling the regulator
$ref: /schemas/types.yaml#/definitions/uint32
qcom,hpm-min-load:
description: |
Load current in uA which corresponds to the minimum load
which requires the regulator to be in high power mode.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,apps-only:
description: |
Boolean flag which indicates that the regulator only has
consumers on the application processor. If this flag
is specified, then voltage and current updates are
only sent to the RPM if the regulator is enabled.
$ref: /schemas/types.yaml#/definitions/flag
qcom,always-wait-for-ack:
description: |
Boolean flag which indicates that the application processor
must wait for an ACK or a NACK from RPMh for every request
sent for this regulator including those which are for a
strictly lower power state.
$ref: /schemas/types.yaml#/definitions/flag
qcom,regulator-hw-type:
description: |
Specifies the regulator LDO hardware type. This
property must be specified if "qcom,regulator-type"
has been specified with a value of 0 (LDO).
enum:
- pmic4-ldo
- pmic5-ldo
qcom,supported-modes:
description: |
A list of integers specifying the PMIC regulator modes
supported by this regulator. Supported values are
RPMH_REGULATOR_MODE_* (i.e. 0 to 4). Elements must be
specified in order from lowest to highest.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 5
items:
minimum: 0
maximum: 4
qcom,mode-threshold-currents:
description: |
A list of integers specifying minimum allowed current in
microamps for each of the modes listed in qcom,supported-modes.
The first element should always be 0. Elements must be specified
in order from lowest to highest.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 5
additionalProperties: false
required:
- compatible
- qcom,resource-name
- qcom,resource-id
- qcom,regulator-type
patternProperties:
"^regulator.*$":
type: object
$ref: regulator.yaml#
description: regulator client voting interface node(s).
properties:
compatible:
const: qcom,rpm-smd-regulator
regulator-name:
description: A string used as a descriptive name for regulator output
regulator-min-microvolt:
description: |
For VRM resources, this is the minimum supported voltage in
microvolts. For ARC resources, this is the minimum
supported voltage level from RPMH_REGULATOR_LEVEL_*.
regulator-max-microvolt:
description: |
For VRM resources, this is the maximum supported voltage in
microvolts. For ARC resources, this is the maximum
supported voltage level from RPMH_REGULATOR_LEVEL_*.
parent-supply:
description: |
phandle to the parent supply/regulator node.
qcom,set:
description: |
Specifies which sets that requests made with this
regulator interface should be sent to. Regulator
requests sent in the active set take effect immediately.
Requests sent in the sleep set take effect when the Apps
processor transitions into RPM assisted power collapse.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 3
qcom,system-load:
description: |
Load in uA present on regulator that is not
captured by any consumer request.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,use-voltage-corner:
description: |
Flag that signifies if regulator_set_voltage
calls should modify the corner parameter instead
of the voltage parameter. When used, voltages
specified inside of the regulator framework
represent corners that have been incremented by
1. This value shift is necessary to work around
limitations in the regulator framework which
treat 0 uV as an error.
$ref: /schemas/types.yaml#/definitions/flag
qcom,use-voltage-floor-corner:
description: |
Flag that signifies if regulator_set_voltage
calls should modify the floor corner parameter
instead of the voltage parameter. When used,
voltages specified inside of the regulator
framework represent corners that have been
incremented by 1. The properties
qcom,use-voltage-corner and
qcom,use-voltage-floor-corner are mutually
exclusive. Only one may be specified for a
given regulator.
$ref: /schemas/types.yaml#/definitions/flag
qcom,use-voltage-level:
description: |
Flag that signifies if regulator_set_voltage
calls should modify the level parameter instead
of the voltage parameter.
$ref: /schemas/types.yaml#/definitions/flag
qcom,use-voltage-floor-level:
description: |
Flag that signifies if regulator_set_voltage
calls should modify the floor level parameter
instead of the voltage parameter.
The properties qcom,use-voltage-level and
qcom,use-voltage-floor-level are mutually
exclusive. Only one may be specified for a
given regulator.
$ref: /schemas/types.yaml#/definitions/flag
qcom,use-pin-ctrl-voltage1:
description: |
Flag which indicates that updates to voltage
should be sent to the pin control voltage 1
parameter. Only one pin may be specified per
regulator. This property only applies to BoB
type regulators.
$ref: /schemas/types.yaml#/definitions/flag
qcom,use-pin-ctrl-voltage2:
description: |
Flag which indicates that updates to voltage
should be sent to the pin control voltage 2
parameter. Only one pin may be specified per
regulator. This property only applies to BoB
type regulators.
$ref: /schemas/types.yaml#/definitions/flag
qcom,use-pin-ctrl-voltage3:
description: |
Flag which indicates that updates to voltage
should be sent to the pin control voltage 3
parameter. Only one pin may be specified per
regulator. This property only applies to BoB
type regulators.
$ref: /schemas/types.yaml#/definitions/flag
qcom,always-send-voltage:
description: |
Flag which indicates that updates to the
voltage, voltage corner or voltage level set
point should always be sent immediately to the
RPM. If this flag is not specified, then
voltage set point updates are only sent if the
given regulator has also been enabled by a
Linux consumer.
$ref: /schemas/types.yaml#/definitions/flag
qcom,always-send-current:
description: |
Flag which indicates that updates to the load
current should always be sent immediately to the
RPM. If this flag is not specified, then load
current updates are only sent if the given
regulator has also been enabled by a Linux
consumer.
$ref: /schemas/types.yaml#/definitions/flag
qcom,send-defaults:
description: |
Boolean flag which indicates that the initial
parameter values should be sent to the RPM
before consumers make their own requests. If
this flag is not specified, then initial
parameters values will only be sent after some
consumer makes a request.
$ref: /schemas/types.yaml#/definitions/flag
qcom,enable-with-pin-ctrl:
description: |
Double in which the first element corresponds to
the pin control enable parameter value to send
when all consumers have requested the regulator
to be disabled. The second element corresponds
to the pin control enable parameter value to
send when any consumer has requested the
regulator to be enabled. Each element supports
the same set of values as the
qcom,init-pin-ctrl-enable property listed below.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-enable:
description: |
Specifies the initial enable state to request for a VRM
regulator: 0 = disabled and 1 = enabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1
qcom,init-voltage:
description: Voltage in uV.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-current:
description: Current in mA.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-ldo-mode:
description: |
Operating mode to be used with LDO regulators
Supported values are 0 = mode determined by current requests
1 = force HPM (NPM)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-smps-mode:
description: |
Operating mode to be used with SMPS regulators
Supported values are:
0 = auto; hardware determines mode
1 = mode determined by current requests
2 = force HPM (PWM)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-bob-mode:
description: |
Operating mode to be used with BoB regulators
Supported values are:
0 = pass; use priority order
1 = force PFM
2 = auto; hardware determines mode
3 = force PWM
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-pin-ctrl-enable:
description: |
Bit mask specifying which hardware pins should be
used to enable the regulator, if any; supported
bits are:
0 = ignore all hardware enable signals
BIT(0) = follow HW0_EN signal
BIT(1) = follow HW1_EN signal
BIT(2) = follow HW2_EN signal
BIT(3) = follow HW3_EN signal
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-pin-ctrl-mode:
description: |
Bit mask specifying which hardware pins should be
used to force the regulator into high power
mode, if any. Supported bits are:
0 = ignore all hardware enable signals
BIT(0) = follow HW0_EN signal
BIT(1) = follow HW1_EN signal
BIT(2) = follow HW2_EN signal
BIT(3) = follow HW3_EN signal
BIT(4) = follow PMIC awake state
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-pin-ctrl-voltage1:
description: |
Minimum voltage in micro-volts to use while pin
control 1 is enabled. This property only
applies to BoB type regulators.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-pin-ctrl-voltage2:
description: |
Minimum voltage in micro-volts to use while pin
control 2 is enabled. This property only
applies to BoB type regulators.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-pin-ctrl-voltage3:
description: |
Minimum voltage in micro-volts to use while pin
control 3 is enabled. This property only
applies to BoB type regulators.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-frequency:
description: |
Switching frequency divisor for SMPS regulators.
Supported values are n = 0 to 31 where
freq = 19.2 MHz / (n + 1).
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-head-room:
description: |
Voltage head room in mV required for the
regulator. This head room value should be used
in situations where the device connected to the
output of the regulator has low noise tolerance.
Note that the RPM independently enforces a
safety head room value for subregulated LDOs
which is sufficient to account for LDO drop-out
voltage.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-quiet-mode:
description: |
Specify that quiet mode is needed for an SMPS
regulator in order to have lower output noise.
Supported values are:
0 = No quiet mode
1 = Quiet mode
2 = Super quiet mode
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-freq-reason:
description: |
Consumer requiring specified frequency for an
SMPS regulator. Supported values are:
0 = None
1 = Bluetooth
2 = GPS
4 = WLAN
8 = WAN
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-voltage-corner:
description: |
Performance corner to use in order to determine
voltage set point. This value corresponds to
the actual value that will be sent and is not
incremented by 1 like the values used inside of
the regulator framework. The meaning of corner
values is set by the RPM. It is possible that
different regulators on a given platform or
similar regulators on different platforms will
utilize different corner values. These are
corner values supported on MSM8974 for PMIC
PM8841 SMPS 2 (VDD_Dig); nominal voltages for
these corners are also shown:
0 = None (don't care)
1 = Retention (0.5000 V)
2 = SVS Krait (0.7250 V)
3 = SVS SOC (0.8125 V)
4 = Normal (0.9000 V)
5 = Turbo (0.9875 V)
6 = Super Turbo (1.0500 V)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-disallow-bypass:
description: |
Specify that bypass mode should not be used for a
given LDO regulator. When in bypass mode, an
LDO performs no regulation and acts as a simple
switch. The RPM can utilize this mode for an
LDO that is subregulated from an SMPS when it is
possible to reduce the SMPS voltage to the
desired LDO output level. Bypass mode may be
disallowed if lower LDO output noise is
required. Supported values are:
0 = Allow RPM to utilize LDO bypass mode
if possible
1 = Disallow LDO bypass mode
$ref: /schemas/types.yaml#/definitions/flag
qcom,init-voltage-floor-corner:
description: |
Minimum performance corner to use if any
processor in the system is awake.This property
supports the same values as
qcom,init-voltage-corner.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-voltage-level:
description: |
Performance level to use in order to determine
voltage set point. The meaning of level
values is set by the RPM. It is possible that
different regulators on a given platform or
similar regulators on different platforms will
utilize different level values. These are
level values supported on MSM8952 for PMIC
PM8952 SMPS 2 (VDD_Dig); nominal voltages for
these level are also shown:
16 = Retention (0.5000 V)
128 = SVS (1.0500 V)
192 = SVS+ (1.1550 V)
256 = Normal (1.2250 V)
320 = Normal+ (1.2875 V)
384 = Turbo (1.3500 V)
$ref: /schemas/types.yaml#/definitions/uint32
qcom,init-voltage-floor-level:
description: |
Minimum performance level to use if any
processor in the system is awake. This property
supports the same values as
qcom,init-voltage-level
$ref: /schemas/types.yaml#/definitions/uint32
additionalProperties: false
required:
- compatible
- regulator-name
- qcom,set
examples:
- |
rpm-regulator-smpb1 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpb";
qcom,resource-id = <1>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
pm8841_s1: regulator-s1 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "8841_s1";
qcom,set = <3>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1150000>;
qcom,init-voltage = <1150000>;
};
pm8841_s1_ao: regulator-s1-ao {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "8841_s1_ao";
qcom,set = <1>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1150000>;
};
pm8841_s1_corner: regulator-s1-corner {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "8841_s1_corner";
qcom,set = <3>;
regulator-min-microvolt = <1>;
regulator-max-microvolt = <6>;
qcom,init-voltage-corner = <3>;
qcom,use-voltage-corner;
};
};
rpm-regulator-ldoa2 {
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <2>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
regulator-l2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "8941_l2";
qcom,set = <3>;
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
qcom,init-voltage = <1225000>;
};
};
...

1
bindings/rtc/qcom-pm8xxx-rtc.yaml
View File

@@ -17,6 +17,7 @@ properties:
- qcom,pm8941-rtc
- qcom,pm8018-rtc
- qcom,pmk8350-rtc
- qcom,pm5100-rtc
reg:
minItems: 1

15
bindings/serial/qcom,serial-geni-msm.yaml
View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/qcom,msm-geni-uart.yaml#"
$id: "http://devicetree.org/schemas/serial/qcom,serial-geni-msm.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Technologies, Inc. Serial UART for GENI based cores
@@ -34,9 +34,8 @@ properties:
- const: qup-memory
interrupts:
minItems: 1
items:
- description: UART core irq
description: first irq for UART core & second irq for host wake up
maxItems: 2
operating-points-v2: true
@@ -59,9 +58,10 @@ properties:
reg:
maxItems: 1
interrupts:
items:
- description: byte which is used for waking up.
# Optional property
qcom,suspend-ignore-children:
type: boolean
description: When set ignores dependencies on children by PM framework
required:
- compatible
@@ -101,5 +101,6 @@ examples:
pinctrl-3 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>,
<&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>;
qcom,wakeup-byte = <0xFD>;
qcom,suspend-ignore-children;
};
...

26
bindings/soc/qcom/cpuss-sleep-stats.yaml
View File

@@ -21,6 +21,8 @@ properties:
compatible:
enum:
- qcom,cpuss-sleep-stats
- qcom,cpuss-sleep-stats-v2
- qcom,cpuss-sleep-stats-v3
- qcom,cpuss-sleep-stats-v4
reg:
@@ -97,6 +99,30 @@ examples:
num-cpus = <8>;
};
- |
cpuss-sleep-stats@18000054 {
compatible = "qcom,cpuss-sleep-stats-v2";
reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
<0x17830054 0x4>, <0x17880098 0x4>, <0x178C0000 0x10000>;
reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
"seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
"l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
num-cpus = <4>;
};
- |
cpuss-sleep-stats@17800054 {
compatible = "qcom,cpuss-sleep-stats-v3";
reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
<0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>,
<0x17880098 0x4>, <0x178C0000 0x10000>;
reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
"seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
"seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
"l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
num-cpus = <6>;
};
- |
cpuss-sleep-stats@17850000 {
compatible = "qcom,cpuss-sleep-stats-v4";

3
bindings/soc/qcom/qcom,crm.yaml
View File

@@ -41,12 +41,13 @@ properties:
- qcom,disp-crm-v2
reg:
minItems: 5
minItems: 6
reg-names:
items:
- const: base
- const: crm_b
- const: crm_b_pt
- const: crm_c
- const: crm_v
- const: common

30
bindings/soc/qcom/qcom,slate_events_bridge.yaml Normal file
View File

@@ -0,0 +1,30 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,slate_events_bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Slate Events Bridge Driver
maintainers:
- Praveen koya <quic_pkoya@quicinc.com>
description: |
slate_events_bridge driver provides a set of apis for clients
to receive events from slate co processor. The events are
received over Glink.
properties:
compatible:
const: qcom,slate-events-bridge
required:
- compatible
additionalProperties: false
examples:
- |
qcom,slate-events-bridge {
compatible = "qcom,slate-events-bridge";
};

46
bindings/soc/qcom/qcom,slate_events_bridge_rpmsg.yaml Normal file
View File

@@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,slate_events_bridge_rpmsg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Slate Events Bridge RPMSG Driver
maintainers:
- Praveen koya <quic_pkoya@quicinc.com>
description: |
slate_events_bridge_rpmsg driver provides functionality
to send and receive data over Glink from slate co processor.
properties:
compatible:
const: qcom,slate-events-bridge-rpmsg
qcom,glink-channels:
$ref: '/schemas/types.yaml#/definitions/string'
description: specifies the glink channel name
qcom,glinkpkt-edge:
$ref: '/schemas/types.yaml#/definitions/string'
description: specifies the glink edge to match
intents:
description: specifies the size and count of intents to glink
required:
- compatible
- qcom,glink-channels
- qcom,glinkpkt-edge
additionalProperties: false
examples:
- |
qcom,slate-events-bridge-rpmsg {
compatible = "qcom,slate-events-bridge-rpmsg";
qcom,glink-channels = "slate_events";
qcom,glinkpkt-edge = "slate";
intents = <0x200 5>;
};

30
bindings/soc/qcom/qcom,slate_rsb.yaml Normal file
View File

@@ -0,0 +1,30 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,slate_rsb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm technologies, Inc. slate-rsb
maintainers:
- Praveen koya <quic_pkoya@quicinc.com>
description: |
slate-rsb is used to communicate with Slate over Glink
to configure the RSB eventsslate-rsb send commands over glink to
send configure, enable/disable RSB to Slate
properties:
compatible:
const: qcom,slate-rsb
required:
- compatible
additionalProperties: false
examples:
- |
qcom,slate-rsb {
compatible = "qcom,slate-rsb";
};

38
bindings/soc/qcom/qcom,slatecom_interface.yaml Normal file
View File

@@ -0,0 +1,38 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,slatecom_interface.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Slatecom Interface Driver
maintainers:
- Praveen koya <quic_pkoya@quicinc.com>
description: |
slatecom_interface driver creates a slate_com_dev device
node for user space communication. Single user space
client can open device node for communication from hardware.
Hardware will provide access to read/write registers or AHB
memory in the device.
properties:
compatible:
const: qcom,slate-daemon
qcom,platform-reset-gpio:
description: This gpio state used to make boot decision for slate subsystem.
required:
- compatible
- qcom,platform-reset-gpio
additionalProperties: false
examples:
- |
qcom,slate-daemon {
compatible = "qcom,slate-daemon";
qcom,platform-reset-gpio = <&pm5100_gpios 15 0>;
};

46
bindings/soc/qcom/qcom,slatecom_rpmsg.yaml Normal file
View File

@@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,slatecom_rpmsg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Slatecom RPMSG Driver
maintainers:
- Praveen koya <quic_pkoya@quicinc.com>
description: |
slatecom_rpmsg driver provides functionality
to send and receive data over Glink from slate co processor.
properties:
compatible:
const: qcom,slatecom-rpmsg
qcom,glink-channels:
$ref: '/schemas/types.yaml#/definitions/string'
description: specifies the glink channel name
qcom,glinkpkt-edge:
$ref: '/schemas/types.yaml#/definitions/string'
description: specifies the glink edge to match
intents:
description: specifies the size and count of intents to glink
required:
- compatible
- qcom,glink-channels
- qcom,glinkpkt-edge
additionalProperties: false
examples:
- |
qcom,slatecom-rpmsg {
compatible = "qcom,slatecom-rpmsg";
qcom,glink-channels = "slate_ctrl";
qcom,glinkpkt-edge = "slate";
intents = <0x200 1>;
};

37
bindings/soc/qcom/qcom,slatecom_spi.yaml Normal file
View File

@@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,slatecom_spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Slate Coprocessor Communication Driver
maintainers:
- Praveen koya <quic_pkoya@quicinc.com>
description: |
slatecom_spi driver provides a set of apis to perform
register, fifo, ahb read and write operations with slate
over spi interface. It also reads slate status and
sends events to the registered clients.
properties:
compatible:
const: qcom,slate-spi
qcom,irq-gpio:
description: IRQ used by the slate to inturrupt MSM.
required:
- compatible
additionalProperties: false
examples:
- |
qcom,slate-spi {
compatible = "qcom,slate-spi";
interrupt-parent = <&tlmm>;
/* IRQ from slate */
qcom,irq-gpio = <&tlmm 104 1>;
};

47
bindings/soc/qcom/qcom,slatersb_rpmsg.yaml Normal file
View File

@@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,slatersb_rpmsg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm technologies, Inc. slatersb-rpmsg
maintainers:
- Praveen koya <quic_pkoya@quicinc.com>
description: |
slatersb-rpmsg is used as an interface between slate-rsb
and slate for Glink communication.slate-rsb is used to communicate with
Slate over Glink to configure the RSB events.
properties:
compatible:
const: qcom,slatersb-rpmsg
qcom,glink-channels:
$ref: '/schemas/types.yaml#/definitions/string'
description: specifies the glink channel name
qcom,glinkpkt-edge:
$ref: '/schemas/types.yaml#/definitions/string'
description: specifies the glink edge to match
intents:
description: specifies the size and count of intents to glink
required:
- compatible
- qcom,glink-channels
- qcom,glinkpkt-edge
- intents
additionalProperties: false
examples:
- |
qcom,slatersb-rpmsg {
compatible = "qcom,slatersb-rpmsg";
qcom,glink-channels = "RSB_CTRL";
qcom,glinkpkt-edge = "slate";
intents = <0x200 1>;
};

2
bindings/vendor-prefixes.yaml
View File

@@ -464,6 +464,8 @@ patternProperties:
description: Firefly
"^focaltech,.*":
description: FocalTech Systems Co.,Ltd
"^novatek,.*":
description: NOVATEK Microelectronics Corporation
"^forlinx,.*":
description: Baoding Forlinx Embedded Technology Co., Ltd.
"^frida,.*":

20
qcom/Makefile
View File

@@ -125,6 +125,26 @@ parrot-dtb-$(CONFIG_ARCH_PARROT) += \
parrot-overlays-dtb-$(CONFIG_ARCH_PARROT) += $(PARROT_BOARDS) $(PARROT_BASE_DTB) $(PARROT_4GB_BOARDS) $(PARROT_4GB_BASE_DTB)
dtb-y += $(parrot-dtb-y)
RAVELIN_BASE_DTB += ravelin.dtb ravelinp.dtb
RAVELIN_4GB_BASE_DTB += ravelin-4gb.dtb ravelinp-4gb.dtb
RAVELIN_BOARDS += \
ravelin-rumi-overlay.dtbo \
ravelin-atp-overlay.dtbo \
ravelin-idp-overlay.dtbo \
ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo \
ravelin-qrd-overlay.dtbo \
RAVELIN_4GB_BOARDS += \
ravelin-idp-wcn3988-4gb-overlay.dtbo \
ravelin-qrd-4gb-overlay.dtbo \
parrot-dtb-$(CONFIG_ARCH_RAVELIN) += \
$(call add-overlays, $(RAVELIN_BOARDS),$(RAVELIN_BASE_DTB)) \
$(call add-overlays, $(RAVELIN_4GB_BOARDS),$(RAVELIN_4GB_BASE_DTB))
parrot-overlays-dtb-$(CONFIG_ARCH_RAVELIN) += $(RAVELIN_BOARDS) $(RAVELIN_BASE_DTB) $(RAVELIN_4GB_BOARDS) $(RAVELIN_4GB_BASE_DTB)
dtb-y += $(parrot-dtb-y)
endif
ifeq ($(CONFIG_ARCH_PINEAPPLE), y)

10
qcom/ipcc-test-ravelin.dtsi Normal file
View File

@@ -0,0 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ipcc-test.dtsi"
&soc {
/delete-node/ ipcc-self-ping-slpi;
};

229
qcom/kera.dtsi
View File

@@ -3,6 +3,14 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,cambistmclkcc-sun.h>
#include <dt-bindings/clock/qcom,camcc-sun.h>
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
#include <dt-bindings/clock/qcom,gcc-kera.h>
#include <dt-bindings/clock/qcom,gpucc-kera.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
#include <dt-bindings/clock/qcom,videocc-tuna.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
@@ -293,6 +301,227 @@
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
pcie_0_pipe_clk: pcie_0_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
};
pcie_1_pipe_clk: pcie_1_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <0>;
};
ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_phy_rx_symbol_0_clk";
#clock-cells = <0>;
};
ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_phy_rx_symbol_1_clk";
#clock-cells = <0>;
};
ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_phy_tx_symbol_0_clk";
#clock-cells = <0>;
};
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <0>;
};
};
rpmhcc: clock-controller {
compatible = "fixed-clock";
clock-output-names = "rpmh_clocks";
clock-frequency = <19200000>;
#clock-cells = <1>;
};
cambistmclkcc: clock-controller@1760000 {
compatible = "qcom,dummycc";
clock-output-names = "cambistmclkcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
camcc: clock-controller@ade0000 {
compatible = "qcom,dummycc";
clock-output-names = "camcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,dummycc";
clock-output-names = "dispcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
gcc: clock-controller@100000 {
compatible = "qcom,dummycc";
clock-output-names = "gcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,dummycc";
clock-output-names = "gpucc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
tcsrcc: clock-controller@1f40000 {
compatible = "qcom,dummycc";
clock-output-names = "tcsrcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,dummycc";
clock-output-names = "videocc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
};
#include "tuna-gdsc.dtsi"
&cam_cc_ipe_0_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&cam_cc_ofe_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&cam_cc_tfe_0_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&cam_cc_tfe_1_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&cam_cc_tfe_2_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&cam_cc_titan_top_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&disp_cc_mdss_core_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&disp_cc_mdss_core_int2_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&gcc_pcie_0_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&gcc_pcie_0_phy_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&gcc_pcie_1_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&gcc_pcie_1_phy_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&gcc_ufs_mem_phy_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&gcc_ufs_phy_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&gcc_usb30_prim_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&gcc_usb3_phy_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&gpu_cc_cx_gdsc_hw_ctrl {
reg = <0x3d99124 0x4>;
};
&gpu_cc_cx_gdsc {
compatible = "regulator-fixed";
reg = <0x3d99110 0x4>;
status = "ok";
};
&gpu_cc_gx_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&video_cc_mvs0_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
&video_cc_mvs0c_gdsc {
compatible = "regulator-fixed";
status = "ok";
};
#include "kera-pinctrl.dtsi"

16
qcom/monaco-regulators.dtsi
View File

@@ -15,7 +15,7 @@
proxy-supply = <&VDD_CX_LEVEL>;
VDD_CX_LEVEL:
S1A_LEVEL: pm5100_s1_level: regulator-s1-level {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_s1_level";
qcom,set = <3>;
regulator-min-microvolt =
@@ -34,7 +34,7 @@
VDD_CX_FLOOR_LEVEL:
S1A_FLOOR_LEVEL:
pm5100_s1_floor_level: regulator-s1-floor-level {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_s1_floor_level";
qcom,set = <3>;
regulator-min-microvolt =
@@ -47,7 +47,7 @@
VDD_CX_LEVEL_AO:
S1A_LEVEL_AO: pm5100_s1_level_ao: regulator-s1-level-ao {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_s1_level_ao";
qcom,set = <1>;
regulator-min-microvolt =
@@ -103,7 +103,7 @@
qcom,resource-id = <0>;
VDD_LPI_CX_LEVEL:
L4A_LEVEL: pm5100_l4_level: regulator-l4-level {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l4_level";
qcom,set = <3>;
regulator-min-microvolt =
@@ -121,7 +121,7 @@
qcom,resource-id = <0>;
VDD_LPI_MX_LEVEL:
L5A_LEVEL: pm5100_l5_level: regulator-l5-level {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l5_level";
qcom,set = <3>;
regulator-min-microvolt =
@@ -163,7 +163,7 @@
VDD_EBI_LEVEL:
L3A_LEVEL:
pm5100_l3_level: regulator-pm5100-l3-level {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l3_level";
qcom,set = <3>;
regulator-min-microvolt =
@@ -182,7 +182,7 @@
VDD_EBI_LEVEL_AO:
L3A_LEVEL_AO:
pm5100_l3_level_ao: regulator-pm5100-l3-level-ao {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l3_level_ao";
qcom,set = <1>;
regulator-min-microvolt =
@@ -193,7 +193,7 @@
};
mx_cdev: mx-cdev-lvl {
/* compatible = "qcom,regulator-cooling-device"; */
compatible = "qcom,regulator-cooling-device";
regulator-cdev-supply = <&VDD_MXA_LEVEL>;
regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NONE
RPM_SMD_REGULATOR_LEVEL_NOM>;

6
qcom/monaco-usb.dtsi
View File

@@ -55,6 +55,12 @@
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
/*
* Establish dependency on smmu driver so that depopulate path of
* deferred probe doesn't run into existing bug in smmu driver.
*/
dummy-supply = <&apps_smmu>;
dwc3@4e00000 {
compatible = "snps,dwc3";
reg = <0x4e00000 0xcd00>;

379
qcom/msm-arm-smmu-ravelin.dtsi Normal file
View File

@@ -0,0 +1,379 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
kgsl_smmu: kgsl-smmu@3da0000 {
compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
reg = <0x3da0000 0x10000>,
<0x3dc2000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,use-3-lvl-tables;
qcom,num-context-banks-override = <0x5>;
qcom,num-smr-override = <0x7>;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
qcom,regulator-names = "vdd";
vdd-supply = <&gpu_cc_cx_gdsc>;
qcom,actlr =
/* All CBs of GFX: +15 deep PF */
<0x0 0x1FFF 0x32B>;
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>;
clock-names =
"gpu_cc_cx_gmu",
"gpu_cc_hub_cx_int",
"gpu_cc_hlos1_vote_gpu_smmu",
"gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb";
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
gfx_0_tbu: gfx_0_tbu@3dc5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x3dc5000 0x1000>,
<0x3dc2200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
};
gfx_1_tbu: gfx_1_tbu@3dc9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x3dc9000 0x1000>,
<0x3dc2208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
};
};
apps_smmu: apps-smmu@15000000 {
compatible = "qcom,qsmmu-v500";
reg = <0x15000000 0x100000>,
<0x151e2000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,use-3-lvl-tables;
qcom,num-context-banks-override = <0x52>;
qcom,num-smr-override = <0x85>;
qcom,handoff-smrs = <0x800 0x402>;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>;
qcom,actlr =
/* For video clients, +3 PF */
<0x1980 0x3F 0x103>,
/* Display and camera clients, +0 PF */
<0x1900 0x3F 0x1>,
<0x1800 0xFF 0x1>,
<0x800 0x7FF 0x1>;
clocks = <&gcc GCC_HLOS1_VOTE_MMU_TCU_CLK>;
clock-names =
"gcc_hlos1_vote_mmu_tcu_clk";
interconnects = <&gem_noc MASTER_APPSS_PROC
&cnoc3 SLAVE_TCU>;
qcom,active-only;
anoc_1_tbu: anoc_1_tbu@151e5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151e5000 0x1000>,
<0x151e2200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
qcom,iova-width = <36>;
qcom,micro-idle;
clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK>;
clock-names =
"gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk";
interconnects = <&gem_noc MASTER_APPSS_PROC
&cnoc3 SLAVE_IMEM>;
qcom,active-only;
};
anoc_2_tbu: anoc_2_tbu@151e9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151e9000 0x1000>,
<0x151e2208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
qcom,iova-width = <36>;
qcom,micro-idle;
clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK>;
clock-names =
"gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk";
interconnects = <&gem_noc MASTER_APPSS_PROC
&cnoc3 SLAVE_IMEM>;
qcom,active-only;
};
mnoc_hf_0_tbu: mnoc_hf_0_tbu@151ed000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151ed000 0x1000>,
<0x151e2210 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x800 0x400>;
qcom,iova-width = <32>;
qcom,micro-idle;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK>;
clock-names =
"gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk";
interconnects = <&mmss_noc MASTER_CAMNOC_HF
&mc_virt SLAVE_EBI1>;
qcom,active-only;
};
mnoc_hf_1_tbu: mnoc_hf_1_tbu@151f1000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f1000 0x1000>,
<0x151e2218 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0xc00 0x400>;
qcom,iova-width = <32>;
qcom,micro-idle;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK>;
clock-names =
"gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk";
interconnects = <&mmss_noc MASTER_CAMNOC_HF
&mc_virt SLAVE_EBI1>;
qcom,active-only;
};
lpass_tbu: lpass_tbu@151f5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f5000 0x1000>,
<0x151e2220 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1000 0x400>;
qcom,iova-width = <32>;
qcom,micro-idle;
clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK>;
clock-names =
"gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk";
interconnects = <&lpass_ag_noc MASTER_LPASS_PROC
&mc_virt SLAVE_EBI1>;
qcom,active-only;
};
pcie_tbu: pcie_tbu@151f9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f9000 0x1000>,
<0x151e2228 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1400 0x400>;
qcom,iova-width = <36>;
qcom,micro-idle;
clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK>;
clock-names =
"gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk";
interconnects = <&pcie_anoc MASTER_PCIE_0
&mc_virt SLAVE_EBI1>;
qcom,active-only;
};
sf_0_tbu: sf_0_tbu@151fd000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151fd000 0x1000>,
<0x151e2230 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1800 0x400>;
qcom,iova-width = <32>;
qcom,regulator-names = "vdd";
vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;
qcom,micro-idle;
clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK>;
clock-names =
"gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk";
interconnects = <&mmss_noc MASTER_CAMNOC_SF
&mc_virt SLAVE_EBI1>;
qcom,active-only;
};
};
dma_dev@0x0 {
compatible = "qcom,iommu-dma";
memory-region = <&system_cma>;
};
iommu_test_device {
compatible = "qcom,iommu-debug-test";
usecase0_apps {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
};
usecase1_apps_fastmap {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "fastmap";
};
usecase2_apps_atomic {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "atomic";
};
usecase3_apps_dma {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "atomic";
};
usecase4_apps_coherent {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e1 0>;
dma-coherent;
};
usecase5_kgsl_dma {
compatible = "qcom,iommu-debug-usecase";
iommus = <&kgsl_smmu 0x7 0x400>;
};
usecase6_kgsl_coherent {
compatible = "qcom,iommu-debug-usecase";
iommus = <&kgsl_smmu 0x407 0x400>;
dma-coherent;
};
usecase7_apps_secure {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "atomic";
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
};
};
};

1
qcom/parrot-idp.dtsi
View File

@@ -43,6 +43,7 @@
novatek@62 {
reg = <0x62>;
compatible = "novatek,NVT-ts";
interrupt-parent = <&tlmm>;
interrupts = <13 0x2008>;

16
qcom/parrot-pmic-overlay.dtsi
View File

@@ -169,10 +169,6 @@
};
};
&pm6150l_revid {
status = "disabled";
};
&pm6150l_4 {
qcom,power-on@800 {
status = "disabled";
@@ -422,16 +418,13 @@
pinctrl-0 = <&pm8010i_active>;
pm8010-chip@900 {
compatible = "qcom,pm8008-chip";
reg = <0x900>;
PM8010I_EN: qcom,pm8008-chip-en {
regulator-name = "pm8010i-chip-en";
};
};
qcom,revid@100 {
reg = <0x100>;
};
};
pm8010i@9 {
@@ -441,6 +434,7 @@
#size-cells = <0>;
qcom,pm8010i-regulator {
compatible = "qcom,pm8010-regulator";
#address-cells = <1>;
#size-cells = <0>;
@@ -517,16 +511,13 @@
pinctrl-0 = <&pm8010j_active>;
pm8010-chip@900 {
compatible = "qcom,pm8008-chip";
reg = <0x900>;
PM8010J_EN: qcom,pm8008-chip-en {
regulator-name = "pm8010j-chip-en";
};
};
qcom,revid@100 {
reg = <0x100>;
};
};
pm8010j@d {
@@ -536,6 +527,7 @@
#size-cells = <0>;
qcom,pm8010j-regulator {
compatible = "qcom,pm8010-regulator";
#address-cells = <1>;
#size-cells = <0>;

15
qcom/parrot-qupv3.dtsi
View File

@@ -19,6 +19,13 @@
* Qup1 5: SE 11
*/
qup_iommu_region: qup_iommu_region {
iommu-addresses = <&gpi_dma0 0x0 0x100000>, <&gpi_dma0 0x200000 0xffe00000>,
<&qupv3_0 0x0 0x40000000>, <&qupv3_0 0x50000000 0xb0000000>,
<&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xffe00000>,
<&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>;
};
/* GPI Instance */
gpi_dma0: qcom,gpi-dma@900000 {
compatible = "qcom,gpi-dma";
@@ -41,7 +48,7 @@
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0x3f>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
memory-region = <&qup_iommu_region>;
dma-coherent;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
@@ -57,7 +64,7 @@
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
iommus = <&apps_smmu 0x163 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
memory-region = <&qup_iommu_region>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
@@ -343,7 +350,7 @@
qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x3e>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
memory-region = <&qup_iommu_region>;
dma-coherent;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
@@ -359,7 +366,7 @@
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0x403 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
memory-region = <&qup_iommu_region>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;

248
qcom/parrot-thermal.dtsi
View File

@@ -257,8 +257,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
};
@@ -276,8 +276,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
};
@@ -295,8 +295,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
};
@@ -318,17 +318,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu4_emerg0: cpu4-emerg0-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
};
@@ -349,17 +349,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu4_emerg1: cpu4-emerg1-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
};
@@ -380,17 +380,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu5_emerg0: cpu5-emerg0-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -418,17 +418,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu5_emerg1: cpu5-emerg1-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -456,17 +456,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu6_emerg0: cpu6-emerg0-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -494,17 +494,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu6_emerg1: cpu6-emerg1-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -532,17 +532,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu7_emerg0: cpu7-emerg0-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -570,17 +570,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu7_emerg1: cpu7-emerg1-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -608,17 +608,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
gpu0_tj_cfg: tj_cfg {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -646,17 +646,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
gpu1_tj_cfg: tj_cfg {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -680,8 +680,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
};
@@ -699,8 +699,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
};
@@ -722,17 +722,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu0_emerg: cpu0-emerg-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -760,17 +760,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu1_emerg: cpu1-emerg-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -798,17 +798,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu2_emerg: cpu2-emerg-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -836,17 +836,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
cpu3_emerg: cpu3-emerg-cfg {
temperature = <110000>;
hysteresis = <10000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -874,17 +874,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
nspss_0_config: junction-config {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -913,17 +913,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
nspss_1_config: junction-config {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -952,17 +952,17 @@
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
};
nspss_2_config: junction-config {
temperature = <95000>;
hysteresis = <5000>;
type = "passive";
};
reset-mon-cfg {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
cooling-maps {
@@ -987,8 +987,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
};
@@ -1012,8 +1012,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
@@ -1062,8 +1062,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
};
@@ -1081,8 +1081,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
};
@@ -1100,8 +1100,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
};
@@ -1119,8 +1119,8 @@
reset-mon-cfg {
temperature = <115000>;
hysteresis = <5000>;
type = "passive";
hysteresis = <0>;
type = "hot";
};
};
};

22
qcom/parrot-usb.dtsi
View File

@@ -12,8 +12,8 @@
reg = <0xa600000 0x100000>;
reg-names = "core_base";
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
@@ -53,13 +53,19 @@
<&aggre1_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>;
dwc3@a600000 {
/*
* Establish dependency on smmu driver so that depopulate path of
* deferred probe doesn't run into existing bug in smmu driver.
*/
dummy-supply = <&apps_smmu>;
dwc3_0: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xd800>;
reg = <0x0 0xa600000 0x0 0xd800>;
iommus = <&apps_smmu 0x80 0x0>;
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
memory-region = <&dwc3_mem_region>;
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
@@ -79,6 +85,12 @@
};
dwc3_mem_region: dwc3_mem_region {
iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>,
<&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>;
};
/* USB port related High Speed PHY */
usb2_phy0: hsphy@88e3000 {
compatible = "qcom,usb-hsphy-snps-femto";

33
qcom/parrot.dtsi
View File

@@ -417,6 +417,12 @@
size = <0x0 0x2800000>;
};
kinfo_mem: debug_kinfo_region {
alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
size = <0x0 0x1000>;
no-map;
};
va_md_mem: va_md_mem_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
@@ -707,6 +713,17 @@
#interrupt-cells = <2>;
};
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
/* ipa - inbound entry from mss */
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-adsp {
@@ -1461,7 +1478,6 @@
reset-names = "core_reset";
iommus = <&apps_smmu 0x60 0x0>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
@@ -1524,7 +1540,6 @@
0x2C010800 0x80040868>;
iommus = <&apps_smmu 0x540 0x0>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
@@ -1772,6 +1787,7 @@
};
qcom_qseecom: qseecom@c1700000 {
compatible = "qcom,qseecom";
memory-region = <&qseecom_mem>;
qseecom_mem = <&qseecom_mem>;
qseecom_ta_mem = <&qseecom_ta_mem>;
@@ -1827,6 +1843,13 @@
};
};
qcom_rng: qrng@10c3000 {
compatible = "qcom,msm-rng";
reg = <0x10c3000 0x1000>;
qcom,no-qrng-config;
qcom,no-clock-support;
};
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xe10>;
reg-names = "phy_mem";
@@ -1965,6 +1988,7 @@
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,max-cpus = <8>;
status = "disabled";
qos0 {
@@ -2729,6 +2753,11 @@
compatible = "qcom,logbuf-vendor-hooks";
};
google,debug-kinfo {
compatible = "google,debug-kinfo";
memory-region = <&kinfo_mem>;
};
mini_dump_node {
compatible = "qcom,minidump";
status = "ok";

8
qcom/pineapple-usb.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
@@ -58,6 +58,12 @@
<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
/*
* Establish dependency on smmu driver so that depopulate path of
* deferred probe doesn't run into existing bug in smmu driver.
*/
dummy-supply = <&apps_smmu>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xd93c>;

3
qcom/pineapple-vm.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
@@ -318,6 +318,7 @@
qcom,mem-buf-msgq {
compatible = "qcom,mem-buf-msgq";
qcom,msgq-names = "trusted_vm";
};
virtio_mem_device {

24
qcom/pineapple.dtsi
View File

@@ -1479,11 +1479,20 @@
};
};
ufshc_dma_resv: ufshc_dma_resv_region {
/*
* Restrict IOVA mappings for UFSHC buffers to the 3 GB region
* from 0x1000 - 0xffffffff.
*/
iommu-addresses = <&ufshc_mem 0x0 0x1000>;
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>,
<0x1d88000 0x18000>;
reg-names = "ufs_mem", "ice";
<0x1d88000 0x18000>,
<0x1da5000 0x2000>, <0x1da4000 0x10>;
reg-names = "ufs_mem", "ice", "mcq_sqd", "mcq_vs";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
@@ -1492,7 +1501,7 @@
qcom,ice-use-hwkm;
qcom,prime-mask = <0x80>;
qcom,silver-mask = <0x0f>;
qcom,esi-affinity-mask = <0xf0>;
qcom,esi-affinity-mask = <0xe0>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
@@ -1594,11 +1603,17 @@
iommus = <&apps_smmu 0x60 0x0>;
qcom,iommu-dma = "fastmap";
qcom,iommu-msi-size = <0x1000>;
memory-region = <&ufshc_dma_resv>;
shared-ice-cfg = <&ice_cfg>;
dma-coherent;
qcom,bypass-pbl-rst-wa;
msi-parent = <&gic_its 0x60>;
qcom,max-cpus = <8>;
qcom,broken-ahit-wa;
status = "disabled";
qos0 {
@@ -2391,7 +2406,8 @@
};
qcom,mem-buf-msgq {
compatible = "qcom,mem-buf-msgq";
compatible = "qcom,mem-buf-msgq";
qcom,msgq-names = "trusted_vm";
};
qti,smmu-proxy {

11
qcom/platform_map.bzl
View File

@@ -191,6 +191,10 @@ _platform_map = {
{"name": "parrot-sg.dtb"},
{"name": "parrotp-sg.dtb"},
{"name": "parrot-4gb.dtb"},
{"name": "ravelin.dtb"},
{"name": "ravelinp.dtb"},
{"name": "ravelin-4gb.dtb"},
{"name": "ravelinp-4gb.dtb"},
],
"dtbo_list": [
# keep sorted
@@ -214,6 +218,13 @@ _platform_map = {
{"name": "parrot-idp-wcn6750-amoled-4gb-overlay.dtbo"},
{"name": "parrot-qrd-4gb-overlay.dtbo"},
{"name": "parrot-qrd-wcn6750-4gb-overlay.dtbo"},
{"name": "ravelin-rumi-overlay.dtbo"},
{"name": "ravelin-atp-overlay.dtbo"},
{"name": "ravelin-idp-overlay.dtbo"},
{"name": "ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo"},
{"name": "ravelin-qrd-overlay.dtbo"},
{"name": "ravelin-idp-wcn3988-4gb-overlay.dtbo"},
{"name": "ravelin-qrd-4gb-overlay.dtbo"},
],
},
}

146
qcom/pm5100-rpm-regulator.dtsi
View File

@@ -5,7 +5,7 @@
&rpm_bus {
rpm-regulator-smpa1 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <1>;
qcom,regulator-type = <1>;
@@ -13,7 +13,7 @@
status = "disabled";
regulator-s1 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_s1";
qcom,set = <3>;
status = "disabled";
@@ -21,7 +21,7 @@
};
rpm-regulator-smpa2 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <2>;
qcom,regulator-type = <1>;
@@ -29,7 +29,7 @@
status = "disabled";
regulator-s2 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_s2";
qcom,set = <3>;
status = "disabled";
@@ -37,7 +37,7 @@
};
rpm-regulator-smpa3 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <3>;
qcom,regulator-type = <1>;
@@ -45,7 +45,7 @@
status = "disabled";
regulator-s3 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_s3";
qcom,set = <3>;
status = "disabled";
@@ -53,7 +53,7 @@
};
rpm-regulator-smpa4 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <4>;
qcom,regulator-type = <1>;
@@ -61,7 +61,7 @@
status = "disabled";
regulator-s4 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_s4";
qcom,set = <3>;
status = "disabled";
@@ -69,7 +69,7 @@
};
rpm-regulator-smpa5 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "smpa";
qcom,resource-id = <5>;
qcom,regulator-type = <1>;
@@ -77,7 +77,7 @@
status = "disabled";
regulator-s5 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_s5";
qcom,set = <3>;
status = "disabled";
@@ -85,7 +85,7 @@
};
rpm-regulator-ldoa1 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <1>;
qcom,regulator-type = <0>;
@@ -94,7 +94,7 @@
status = "disabled";
regulator-l1 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l1";
qcom,set = <3>;
status = "disabled";
@@ -102,7 +102,7 @@
};
rpm-regulator-ldoa2 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <2>;
qcom,regulator-type = <0>;
@@ -111,7 +111,7 @@
status = "disabled";
regulator-l2 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l2";
qcom,set = <3>;
status = "disabled";
@@ -119,7 +119,7 @@
};
rpm-regulator-ldoa3 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <3>;
qcom,regulator-type = <0>;
@@ -128,7 +128,7 @@
status = "disabled";
regulator-l3 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l3";
qcom,set = <3>;
status = "disabled";
@@ -136,7 +136,7 @@
};
rpm-regulator-ldoa4 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <4>;
qcom,regulator-type = <0>;
@@ -145,7 +145,7 @@
status = "disabled";
regulator-l4 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l4";
qcom,set = <3>;
status = "disabled";
@@ -153,7 +153,7 @@
};
rpm-regulator-ldoa5 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <5>;
qcom,regulator-type = <0>;
@@ -162,7 +162,7 @@
status = "disabled";
regulator-l5 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l5";
qcom,set = <3>;
status = "disabled";
@@ -170,7 +170,7 @@
};
rpm-regulator-ldoa6 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <6>;
qcom,regulator-type = <0>;
@@ -179,7 +179,7 @@
status = "disabled";
regulator-l6 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l6";
qcom,set = <3>;
status = "disabled";
@@ -187,7 +187,7 @@
};
rpm-regulator-ldoa7 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <7>;
qcom,regulator-type = <0>;
@@ -196,7 +196,7 @@
status = "disabled";
regulator-l7 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l7";
qcom,set = <3>;
status = "disabled";
@@ -204,7 +204,7 @@
};
rpm-regulator-ldoa8 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <8>;
qcom,regulator-type = <0>;
@@ -213,7 +213,7 @@
status = "disabled";
regulator-l8 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l8";
qcom,set = <3>;
status = "disabled";
@@ -221,7 +221,7 @@
};
rpm-regulator-ldoa9 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <9>;
qcom,regulator-type = <0>;
@@ -230,7 +230,7 @@
status = "disabled";
regulator-l9 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l9";
qcom,set = <3>;
status = "disabled";
@@ -238,7 +238,7 @@
};
rpm-regulator-ldoa10 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <10>;
qcom,regulator-type = <0>;
@@ -247,7 +247,7 @@
status = "disabled";
regulator-l10 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l10";
qcom,set = <3>;
status = "disabled";
@@ -255,7 +255,7 @@
};
rpm-regulator-ldoa11 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <11>;
qcom,regulator-type = <0>;
@@ -264,7 +264,7 @@
status = "disabled";
regulator-l11 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l11";
qcom,set = <3>;
status = "disabled";
@@ -272,7 +272,7 @@
};
rpm-regulator-ldoa12 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <12>;
qcom,regulator-type = <0>;
@@ -281,7 +281,7 @@
status = "disabled";
regulator-l12 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l12";
qcom,set = <3>;
status = "disabled";
@@ -289,7 +289,7 @@
};
rpm-regulator-ldoa13 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <13>;
qcom,regulator-type = <0>;
@@ -298,7 +298,7 @@
status = "disabled";
regulator-l13 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l13";
qcom,set = <3>;
status = "disabled";
@@ -306,7 +306,7 @@
};
rpm-regulator-ldoa14 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <14>;
qcom,regulator-type = <0>;
@@ -315,7 +315,7 @@
status = "disabled";
regulator-l14 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l14";
qcom,set = <3>;
status = "disabled";
@@ -323,7 +323,7 @@
};
rpm-regulator-ldoa15 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <15>;
qcom,regulator-type = <0>;
@@ -332,7 +332,7 @@
status = "disabled";
regulator-l15 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l15";
qcom,set = <3>;
status = "disabled";
@@ -340,7 +340,7 @@
};
rpm-regulator-ldoa16 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <16>;
qcom,regulator-type = <0>;
@@ -349,7 +349,7 @@
status = "disabled";
regulator-l16 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l16";
qcom,set = <3>;
status = "disabled";
@@ -357,7 +357,7 @@
};
rpm-regulator-ldoa17 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <17>;
qcom,regulator-type = <0>;
@@ -366,7 +366,7 @@
status = "disabled";
regulator-l17 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l17";
qcom,set = <3>;
status = "disabled";
@@ -374,7 +374,7 @@
};
rpm-regulator-ldoa18 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <18>;
qcom,regulator-type = <0>;
@@ -383,7 +383,7 @@
status = "disabled";
regulator-l18 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l18";
qcom,set = <3>;
status = "disabled";
@@ -391,7 +391,7 @@
};
rpm-regulator-ldoa19 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <19>;
qcom,regulator-type = <0>;
@@ -400,7 +400,7 @@
status = "disabled";
regulator-l19 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l19";
qcom,set = <3>;
status = "disabled";
@@ -408,7 +408,7 @@
};
rpm-regulator-ldoa20 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <20>;
qcom,regulator-type = <0>;
@@ -417,7 +417,7 @@
status = "disabled";
regulator-l20 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l20";
qcom,set = <3>;
status = "disabled";
@@ -425,7 +425,7 @@
};
rpm-regulator-ldoa21 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <21>;
qcom,regulator-type = <0>;
@@ -434,7 +434,7 @@
status = "disabled";
regulator-l21 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l21";
qcom,set = <3>;
status = "disabled";
@@ -442,7 +442,7 @@
};
rpm-regulator-ldoa22 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <22>;
qcom,regulator-type = <0>;
@@ -451,7 +451,7 @@
status = "disabled";
regulator-l22 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l22";
qcom,set = <3>;
status = "disabled";
@@ -459,7 +459,7 @@
};
rpm-regulator-ldoa23 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <23>;
qcom,regulator-type = <0>;
@@ -468,7 +468,7 @@
status = "disabled";
regulator-l23 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l23";
qcom,set = <3>;
status = "disabled";
@@ -476,7 +476,7 @@
};
rpm-regulator-ldoa24 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <24>;
qcom,regulator-type = <0>;
@@ -485,7 +485,7 @@
status = "disabled";
regulator-l24 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l24";
qcom,set = <3>;
status = "disabled";
@@ -493,7 +493,7 @@
};
rpm-regulator-ldoa25 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <25>;
qcom,regulator-type = <0>;
@@ -502,7 +502,7 @@
status = "disabled";
regulator-l25 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l25";
qcom,set = <3>;
status = "disabled";
@@ -510,7 +510,7 @@
};
rpm-regulator-ldoa26 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <26>;
qcom,regulator-type = <0>;
@@ -519,7 +519,7 @@
status = "disabled";
regulator-l26 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l26";
qcom,set = <3>;
status = "disabled";
@@ -527,7 +527,7 @@
};
rpm-regulator-ldoa27 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <27>;
qcom,regulator-type = <0>;
@@ -536,7 +536,7 @@
status = "disabled";
regulator-l27 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l27";
qcom,set = <3>;
status = "disabled";
@@ -544,7 +544,7 @@
};
rpm-regulator-ldoa28 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <28>;
qcom,regulator-type = <0>;
@@ -553,7 +553,7 @@
status = "disabled";
regulator-l28 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l28";
qcom,set = <3>;
status = "disabled";
@@ -561,7 +561,7 @@
};
rpm-regulator-ldoa29 {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "ldoa";
qcom,resource-id = <29>;
qcom,regulator-type = <0>;
@@ -570,7 +570,7 @@
status = "disabled";
regulator-l29 {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_l29";
qcom,set = <3>;
status = "disabled";
@@ -578,7 +578,7 @@
};
rpm-regulator-boba {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "boba";
qcom,resource-id = <1>;
qcom,regulator-type = <4>;
@@ -587,14 +587,14 @@
status = "disabled";
regulator-pm5100a-bob {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100a_bob";
qcom,set = <3>;
status = "disabled";
};
regulator-pm5100a-bob-ao {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100a_bob_ao";
qcom,set = <1>;
status = "disabled";
@@ -602,7 +602,7 @@
};
rpm-regulator-chg-boost {
/* compatible = "qcom,rpm-smd-regulator-resource"; */
compatible = "qcom,rpm-smd-regulator-resource";
qcom,resource-name = "bsta";
qcom,resource-id = <1>;
qcom,regulator-type = <1>;
@@ -610,7 +610,7 @@
status = "disabled";
regulator-chg-boost {
/* compatible = "qcom,rpm-smd-regulator"; */
compatible = "qcom,rpm-smd-regulator";
regulator-name = "pm5100_chg_boost";
qcom,set = <3>;
status = "disabled";

78
qcom/pm6150l.dtsi
View File

@@ -20,11 +20,8 @@
#address-cells = <1>;
#size-cells = <0>;
pm6150l_revid: qcom,revid@100 {
reg = <0x100>;
};
qcom,power-on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
};
@@ -124,45 +121,15 @@
pm6150l_pwm_1: qcom,pwms@bc00 {
status = "disabled";
compatible = "qcom,pwm-lpg";
reg = <0xbc00>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <1>;
#pwm-cells = <2>;
};
pm6150l_lcdb: qcom,lcdb@ec00 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xec00>;
interrupts = <0x5 0xec 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "sc-irq";
qcom,pmic-revid = <&pm6150l_revid>;
qcom,voltage-step-ramp;
status = "disabled";
lcdb_ldo_vreg: ldo {
label = "ldo";
regulator-name = "lcdb_ldo";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <6000000>;
};
lcdb_ncp_vreg: ncp {
label = "ncp";
regulator-name = "lcdb_ncp";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <6000000>;
};
lcdb_bst_vreg: bst {
label = "bst";
regulator-name = "lcdb_bst";
regulator-min-microvolt = <4700000>;
regulator-max-microvolt = <6275000>;
};
};
flash_led: qcom,leds@d300 {
compatible = "qcom,pm6150l-flash-led-v2";
status = "disabled";
reg = <0xd300>;
label = "flash";
@@ -179,7 +146,6 @@
qcom,thermal-derate-en;
qcom,thermal-derate-current = <200 500 1000>;
qcom,isc-delay = <192>;
qcom,pmic-revid = <&pm6150l_revid>;
pm6150l_flash0: qcom,flash_0 {
label = "flash";
@@ -280,36 +246,8 @@
};
};
pm6150l_wled: qcom,wled@d800 {
reg = <0xd800>, <0xd900>;
reg-names = "wled-ctrl-base", "wled-sink-base";
label = "backlight";
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x5 0xd8 0x4 IRQ_TYPE_EDGE_BOTH>,
<0x5 0xd8 0x5 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "ovp-irq", "pre-flash-irq",
"flash-irq";
qcom,auto-calibration;
status = "disabled";
wled_flash: qcom,wled-flash {
label = "flash";
qcom,default-led-trigger = "wled_flash";
};
wled_torch: qcom,wled-torch {
label = "torch";
qcom,default-led-trigger = "wled_torch";
qcom,wled-torch-timer = <1200>;
};
wled_switch: qcom,wled-switch {
label = "switch";
qcom,default-led-trigger = "wled_switch";
};
};
pm6150l_lpg: qcom,pwms@b100 {
compatible = "qcom,pwm-lpg";
reg = <0xb100>, <0xb000>;
reg-names = "lpg-base", "lut-base";
#pwm-cells = <2>;
@@ -351,6 +289,7 @@
};
pm6150l_rgb_led: qcom,leds@d000 {
compatible = "qcom,tri-led";
reg = <0xd000>;
red {
label = "red";
@@ -375,6 +314,7 @@
};
pm6150a_amoled: qcom,amoled {
compatible = "qcom,amoled-regulator";
status = "disabled";
oledb_vreg: oledb@e000 {
@@ -421,16 +361,16 @@
type = "passive";
};
pm6150l_trip1: trip1 {
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "passive";
type = "critical";
};
};
};

7
qcom/pm6450.dtsi
View File

@@ -36,6 +36,7 @@
pm6450_pwm_1: qcom,pwms@e800 {
status = "disabled";
compatible = "qcom,pwm-lpg";
reg = <0xe800>;
reg-names = "lpg-base";
qcom,num-lpg-channels = <1>;
@@ -58,16 +59,16 @@
type = "passive";
};
pm6450_trip1: trip1 {
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
type = "hot";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "passive";
type = "critical";
};
};
};

10
qcom/pm7250b.dtsi
View File

@@ -21,6 +21,7 @@
#size-cells = <0>;
qcom,power-on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
};
@@ -199,6 +200,7 @@
#size-cells = <0>;
pm7250b_vib: qcom,vibrator@5300 {
compatible = "qcom,qpnp-vibrator-ldo";
reg = <0x5300>;
qcom,vib-ldo-volt-uv = <3000000>;
qcom,disable-overdrive;
@@ -220,16 +222,16 @@
type = "passive";
};
pm7250b_trip1: trip1 {
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
type = "hot";
};
pm7250b_trip2: trip2 {
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "passive";
type = "critical";
};
};
};

1
qcom/pm8350b.dtsi
View File

@@ -180,6 +180,7 @@
};
pm8350b_amoled: qcom,amoled {
compatible = "qcom,amoled-regulator";
#address-cells = <1>;
#size-cells = <0>;

532
qcom/pmi632.dtsi Normal file
View File

@@ -0,0 +1,532 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
pmi632_2: qcom,pmi632@2 {
compatible = "qcom,spmi-pmic";
reg = <2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi632_pon: qcom,power-on@800 {
reg = <0x800>;
};
pmi632_vadc: vadc@3100 {
compatible = "qcom,spmi-adc5-lite";
reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eoc-int-en-set";
#io-channel-cells = <1>;
io-channel-ranges;
/* Channel nodes */
ref_gnd {
reg = <ADC5_REF_GND>;
label = "ref_gnd";
qcom,pre-scaling = <1 1>;
};
vref_1p25 {
reg = <ADC5_1P25VREF>;
label = "vref_1p25";
qcom,pre-scaling = <1 1>;
};
die_temp {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
qcom,pre-scaling = <1 1>;
};
vph_pwr {
reg = <ADC5_VPH_PWR>;
label = "vph_pwr";
qcom,pre-scaling = <1 3>;
};
vbat_sns {
reg = <ADC5_VBAT_SNS>;
label = "vbat_sns";
qcom,pre-scaling = <1 3>;
};
usb_in_i_uv {
reg = <ADC5_USB_IN_I>;
label = "usb_in_i_uv";
qcom,pre-scaling = <1 1>;
};
chg_temp {
reg = <ADC5_CHG_TEMP>;
label = "chg_temp";
qcom,pre-scaling = <1 1>;
};
bat_therm {
reg = <ADC5_BAT_THERM_100K_PU>;
label = "bat_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
bat_therm_30k {
reg = <ADC5_BAT_THERM_30K_PU>;
label = "bat_therm_30k";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
bat_therm_400k {
reg = <ADC5_BAT_THERM_400K_PU>;
label = "bat_therm_400k";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
bat_id {
reg = <ADC5_BAT_ID_100K_PU>;
label = "bat_id";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
i_parallel {
reg = <ADC5_PARALLEL_ISENSE>;
label = "i_parallel";
qcom,pre-scaling = <1 1>;
};
};
pmi632_adc_tm: adc_tm@3500 {
reg = <0x3500>;
interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "threshold";
#address-cells = <1>;
#size-cells = <0>;
#thermal-sensor-cells = <1>;
};
pmi632_tz: qcom,temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
io-channels = <&pmi632_vadc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
qcom,schgm-flash@a600 {
reg = <0xa600>;
interrupts = <0x2 0xa6 0x2 IRQ_TYPE_EDGE_RISING>,
<0x2 0xa6 0x6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "flash-state-change",
"ilim2-s2";
qcom,flash-disable-soc = <10>;
};
pmi632_gpios: pinctrl@c000 {
reg = <0xc000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmi632_pbs_client3: qcom,pbs@7400 {
compatible = "qcom,qpnp-pbs";
reg = <0x7400>;
};
pmi632_sdam7: qcom,sdam@b600 {
compatible = "qcom,spmi-sdam";
reg = <0xb600>;
};
pmi632_bcl: bcl@3d00 {
compatible = "qcom,bcl-v5";
reg = <0x3d00>;
interrupts = <0x2 0x3d 0x0 IRQ_TYPE_NONE>,
<0x2 0x3d 0x1 IRQ_TYPE_NONE>,
<0x2 0x3d 0x2 IRQ_TYPE_NONE>;
interrupt-names = "bcl-lvl0",
"bcl-lvl1",
"bcl-lvl2";
qcom,ibat-use-qg-adc-5a;
#thermal-sensor-cells = <1>;
};
bcl_soc: bcl-soc {
compatible = "qcom,msm-bcl-soc";
#thermal-sensor-cells = <0>;
};
};
pmi632_3: qcom,pmi632@3 {
compatible ="qcom,spmi-pmic";
reg = <3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi632_vib: qcom,vibrator@5700 {
reg = <0x5700>;
qcom,vib-ldo-volt-uv = <3000000>;
qcom,disable-overdrive;
};
pmi632_pwm: qcom,pwms@b300 {
reg = <0xb300>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <5>;
nvmem-names = "ppg_sdam";
nvmem = <&pmi632_sdam7>;
qcom,pbs-client = <&pmi632_pbs_client3>;
qcom,lut-sdam-base = <0x80>;
qcom,lut-patterns = <0 0 0 14 28 42 56 70 84 100
100 84 70 56 42 28 14 0 0 0>;
lpg@1 {
qcom,lpg-chan-id = <1>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x48>;
};
lpg@2 {
qcom,lpg-chan-id = <2>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x56>;
};
lpg@3 {
qcom,lpg-chan-id = <3>;
qcom,ramp-step-ms = <200>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x64>;
};
};
pmi632_rgb: qcom,leds@d000 {
reg = <0xd000>;
red {
label = "red";
pwms = <&pmi632_pwm 0 1000000>;
led-sources = <0>;
linux,default-trigger = "timer";
};
green {
label = "green";
pwms = <&pmi632_pwm 1 1000000>;
led-sources = <1>;
linux,default-trigger = "timer";
};
blue {
label = "blue";
pwms = <&pmi632_pwm 2 1000000>;
led-sources = <2>;
linux,default-trigger = "timer";
};
};
pmi632_lcdb: qpnp-lcdb@ec00 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xec00>;
interrupts = <0x3 0xec 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "sc-irq";
qcom,voltage-step-ramp;
lcdb_ldo_vreg: ldo {
label = "ldo";
regulator-name = "lcdb_ldo";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <6000000>;
};
lcdb_ncp_vreg: ncp {
label = "ncp";
regulator-name = "lcdb_ncp";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <6000000>;
};
lcdb_bst_vreg: bst {
label = "bst";
regulator-name = "lcdb_bst";
regulator-min-microvolt = <4700000>;
regulator-max-microvolt = <6275000>;
};
};
flash_led: qcom,leds@d300 {
reg = <0xd300>;
label = "flash";
interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "led-fault-irq",
"all-ramp-down-done-irq",
"all-ramp-up-done-irq";
qcom,short-circuit-det;
qcom,open-circuit-det;
qcom,vph-droop-det;
qcom,thermal-derate-en;
qcom,thermal-derate-current = <200 500 1000>;
qcom,isc-delay = <192>;
pmi632_flash0: qcom,flash_0 {
label = "flash";
qcom,led-name = "led:flash_0";
qcom,max-current = <1500>;
qcom,default-led-trigger = "flash0_trigger";
qcom,id = <0>;
qcom,current-ma = <1000>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <400>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi632_flash1: qcom,flash_1 {
label = "flash";
qcom,led-name = "led:flash_1";
qcom,max-current = <1500>;
qcom,default-led-trigger = "flash1_trigger";
qcom,id = <1>;
qcom,current-ma = <1000>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <400>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi632_torch0: qcom,torch_0 {
label = "torch";
qcom,led-name = "led:torch_0";
qcom,max-current = <500>;
qcom,default-led-trigger = "torch0_trigger";
qcom,id = <0>;
qcom,current-ma = <300>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <400>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi632_torch1: qcom,torch_1 {
label = "torch";
qcom,led-name = "led:torch_1";
qcom,max-current = <500>;
qcom,default-led-trigger = "torch1_trigger";
qcom,id = <1>;
qcom,current-ma = <300>;
qcom,ires-ua = <12500>;
qcom,hdrm-voltage-mv = <400>;
qcom,hdrm-vol-hi-lo-win-mv = <100>;
};
pmi632_switch0: qcom,led_switch_0 {
label = "switch";
qcom,led-name = "led:switch_0";
qcom,led-mask = <3>;
qcom,default-led-trigger = "switch0_trigger";
};
pmi632_switch1: qcom,led_switch_1 {
label = "switch";
qcom,led-name = "led:switch_1";
qcom,led-mask = <2>;
qcom,default-led-trigger = "switch1_trigger";
};
};
};
};
&thermal_zones {
pmi632-tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmi632_tz>;
trips {
pmi632_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmi632_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "passive";
};
};
};
pmi632-ibat-lvl0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmi632_bcl 0>;
trips {
ibat_lvl0: ibat-lvl0 {
temperature = <4000>;
hysteresis = <200>;
type = "passive";
};
};
};
pmi632-ibat-lvl1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmi632_bcl 1>;
trips {
ibat_lvl1: ibat-lvl1 {
temperature = <5000>;
hysteresis = <200>;
type = "passive";
};
};
};
pmi632-bcl-lvl0 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmi632_bcl 5>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl0: b-bcl-lvl0 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pmi632-bcl-lvl1 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmi632_bcl 6>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl1: b-bcl-lvl1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pmi632-bcl-lvl2 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmi632_bcl 7>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl2: b-bcl-lvl2 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
socd {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&bcl_soc>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
socd_trip:socd-trip {
temperature = <90>;
hysteresis = <1>;
type = "passive";
};
};
};
};

13
qcom/pmk8350.dtsi
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@@ -4,6 +4,7 @@
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/qcom,qpnp-power-on.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
@@ -25,16 +26,28 @@
#size-cells = <0>;
pon_pbs@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
qcom,system-reset;
qcom,store-hard-reset-reason;
};
pmk8350_pon: pon_hlos@1300 {
compatible = "qcom,qpnp-power-on";
reg = <0x1300>;
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "kpdpwr", "resin";
qcom,pon_1 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
linux,code = <KEY_POWER>;
};
qcom,pon_2 {
qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
pmk8350_vadc: vadc@3100 {

14
qcom/ravelin-4gb.dts Normal file
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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin 4Gb SoC";
compatible = "qcom,ravelin";
qcom,board-id = <0 0x600>;
};

16
qcom/ravelin-4gb.dtsi Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin.dtsi"
#include "ravelin-low-memory.dtsi"
/ {
};
&mem_client_3_size {
qcom,peripheral-size = <0x200000>;
};
&soc {
};

16
qcom/ravelin-atp-overlay.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin ATP";
compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp";
qcom,msm-id = <568 0x10000>, <602 0x10000>;
qcom,board-id = <33 0>;
};

15
qcom/ravelin-atp.dts Normal file
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@@ -0,0 +1,15 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin.dtsi"
#include "ravelin-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin ATP";
compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp";
qcom,board-id = <33 0>;
};

144
qcom/ravelin-atp.dtsi Normal file
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@@ -0,0 +1,144 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-pmic-overlay.dtsi"
#include "ravelin-pm7250b.dtsi"
#include "ravelin-thermal-overlay.dtsi"
&soc {
};
&qupv3_se1_spi {
status = "ok";
#address-cells = <1>;
#size-cells = <0>;
qcom,spi-touch-active = "focaltech,fts_ts";
focaltech@0 {
reg = <0x0>;
spi-max-frequency = <6000000>;
interrupt-parent = <&tlmm>;
interrupts = <91 0x2008>;
focaltech,reset-gpio = <&tlmm 90 0x00>;
focaltech,irq-gpio = <&tlmm 91 0x2008>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,max-touch-number = <5>;
focaltech,ic-type = <0x3658D488>;
focaltech,touch-type = "primary";
vdd-supply = <&L4E>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
pinctrl-0 = <&ts_spi_active>;
pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>;
pinctrl-2 = <&ts_spi_release>;
};
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L5E>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L19B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-current-level = <0 325000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&sdhc_2 {
status = "ok";
vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
/*
* min/max voltages are voted on L24B/L28B and L24B/L28B_PBS
* regulators will only be voted for enabling/disabling conditions
* to support FR84471 for chipsets where PMIC doesn't support
* PBS ram sequence to turn OFF regulators automatically on
* multicard tray removal and these new regulator resources are
* exposed by PMIC team as part of this FR.
*/
vdd-en-dis-supply = <&L24B_PBS>;
vdd-io-supply = <&L28B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
vdd-io-en-dis-supply = <&L28B_PBS>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&ufsphy_mem {
/*
* Here parrot phy is used for ravelin as it
* do not have its own list for module load and
* hence compatible is using parrot.
* We have plan to improve this by making phy binary
* target independent.
*/
compatible = "qcom,ufs-phy-qmp-v4-waipio";
vdda-phy-supply = <&L5B>;
vdda-pll-supply = <&L16B>;
vdda-phy-max-microamp = <88530>;
vdda-pll-max-microamp = <18310>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L5E>;
vcc-max-microamp = <1056000>;
vccq-supply = <&L13B>;
vccq-max-microamp = <750000>;
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <100>;
/*
* ufs-dev-types and nvmem entries are for ufs device
* identification using nvmem interface. Use number of
* ufs devices supported for ufs-dev-types, and nvmem handle
* added by pmic for sdam register.
*
* Default value taken by driver is bit[0] = 0 for 3.x and
* bit[0] = 1 for 2.x driver code takes this as default case.
*
* But Bit value to identify ufs device is not consistent
* across the targets it could be bit[0] = 0/1 for UFS2.x/3x
* and vice versa. If the bit[0] value is not same as default
* value used in driver and if its reverted then use flag
* qcom,ufs-dev-revert to identify ufs device.
*/
ufs-dev-types = <2>;
qcom,ufs-dev-revert;
nvmem-cells = <&ufs_dev>, <&boot_config>;
nvmem-cell-names = "ufs_dev", "boot_conf";
status = "ok";
};
&battery_charger {
qcom,thermal-mitigation-step = <500000>;
qcom,wireless-charging-not-supported;
};

3727
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1584
qcom/ravelin-debug.dtsi Normal file
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File diff suppressed because it is too large Load Diff

43
qcom/ravelin-dma-heaps.dtsi Normal file
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@@ -0,0 +1,43 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
&soc {
qcom,dma-heaps {
compatible = "qcom,dma-heaps";
qcom,user_contig {
qcom,dma-heap-name = "qcom,user-contig";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&user_contig_mem>;
};
qcom,qseecom {
qcom,dma-heap-name = "qcom,qseecom";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_mem>;
};
qcom,qseecom_ta {
qcom,dma-heap-name = "qcom,qseecom-ta";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_ta_mem>;
};
qcom,audio_ml {
qcom,dma-heap-name = "qcom,audio-ml";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&audio_cma_mem>;
};
non_secure_display_dma_buf: qcom,display {
qcom,dma-heap-name = "qcom,display";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
qcom,max-align = <9>;
memory-region = <&non_secure_display_memory>;
};
};
};

16
qcom/ravelin-idp-overlay.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin IDP";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,msm-id = <568 0x10000>, <602 0x10000>;
qcom,board-id = <34 0>;
};

16
qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-idp-wcn3950-amoled-rcm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,msm-id = <568 0x10000>, <602 0x10000>;
qcom,board-id = <34 2>;
};

15
qcom/ravelin-idp-wcn3950-amoled-rcm.dts Normal file
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@@ -0,0 +1,15 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin.dtsi"
#include "ravelin-idp-wcn3950-amoled-rcm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,board-id = <34 2>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-idp.dtsi"
&soc {
};
&qupv3_se1_i2c {
status = "disabled";
};
&qupv3_se1_spi {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,touch-active = "goodix,gt9916S";
goodix-berlin@0 {
reg = <0>;
spi-max-frequency = <1000000>;
goodix,avdd-name = "avdd";
avdd-supply = <&L4E>;
interrupt-parent = <&tlmm>;
interrupts = <91 0x2008>;
goodix,reset-gpio = <&tlmm 90 0x00>;
goodix,irq-gpio = <&tlmm 91 0x2008>;
goodix,irq-flags = <2>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,firmware-name = "goodix_firmware_spi.bin";
goodix,config-name = "goodix_cfg_group_spi.bin";
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
pinctrl-0 = <&ts_spi_active>;
pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>;
pinctrl-2 = <&ts_spi_release>;
qcom,touch-environment = "pvm";
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-idp-wcn3988-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR + WCN3988";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,msm-id = <568 0x10000>, <602 0x10000>;
qcom,board-id = <34 0x601>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin-4gb.dtsi"
#include "ravelin-idp-wcn3988-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR + WCN3988";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,board-id = <34 0x601>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-idp.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin.dtsi"
#include "ravelin-idp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin IDP";
compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp";
qcom,board-id = <34 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-pmic-overlay.dtsi"
#include "ravelin-pm7250b.dtsi"
#include "ravelin-thermal-overlay.dtsi"
&soc {
};
&qupv3_se8_i2c {
awinic@64 {
reg = <0x64>;
awinic,red {
awinic,name = "red";
awinic,id = <0>;
awinic,imax = <2>;
awinic,led-current = <3>;
awinic,max-brightness = <255>;
awinic,rise-time-ms = <6>;
awinic,hold-time-ms = <0>;
awinic,fall-time-ms = <6>;
awinic,off-time-ms = <4>;
};
awinic,green {
awinic,name = "green";
awinic,id = <1>;
awinic,imax = <2>;
awinic,led-current = <3>;
awinic,max-brightness = <255>;
awinic,rise-time-ms = <6>;
awinic,hold-time-ms = <0>;
awinic,fall-time-ms = <6>;
awinic,off-time-ms = <4>;
};
awinic,blue {
awinic,name = "blue";
awinic,id = <2>;
awinic,imax = <2>;
awinic,led-current = <3>;
awinic,max-brightness = <255>;
awinic,rise-time-ms = <6>;
awinic,hold-time-ms = <0>;
awinic,fall-time-ms = <6>;
awinic,off-time-ms = <4>;
};
};
};
&qupv3_se1_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,i2c-touch-active = "focaltech,fts_ts";
focaltech@38 {
reg = <0x38>;
interrupt-parent = <&tlmm>;
interrupts = <13 0x2008>;
focaltech,reset-gpio = <&tlmm 12 0x00>;
focaltech,irq-gpio = <&tlmm 13 0x2008>;
focaltech,display-coords = <0 0 1080 2408>;
focaltech,max-touch-number = <10>;
focaltech,ic-type = <0x8726081C>;
focaltech,touch-type = "primary";
pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";
focaltech,trusted-touch-type = "primary";
focaltech,trusted-touch-spi-irq = <566>;
focaltech,trusted-touch-io-bases = <0x984000 0x910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x4000>;
focaltech,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0
&tlmm 12 0 &tlmm 13 0x2008>;
};
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L5E>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L19B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-current-level = <0 325000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&sdhc_2 {
status = "ok";
vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
/*
* min/max voltages are voted on L24B/L28B and L24B/L28B_PBS
* regulators will only be voted for enabling/disabling conditions
* to support FR84471 for chipsets where PMIC doesn't support
* PBS ram sequence to turn OFF regulators automatically on
* multicard tray removal and these new regulator resources are
* exposed by PMIC team as part of this FR.
*/
vdd-en-dis-supply = <&L24B_PBS>;
vdd-io-supply = <&L28B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
vdd-io-en-dis-supply = <&L28B_PBS>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&ufsphy_mem {
/*
* Here parrot phy is used for ravelin as it
* do not have its own list for module load and
* hence compatible is using parrot.
* We have plan to improve this by making phy binary
* target independent.
*/
compatible = "qcom,ufs-phy-qmp-v4-waipio";
vdda-phy-supply = <&L5B>;
vdda-pll-supply = <&L16B>;
vdda-phy-max-microamp = <88530>;
vdda-pll-max-microamp = <18310>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L5E>;
vcc-max-microamp = <1056000>;
vccq-supply = <&L13B>;
vccq-max-microamp = <750000>;
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <100>;
/*
* ufs-dev-types and nvmem entries are for ufs device
* identification using nvmem interface. Use number of
* ufs devices supported for ufs-dev-types, and nvmem handle
* added by pmic for sdam register.
*
* Default value taken by driver is bit[0] = 0 for 3.x and
* bit[0] = 1 for 2.x driver code takes this as default case.
*
* But Bit value to identify ufs device is not consistent
* across the targets it could be bit[0] = 0/1 for UFS2.x/3x
* and vice versa. If the bit[0] value is not same as default
* value used in driver and if its reverted then use flag
* qcom,ufs-dev-revert to identify ufs device.
*/
ufs-dev-types = <2>;
qcom,ufs-dev-revert;
nvmem-cells = <&ufs_dev>, <&boot_config>;
nvmem-cell-names = "ufs_dev", "boot_conf";
status = "ok";
};
&battery_charger {
qcom,thermal-mitigation-step = <500000>;
qcom,wireless-charging-not-supported;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&trust_ui_vm_mem {
status = "disabled";
};
&trust_ui_vm_qrtr {
status = "disabled";
};
&trust_ui_vm_vblk0_ring {
status = "disabled";
};
&trust_ui_vm_swiotlb {
status = "disabled";
};
&non_secure_display_dma_buf {
status = "disabled";
};
&non_secure_display_memory {
status = "disabled";
};
&soc {
qcom,guestvm_loader@e0b00000 {
status = "disabled";
};
qrtr-gunyah {
status = "disabled";
};
qcom,virtio_backend@0 {
status = "disabled";
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
/* smp2p information */
qcom,smp2p_interrupt_rdbg_2_out {
compatible = "qcom,smp2p-interrupt-rdbg-2-out";
qcom,smem-states = <&smp2p_rdbg2_out 0>;
qcom,smem-state-names = "rdbg-smp2p-out";
};
qcom,smp2p_interrupt_rdbg_2_in {
compatible = "qcom,smp2p-interrupt-rdbg-2-in";
interrupts-extended = <&smp2p_rdbg2_in 0 0>;
interrupt-names = "rdbg-smp2p-in";
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
#include <dt-bindings/gpio/gpio.h>
&soc {
pcie0: qcom,pcie@1c00000 {
compatible = "qcom,pci-msm";
reg = <0x01c00000 0x3000>,
<0x01c06000 0x2000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <0>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
interrupt-parent = <&pcie0>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie0_msi>;
perst-gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>;
wake-gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_perst_default
&pcie0_clkreq_default
&pcie0_wake_default>;
pinctrl-1 = <&pcie0_perst_default
&pcie0_clkreq_sleep
&pcie0_wake_default>;
gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
vreg-1p8-supply = <&L16B>;
vreg-0p9-supply = <&L5B>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
vreg-mx-supply = <&VDD_MX_LEVEL>;
qcom,vreg-1p8-voltage-level = <1200000 1200000 15070>;
qcom,vreg-0p9-voltage-level = <880000 880000 46890>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
interconnect-names = "icc_path";
interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
<&gcc GCC_QMIP_PCIE_AHB_CLK>,
<&pcie_0_pipe_clk>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
"pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_0_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk",
"pcie_pipe_clk_mux", "pcie_0_pipe_div2_clk",
"pcie_qmip_pcie_ahb_clk", "pcie_pipe_clk_ext_src";
max-clock-frequency-hz = <0>, <0>, <0>, <19200000>, <0>, <0>,
<0>, <0>, <0>, <0>, <0>, <100000000>,
<0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset";
dma-coherent;
qcom,smmu-sid-base = <0x1400>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,drv-supported;
qcom,drv-l1ss-timeout-us = <5000>;
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <150>;
qcom,slv-addr-space-size = <0x4000000>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,config-recovery;
qcom,pcie-phy-ver = <107>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
0x016c 0x08 0x0
0x0058 0x0f 0x0
0x00a4 0x42 0x0
0x0110 0x24 0x0
0x011c 0x03 0x0
0x0118 0xb4 0x0
0x010c 0x02 0x0
0x01bc 0x11 0x0
0x00bc 0x82 0x0
0x00d4 0x03 0x0
0x00d0 0x55 0x0
0x00cc 0x55 0x0
0x00b0 0x1a 0x0
0x00ac 0x0a 0x0
0x00c4 0x68 0x0
0x00e0 0x02 0x0
0x00dc 0xaa 0x0
0x00d8 0xab 0x0
0x00b8 0x34 0x0
0x00b4 0x14 0x0
0x0158 0x01 0x0
0x0074 0x06 0x0
0x007c 0x16 0x0
0x0084 0x36 0x0
0x0078 0x06 0x0
0x0080 0x16 0x0
0x0088 0x36 0x0
0x01b0 0x1e 0x0
0x01ac 0xca 0x0
0x01b8 0x18 0x0
0x01b4 0xa2 0x0
0x0050 0x07 0x0
0x0010 0x01 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0ee4 0x20 0x0
0x0e84 0x75 0x0
0x0e90 0x3f 0x0
0x115c 0x7f 0x0
0x1160 0xff 0x0
0x1164 0xbf 0x0
0x1168 0x3f 0x0
0x116c 0xd8 0x0
0x1170 0xdc 0x0
0x1174 0xdc 0x0
0x1178 0x5c 0x0
0x117c 0x34 0x0
0x1180 0xa6 0x0
0x1190 0x34 0x0
0x1194 0x38 0x0
0x10d8 0x0f 0x0
0x0e3c 0x12 0x0
0x0e40 0x01 0x0
0x10dc 0x00 0x0
0x104c 0x08 0x0
0x1050 0x08 0x0
0x1044 0xf0 0x0
0x11a4 0x38 0x0
0x10cc 0xf0 0x0
0x10f4 0x07 0x0
0x1008 0x09 0x0
0x1014 0x05 0x0
0x0694 0x00 0x0
0x0654 0x00 0x0
0x06a8 0x0f 0x0
0x0048 0x90 0x0
0x0620 0xc1 0x0
0x0388 0x77 0x0
0x0398 0x0b 0x0
0x02dc 0x05 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
0x04D0 0x04D4 0x03C0 0x0630 0x0230
0x0000>;
qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x0204 0x0730
0x0734 0x0738 0x073C>;
qcom,phy-debug-reg = <0x0068 0x0140 0x0144 0x0148 0x014C
0x0150 0x0160 0x0178 0x0ED0 0x0EDC
0x0F34 0x0F38 0x0f3C 0x0F40 0x0F44
0x0F48 0x0F4C 0x0F50 0x0F54 0x0F58
0x11E8 0x0A00 0x0A04 0x0A08 0x0A0C
0x0A10 0x0A14 0x0A18 0x0C20 0x0214
0x0218 0x021C 0x0220 0x0224 0x0228
0x022C 0x0230 0x0234 0x0238 0x023C
0x0600 0x0604 0x1204 0x1210>;
status = "disabled";
pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>;
};
};
pcie0_msi: qcom,pcie0_msi@0x17210040 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0x17210040 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/thermal/thermal_qti.h>
#include "pm7250b.dtsi"
&soc {
qcom,pmic_glink {
status = "okay";
};
qcom,pmic_glink_log {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
qcom,battery_debug {
compatible = "qcom,battery-debug";
};
qcom,charger_ulog_glink {
compatible = "qcom,charger-ulog-glink";
};
spmi_glink_debug: qcom,spmi_glink_debug {
compatible = "qcom,spmi-glink-debug";
#address-cells = <1>;
#size-cells = <0>;
depends-on-supply = <&spmi0_bus>;
/* Primary SPMI bus */
spmi@0 {
reg = <0>;
#address-cells = <2>;
#size-cells = <0>;
qcom,pm7250b-debug@8 {
compatible = "qcom,spmi-pmic";
reg = <8 SPMI_USID>;
qcom,can-sleep;
};
};
};
};
};
&glink_edge {
qcom,pmic_glink_rpmsg {
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
};
qcom,pmic_glink_log_rpmsg {
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
qcom,intents = <0x800 5
0xc00 3
0x2000 1>;
};
};
&battery_charger {
status = "okay";
};
&ucsi {
status = "okay";
};
&altmode {
status = "okay";
};
&spmi0_debug_bus {
qcom,pm7250b-debug@8 {
compatible = "qcom,spmi-pmic";
reg = <8 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm7250b-debug@9 {
compatible = "qcom,spmi-pmic";
reg = <9 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
};
&pm7250b_2 {
/* Slave ID - 8 */
reg = <8 SPMI_USID>;
};
&pm7250b_3 {
/* Slave ID - 9 */
reg = <9 SPMI_USID>;
};
&pm7250b_clkdiv {
clocks = <&rpmhcc RPMH_CXO_CLK>;
};
&pm7250b_vadc {
interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
pm7250b_usb_conn_therm {
reg = <ADC5_AMUX_THM3_100K_PU>;
label = "pm7250b_usb_conn_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm7250b_charger_skin_therm {
reg = <ADC5_AMUX_THM1_100K_PU>;
label = "pm7250b_charger_skin_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
&pm7250b_adc_tm {
interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>,
<&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>;
pm7250b_usb_conn_therm {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm7250b_charger_skin_therm {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&thermal_zones {
socd {
cooling-maps {
socd_cpu_6_7 {
trip = <&socd_trip>;
cooling-device = <&cpu_6_7_pause 1 1>;
};
socd_gpu0 {
trip = <&socd_trip>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pm7250b-ibat-lvl0 {
trips {
ibat-lvl0 {
temperature = <4000>;
};
};
};
pm7250b-ibat-lvl1 {
trips {
ibat-lvl1 {
temperature = <5000>;
};
};
};
pm7250b-bcl-lvl0 {
cooling-maps {
vbat_lte0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_lte_dsc 8 8>;
};
vbat_nr0_scg {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_scg_dsc 3 3>;
};
vbat_nr0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_dsc 6 6>;
};
vbat_cpu_4 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu4_pause 1 1>;
};
vbat_cpu_5 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu5_pause 1 1>;
};
vbat_cpu_6 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu6_pause 1 1>;
};
vbat_gpu0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pm7250b-bcl-lvl1 {
cooling-maps {
vbat_lte1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_lte_dsc 255 255>;
};
vbat_nr1_scg {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
vbat_nr1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_nr_dsc 255 255>;
};
vbat_cpu_7 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cpu7_pause 1 1>;
};
vbat_gpu1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
};
};
pm7250b-bcl-lvl2 {
cooling-maps {
vbat_gpu2 {
trip = <&b_bcl_lvl2>;
cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
};
};
};
sys-therm-9 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-7 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
&pm7250b_tz {
interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
};
&pm7250b_bcl {
interrupts = <0x8 0x1d 0x0 IRQ_TYPE_EDGE_RISING>,
<0x8 0x1d 0x1 IRQ_TYPE_EDGE_RISING>,
<0x8 0x1d 0x2 IRQ_TYPE_EDGE_RISING>;
};
&pm7250b_gpios {
display_panel_supply_ctrl {
display_panel_vddio_default: display_panel_vddio_default {
pins = "gpio11";
function = "normal";
input-disable;
output-enable;
bias-disable;
power-source = <0>;
qcom,drive-strength = <2>;
};
display_panel_extvdd_default: display_panel_extvdd_default {
pins = "gpio12";
function = "normal";
input-disable;
output-enable;
bias-disable;
power-source = <0>;
qcom,drive-strength = <2>;
};
};
};
&soc {
display_panel_vddio: display_gpio_regulator@1 {
compatible = "qti-regulator-fixed";
regulator-name = "display_panel_vddio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <233>;
gpio = <&pm7250b_gpios 11 0>;
enable-active-high;
regulator-boot-on;
proxy-supply = <&display_panel_vddio>;
qcom,proxy-consumer-enable;
pinctrl-names = "default";
pinctrl-0 = <&display_panel_vddio_default>;
};
display_panel_extvdd: display_gpio_regulator@2 {
compatible = "qti-regulator-fixed";
regulator-name = "display_panel_extvdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-enable-ramp-delay = <233>;
gpio = <&pm7250b_gpios 12 0>;
enable-active-high;
regulator-boot-on;
proxy-supply = <&display_panel_extvdd>;
qcom,proxy-consumer-enable;
pinctrl-names = "default";
pinctrl-0 = <&display_panel_extvdd_default>;
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/thermal/thermal_qti.h>
#include "pmi632.dtsi"
&soc {
qcom,pmic_glink {
status = "okay";
};
qcom,pmic_glink_log {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
qcom,battery_debug {
compatible = "qcom,battery-debug";
};
qcom,charger_ulog_glink {
compatible = "qcom,charger-ulog-glink";
};
spmi_glink_debug: qcom,spmi_glink_debug {
compatible = "qcom,spmi-glink-debug";
#address-cells = <1>;
#size-cells = <0>;
depends-on-supply = <&spmi0_bus>;
/* Primary SPMI bus */
spmi@0 {
reg = <0>;
#address-cells = <2>;
#size-cells = <0>;
qcom,pmi632-debug@2 {
compatible = "qcom,spmi-pmic";
reg = <2 SPMI_USID>;
qcom,can-sleep;
};
};
};
};
};
&glink_edge {
qcom,pmic_glink_rpmsg {
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
};
qcom,pmic_glink_log_rpmsg {
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
qcom,intents = <0x800 5
0xc00 3
0x2000 1>;
};
};
&battery_charger {
status = "okay";
};
&ucsi {
status = "okay";
};
&altmode {
status = "disabled";
};
&spmi0_debug_bus {
qcom,pmi632-debug@2 {
compatible = "qcom,spmi-pmic";
reg = <2 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pmi632-debug@3 {
compatible = "qcom,spmi-pmic";
reg = <3 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
};
&pmi632_gpios {
usb_conn_therm {
usb_conn_therm_default: usb_conn_therm_default {
pins = "gpio1";
bias-high-impedance;
};
};
charger_skin_temp {
charger_skin_temp_default: charger_skin_temp_default {
pins = "gpio3";
bias-high-impedance;
};
};
smb_skin_therm {
smb_skin_therm_default: smb_skin_therm_default {
pins = "gpio4";
bias-high-impedance;
};
};
};
&pmi632_vadc {
pinctrl-names = "default";
pinctrl-0 = <&usb_conn_therm_default &charger_skin_temp_default
&smb_skin_therm_default>;
pmi632_usb_conn_therm {
reg = <ADC5_GPIO1_100K_PU>;
label = "pmi632_usb_conn_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmi632_charger_skin_temp {
reg = <ADC5_GPIO2_100K_PU>;
label = "pmi632_charger_skin_temp";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmi632_smb_skin_therm {
reg = <ADC5_GPIO3_100K_PU>;
label = "pmi632_smb_skin_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
&pmi632_adc_tm {
io-channels = <&pmi632_vadc ADC5_GPIO1_100K_PU>,
<&pmi632_vadc ADC5_GPIO2_100K_PU>,
<&pmi632_vadc ADC5_GPIO3_100K_PU>;
pmi632_usb_conn_therm {
reg = <ADC5_GPIO1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmi632_charger_skin_temp {
reg = <ADC5_GPIO2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmi632_smb_skin_therm {
reg = <ADC5_GPIO3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&thermal_zones {
socd {
cooling-maps {
socd_cpu_6_7 {
trip = <&socd_trip>;
cooling-device = <&cpu_6_7_pause 1 1>;
};
socd_gpu0 {
trip = <&socd_trip>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pmi632-bcl-lvl0 {
cooling-maps {
vbat_lte0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_lte_dsc 8 8>;
};
vbat_nr0_scg {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_scg_dsc 3 3>;
};
vbat_nr0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_dsc 6 6>;
};
vbat_cpu_4 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu4_pause 1 1>;
};
vbat_cpu_5 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu5_pause 1 1>;
};
vbat_cpu_6 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu6_pause 1 1>;
};
vbat_gpu0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pmi632-bcl-lvl1 {
cooling-maps {
vbat_lte1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_lte_dsc 255 255>;
};
vbat_nr1_scg {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
vbat_nr1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&modem_nr_dsc 255 255>;
};
vbat_cpu_7 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cpu7_pause 1 1>;
};
vbat_gpu1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
};
};
pmi632-bcl-lvl2 {
cooling-maps {
vbat_gpu2 {
trip = <&b_bcl_lvl2>;
cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
};
};
};
sys-therm-9 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmi632_adc_tm ADC5_GPIO1_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-7 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmi632_adc_tm ADC5_GPIO2_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-8 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmi632_adc_tm ADC5_GPIO3_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
&flash_led {
qcom,use-qti-battery-interface;
};
&pmi632_lcdb {
status = "ok";
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pm6450.h>
#include <dt-bindings/gpio/gpio.h>
#include "pmk8350.dtsi"
#include "pm6450.dtsi"
&soc {
reboot_reason {
compatible = "qcom,reboot-reason";
nvmem-cells = <&restart_reason>;
nvmem-cell-names = "restart_reason";
};
pmic-pon-log {
compatible = "qcom,pmic-pon-log";
nvmem = <&pmk8350_sdam_5>;
nvmem-names = "pon_log";
};
};
&pmk8350 {
/delete-node/ pon_pbs@800;
/delete-node/ pon_hlos@1300;
pon_hlos@1300 {
compatible = "qcom,pm8998-pon";
reg = <0x1300>, <0x800>;
reg-names = "pon_hlos", "pon_pbs";
qcom,log-kpd-event;
pwrkey {
compatible = "qcom,pmk8350-pwrkey";
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
};
resin {
compatible = "qcom,pmk8350-resin";
interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
};
&pmk8350_vadc {
pinctrl-names = "default";
pinctrl-0 = <&quiet_therm_default &wide_rfc_therm_default
&rear_cam_flash_therm_default &pa_therm2_default &pa_therm1_default>;
/delete-node/ pm8350_ref_gnd;
/delete-node/ pm8350_vref_1p25;
/delete-node/ pm8350_die_temp;
/delete-node/ pm8350_vph_pwr;
/delete-node/ pm8350b_ref_gnd;
/delete-node/ pm8350b_vref_1p25;
/delete-node/ pm8350b_die_temp;
/delete-node/ pm8350b_vph_pwr;
/delete-node/ pm8350b_vbat_sns;
/delete-node/ pmr735b_ref_gnd;
/delete-node/ pmr735b_vref_1p25;
/delete-node/ pmr735b_die_temp;
/delete-node/ pmr735a_ref_gnd;
/delete-node/ pmr735a_vref_1p25;
/delete-node/ pmr735a_die_temp;
/* PM6450 Channel nodes */
pm6450_ref_gnd {
reg = <PM6450_ADC7_REF_GND>;
label = "pm6450_ref_gnd";
qcom,pre-scaling = <1 1>;
};
pm6450_vref_1p25 {
reg = <PM6450_ADC7_1P25VREF>;
label = "pm6450_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pm6450_die_temp {
reg = <PM6450_ADC7_DIE_TEMP>;
label = "pm6450_die_temp";
qcom,pre-scaling = <1 1>;
};
pm6450_quiet_therm {
reg = <PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
label = "pm6450_quiet_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmk8350_wide_rfc_therm {
reg = <PMK8350_ADC7_AMUX_THM2_100K_PU>;
label = "pmk8350_wide_rfc_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm6450_rear_cam_flash_therm {
reg = <PM6450_ADC7_AMUX4_GPIO5_100K_PU>;
label = "pm6450_rear_cam_flash_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm6450_pa_therm2 {
reg = <PM6450_ADC7_AMUX3_GPIO4_100K_PU>;
label = "pm6450_pa_therm2";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pmk8350_pa_therm1 {
reg = <PMK8350_ADC7_AMUX_THM3_100K_PU>;
label = "pmk8350_pa_therm1";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
pm8010_e: qcom,pm8010@4 {
compatible = "qcom,spmi-pmic";
reg = <4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8010e_tz: pm8010-e-temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
};
};
&pmk8350_adc_tm {
io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>,
<&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>,
<&pmk8350_vadc PMK8350_ADC7_AMUX_THM2_100K_PU>,
<&pmk8350_vadc PM6450_ADC7_AMUX4_GPIO5_100K_PU>,
<&pmk8350_vadc PM6450_ADC7_AMUX3_GPIO4_100K_PU>,
<&pmk8350_vadc PMK8350_ADC7_AMUX_THM3_100K_PU>;
pmk8350_xo_therm {
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm6450_quiet_therm {
reg = <PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmk8350_wide_rfc_therm {
reg = <PMK8350_ADC7_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm6450_rear_cam_flash_therm {
reg = <PM6450_ADC7_AMUX4_GPIO5_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm6450_pa2_therm {
reg = <PM6450_ADC7_AMUX3_GPIO4_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmk8350_pa1_therm {
reg = <PMK8350_ADC7_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&pmk8350_gpios {
wide_rfc_therm {
wide_rfc_therm_default: wide_rfc_therm_default {
pins = "gpio1";
bias-high-impedance;
};
};
pa_therm1 {
pa_therm1_default: pa_therm1_default {
pins = "gpio2";
bias-high-impedance;
};
};
};
&pmk8350_sdam_23 {
adc_scaling: scaling@bf {
reg = <0xbf 0x1>;
bits = <0 2>;
};
};
&pmk8350_sdam_1 {
ufs_dev: ufs_dev@94 {
reg = <0x94 0x1>;
bits = <0 0>;
};
};
&pm6450_gpios {
quiet_therm {
quiet_therm_default: quiet_therm_default {
pins = "gpio2";
bias-high-impedance;
};
};
rear_cam_flash_therm {
rear_cam_flash_therm_default: rear_cam_flash_therm_default {
pins = "gpio5";
bias-high-impedance;
};
};
pa_therm2 {
pa_therm2_default: pa_therm2_default {
pins = "gpio4";
bias-high-impedance;
};
};
};
&thermal_zones {
pm8010e_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8010e_tz>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
sys-therm-6 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM2_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX1_GPIO2_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX4_GPIO5_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-11 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX3_GPIO4_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM3_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
&tlmm {
key_vol_up_default: key_vol_up_default {
mux {
pins = "gpio53";
function = "gpio";
};
config {
pins = "gpio53";
drive-strength = <2>;
bias-pull-up;
input-enable;
};
};
pm8010m_active: pm8010m-active {
mux {
pins = "gpio29";
function = "gpio";
};
config {
pins = "gpio29";
bias-pull-up;
output-high;
drive-strength = <2>;
};
};
pm8010n_active: pm8010n-active {
mux {
pins = "gpio30";
function = "gpio";
};
config {
pins = "gpio30";
bias-pull-up;
output-high;
drive-strength = <2>;
};
};
};
&soc {
gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
vol_up {
label = "volume_up";
gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
/*
* Each QUP device that's a parent to PMIC must be listed as a critical device
* to GCC
*/
&gcc {
qcom,critical-devices = <&qupv3_se8_i2c>;
};
&qupv3_se8_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
pm8010m@8 {
compatible = "qcom,i2c-pmic";
reg = <0x8>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pm8010m_active>;
pm8010-chip@900 {
reg = <0x900>;
PM8010M_EN: qcom,pm8008-chip-en {
regulator-name = "pm8010m-chip-en";
};
};
qcom,revid@100 {
reg = <0x100>;
};
};
pm8010m@9 {
compatible = "qcom,i2c-pmic";
reg = <0x9>;
#address-cells = <1>;
#size-cells = <0>;
qcom,pm8010m-regulator {
#address-cells = <1>;
#size-cells = <0>;
pm8008_en-supply = <&PM8010M_EN>;
vdd_l1_l2-supply = <&S8B>;
L1M: pm8010m_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8010m_l1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1200000>;
qcom,min-dropout-voltage = <88000>;
qcom,hpm-min-load = <30000>;
};
L2M: pm8010m_l2: regulator@4100 {
reg = <0x4100>;
regulator-name = "pm8010m_l2";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,min-dropout-voltage = <80000>;
qcom,hpm-min-load = <30000>;
};
L3M: pm8010m_l3: regulator@4200 {
reg = <0x4200>;
regulator-name = "pm8010m_l3";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
qcom,hpm-min-load = <0>;
};
L4M: pm8010m_l4: regulator@4300 {
reg = <0x4300>;
regulator-name = "pm8010m_l4";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
qcom,hpm-min-load = <0>;
};
L6M: pm8010m_l6: regulator@4500 {
reg = <0x4500>;
regulator-name = "pm8010m_l6";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3000000>;
qcom,hpm-min-load = <0>;
};
L7M: pm8010m_l7: regulator@4600 {
reg = <0x4600>;
regulator-name = "pm8010m_l7";
regulator-min-microvolt = <2650000>;
regulator-max-microvolt = <2950000>;
qcom,hpm-min-load = <0>;
};
};
};
pm8010n@c {
compatible = "qcom,i2c-pmic";
reg = <0xc>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pm8010n_active>;
pm8010-chip@900 {
reg = <0x900>;
PM8010N_EN: qcom,pm8008-chip-en {
regulator-name = "pm8010n-chip-en";
};
};
qcom,revid@100 {
reg = <0x100>;
};
};
pm8010n@d {
compatible = "qcom,i2c-pmic";
reg = <0xd>;
#address-cells = <1>;
#size-cells = <0>;
qcom,pm8010n-regulator {
#address-cells = <1>;
#size-cells = <0>;
pm8008_en-supply = <&PM8010N_EN>;
vdd_l1_l2-supply = <&S8B>;
vdd_l3_l4-supply = <&S9B>;
L1N: pm8010n_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8010n_l1";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,min-dropout-voltage = <72000>;
qcom,hpm-min-load = <30000>;
};
L3N: pm8010n_l3: regulator@4200 {
reg = <0x4200>;
regulator-name = "pm8010n_l3";
regulator-min-microvolt = <1736000>;
regulator-max-microvolt = <3312000>;
qcom,hpm-min-load = <0>;
qcom,min-dropout-voltage = <120000>;
};
L4N: pm8010n_l4: regulator@4300 {
reg = <0x4300>;
regulator-name = "pm8010N_l4";
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <1900000>;
qcom,hpm-min-load = <0>;
qcom,min-dropout-voltage = <152000>;
};
L6N: pm8010n_l6: regulator@4500 {
reg = <0x4500>;
regulator-name = "pm8010n_l6";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3000000>;
qcom,hpm-min-load = <0>;
};
};
};
};
&pm6450_pwm_1 {
status = "ok";
};
&pm6450_gpios {
lcd_backlight_ctrl {
lcd_backlight_pwm_default: lcd_backlight_pwm_default {
pins = "gpio7";
function = "func1";
input-disable;
output-enable;
bias-disable;
power-source = <1>; /* 1.8V */
qcom,drive-strength = <2>;
};
lcd_backlight_en_default: lcd_backlight_en_default {
pins = "gpio6";
function = "normal";
input-disable;
output-enable;
bias-disable;
power-source = <0>;
qcom,drive-strength = <2>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
wil6210: qcom,wil6210 {
qcom,pcie-parent = <&pcie0>;
qcom,wigig-en = <&tlmm 91 0>;
pinctrl-names = "default";
pinctrl-0 = <&wil6210_refclk_en_pin>;
qcom,11ad-bus-bw,name = "wil6210";
qcom,11ad-bus-bw,num-cases = <3>;
qcom,11ad-bus-bw,num-paths = <1>;
qcom,11ad-bus-bw,vectors-KBps = <100 512 0 0>,
<100 512 600000 800000>,
<100 512 1300000 1300000>;
qcom,use-ext-supply;
vdd-s1c-supply = <&S9B>;
qcom,keep-radio-on-during-sleep;
qcom,use-ap-power-save;
status = "disabled";
};
};
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
wil6210_pci: wil6210_pci {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&wil6210_pci_iommu_group>;
#address-cells = <1>;
#size-cells = <1>;
wil6210_pci_iommu_group: wil6210_pci_iommu_group {
reg = <0 0>;
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
};
};
};
&tlmm {
talyn_pins {
wil6210_refclk_en_pin: wil6210_refclk_en_pin {
mux {
pins = "gpio83";
function = "gpio";
};
config {
pins = "gpio83";
drive-strength = <2>;
bias-pull-down;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-qrd-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR";
compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
qcom,msm-id = <568 0x10000>, <602 0x10000>;
qcom,board-id = <0x1000B 0x600>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin-4gb.dtsi"
#include "ravelin-qrd-4gb.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR";
compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
qcom,board-id = <0x1000B 0x600>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-qrd.dtsi"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin QRD";
compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>;
qcom,board-id = <0x1000B 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ravelin.dtsi"
#include "ravelin-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin QRD";
compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd";
qcom,board-id = <0x1000B 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ravelin-pmic-overlay.dtsi"
#include "ravelin-pmi632.dtsi"
#include "ravelin-thermal-overlay.dtsi"
&soc {
};
&qupv3_se1_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,i2c-touch-active = "focaltech,fts_ts";
focaltech@38 {
status = "ok";
reg = <0x38>;
interrupt-parent = <&tlmm>;
interrupts = <13 0x2008>;
focaltech,reset-gpio = <&tlmm 12 0x00>;
focaltech,irq-gpio = <&tlmm 13 0x2008>;
focaltech,display-coords = <0 0 1080 2408>;
focaltech,max-touch-number = <10>;
focaltech,ic-type = <0x8726081C>;
focaltech,touch-type = "primary";
focaltech,touch-environment = "pvm";
pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
};
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L5E>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L19B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-current-level = <0 325000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&sdhc_2 {
status = "ok";
vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
/*
* min/max voltages are voted on L24B/L28B and L24B/L28B_PBS
* regulators will only be voted for enabling/disabling conditions
* to support FR84471 for chipsets where PMIC doesn't support
* PBS ram sequence to turn OFF regulators automatically on
* multicard tray removal and these new regulator resources are
* exposed by PMIC team as part of this FR.
*/
vdd-en-dis-supply = <&L24B_PBS>;
vdd-io-supply = <&L28B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
vdd-io-en-dis-supply = <&L28B_PBS>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&ufsphy_mem {
/*
* Here parrot phy is used for ravelin as it
* do not have its own list for module load and
* hence compatible is using parrot.
* We have plan to improve this by making phy binary
* target independent.
*/
compatible = "qcom,ufs-phy-qmp-v4-waipio";
vdda-phy-supply = <&L5B>;
vdda-pll-supply = <&L16B>;
vdda-phy-max-microamp = <88530>;
vdda-pll-max-microamp = <18310>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L5E>;
vcc-max-microamp = <1056000>;
vccq-supply = <&L13B>;
vccq-max-microamp = <750000>;
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <100>;
/*
* ufs-dev-types and nvmem entries are for ufs device
* identification using nvmem interface. Use number of
* ufs devices supported for ufs-dev-types, and nvmem handle
* added by pmic for sdam register.
*
* Default value taken by driver is bit[0] = 0 for 3.x and
* bit[0] = 1 for 2.x driver code takes this as default case.
*
* But Bit value to identify ufs device is not consistent
* across the targets it could be bit[0] = 0/1 for UFS2.x/3x
* and vice versa. If the bit[0] value is not same as default
* value used in driver and if its reverted then use flag
* qcom,ufs-dev-revert to identify ufs device.
*/
ufs-dev-types = <2>;
qcom,ufs-dev-revert;
nvmem-cells = <&ufs_dev>, <&boot_config>;
nvmem-cell-names = "ufs_dev", "boot_conf";
status = "ok";
};
&usb0 {
dwc3@a600000 {
usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
maximum-speed = "high-speed";
};
};
&usb_qmp_dp_phy {
status = "disabled";
};
&usb2_phy0 {
qcom,param-override-seq =
<0x86 0x6c>;
};
&battery_charger {
qcom,thermal-mitigation-step = <500000>;
qcom,wireless-charging-not-supported;
qcom,thermal-mitigation = <11500000 11000000 10500000 10000000 9500000
9000000 8500000 8000000 7500000 7000000 6500000
6000000 5500000 5000000 4500000 4000000 3500000
3000000 2500000 2000000 1500000 1000000 500000>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
/* QUPv3 SE Instances
* Qup0 0: SE 0
* Qup0 1: SE 1
* Qup0 2: SE 2
* Qup0 3: SE 3
* Qup0 4: SE 4
* Qup1 0: SE 5
* Qup1 1: SE 6
* Qup1 2: SE 7
* Qup1 3: SE 8
* Qup1 4: SE 9
*/
/* GPI Instance */
gpi_dma0: qcom,gpi-dma@900000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0x900000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x176 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x3e>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
dma-coherent;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
};
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x9c0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
iommus = <&apps_smmu 0x163 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
status = "ok";
/* HS UART Instance */
qupv3_se2_4uart: qcom,qup_uart@988000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0x988000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 17 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>,
<&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>;
pinctrl-1 = <&qupv3_se2_cts>, <&qupv3_se2_rts>,
<&qupv3_se2_tx>, <&qupv3_se2_rx>;
pinctrl-2 = <&qupv3_se2_cts>, <&qupv3_se2_rts>,
<&qupv3_se2_tx>, <&qupv3_se2_default_rx>;
pinctrl-3 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>,
<&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>;
qcom,wakeup-byte = <0xFD>;
status = "disabled";
};
/* HST Debug UART Instance */
qupv3_se0_2uart: qcom,qup_uart@980000 {
compatible = "qcom,geni-debug-uart";
reg = <0x980000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_2uart_tx_active>, <&qupv3_se0_2uart_rx_active>;
pinctrl-1 = <&qupv3_se0_2uart_sleep>;
status = "disabled";
};
qupv3_se0_i2c: i2c@980000 {
compatible = "qcom,i2c-geni";
reg = <0x980000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
dmas = <&gpi_dma0 0 0 3 64 0>,
<&gpi_dma0 1 0 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se1_i2c: i2c@984000 {
compatible = "qcom,i2c-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
dmas = <&gpi_dma0 0 1 3 64 2>,
<&gpi_dma0 1 1 3 64 2>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se1_spi: spi@984000 {
compatible = "qcom,spi-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
dmas = <&gpi_dma0 0 1 1 64 2>,
<&gpi_dma0 1 1 1 64 2>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se3_i2c: i2c@98c000 {
compatible = "qcom,i2c-geni";
reg = <0x98c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
dmas = <&gpi_dma0 0 3 3 64 0>,
<&gpi_dma0 1 3 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se3_spi: spi@98c000 {
compatible = "qcom,spi-geni";
reg = <0x98c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
<&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
pinctrl-1 = <&qupv3_se3_spi_sleep>;
dmas = <&gpi_dma0 0 3 1 64 0>,
<&gpi_dma0 1 3 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se4_i2c: i2c@990000 {
compatible = "qcom,i2c-geni";
reg = <0x990000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
dmas = <&gpi_dma0 0 4 3 64 0>,
<&gpi_dma0 1 4 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se4_spi: spi@990000 {
compatible = "qcom,spi-geni";
reg = <0x990000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
pinctrl-1 = <&qupv3_se4_spi_sleep>;
dmas = <&gpi_dma0 0 4 1 64 0>,
<&gpi_dma0 1 4 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
};
/* GPI Instance */
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0xa00000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x416 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0x3f>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
dma-coherent;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0x403 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
ranges;
status = "ok";
/* PORed Debug UART Instance */
qupv3_se7_2uart: qcom,qup_uart@a88000 {
compatible = "qcom,geni-debug-uart";
reg = <0xa88000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>;
pinctrl-1 = <&qupv3_se7_2uart_sleep>;
status = "disabled";
};
qupv3_se5_i2c: i2c@a80000 {
compatible = "qcom,i2c-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
dmas = <&gpi_dma1 0 0 3 64 0>,
<&gpi_dma1 1 0 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se5_spi: spi@a80000 {
compatible = "qcom,spi-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
pinctrl-1 = <&qupv3_se5_spi_sleep>;
dmas = <&gpi_dma1 0 0 1 64 0>,
<&gpi_dma1 1 0 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se6_i2c: i2c@a84000 {
compatible = "qcom,i2c-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
dmas = <&gpi_dma1 0 1 3 64 0>,
<&gpi_dma1 1 1 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se6_spi: spi@a84000 {
compatible = "qcom,spi-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
pinctrl-1 = <&qupv3_se6_spi_sleep>;
dmas = <&gpi_dma1 0 1 1 64 0>,
<&gpi_dma1 1 1 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se8_i2c: i2c@a8c000 {
compatible = "qcom,i2c-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
dmas = <&gpi_dma1 0 3 3 64 0>,
<&gpi_dma1 1 3 3 64 0>;
dma-names = "tx", "rx";
qcom,shared;
status = "disabled";
};
qupv3_se8_spi: spi@a8c000 {
compatible = "qcom,spi-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
pinctrl-1 = <&qupv3_se8_spi_sleep>;
dmas = <&gpi_dma1 0 3 1 64 0>,
<&gpi_dma1 1 3 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se9_i2c: i2c@a90000 {
compatible = "qcom,i2c-geni";
reg = <0xa90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
dmas = <&gpi_dma1 0 4 3 64 0>,
<&gpi_dma1 1 4 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se9_spi: spi@a90000 {
compatible = "qcom,spi-geni";
reg = <0xa90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
<&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>;
pinctrl-1 = <&qupv3_se9_spi_sleep>;
dmas = <&gpi_dma1 0 4 1 64 0>,
<&gpi_dma1 1 4 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
&apps_rsc_drv2 {
rpmh-regulator-msslvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "mss.lvl";
VDD_MODEM_LEVEL:
S1B_LEVEL:
pm6450_s1_level: regulator-pm6450-s1-level {
regulator-name = "pm6450_s1_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-cxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "cx.lvl";
proxy-supply = <&VDD_CX_LEVEL>;
VDD_CX_LEVEL:
S5B_LEVEL:
pm6450_s5_level: regulator-pm6450-s5-level {
regulator-name = "pm6450_s5_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-voltage =
<RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_CX_LEVEL_AO:
S5B_LEVEL_AO:
pm6450_s5_level_ao: regulator-pm6450-s5-level-ao {
regulator-name = "pm6450_s5_level_ao";
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-ebilvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "ebi.lvl";
VDD_EBI_LEVEL:
S6B_LEVEL:
pm6450_s6_level: regulator-pm6450-s6-level {
regulator-name = "pm6450_s6_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-smpb7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb7";
S7B:
pm6450_s7: regulator-pm6450-s7 {
regulator-name = "pm6450_s7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
qcom,init-voltage = <1120000>;
};
};
rpmh-regulator-smpb8 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb8";
S8B:
pm6450_s8: regulator-pm6450-s8 {
regulator-name = "pm6450_s8";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <382000>;
regulator-max-microvolt = <1744000>;
qcom,init-voltage = <1352000>;
};
};
rpmh-regulator-smpb9 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb9";
S9B:
pm6450_s9: regulator-pm6450-s9 {
regulator-name = "pm6450_s9";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <2040000>;
qcom,init-voltage = <1872000>;
};
};
rpmh-regulator-ldob1 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob1";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L1B:
pm6450_l1: regulator-pm6450-l1 {
regulator-name = "pm6450_l1";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <650000>;
qcom,init-voltage = <504000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-lcxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "lcx.lvl";
VDD_LPI_CX_LEVEL:
L2B_LEVEL:
pm6450_l2_level: regulator-pm6450-l2-level {
regulator-name = "pm6450_l2_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-ldob3 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob3";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L3B:
pm6450_l3: regulator-pm6450-l3 {
regulator-name = "pm6450_l3";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
qcom,init-voltage = <904000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob4 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob4";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L4B:
pm6450_l4: regulator-pm6450-l4 {
regulator-name = "pm6450_l4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <860000>;
qcom,init-voltage = <808000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob5 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob5";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L5B:
pm6450_l5: regulator-pm6450-l5 {
regulator-name = "pm6450_l4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <1052000>;
qcom,init-voltage = <880000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob6 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob6";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L6B:
pm6450_l6: regulator-pm6450-l6 {
regulator-name = "pm6450_l6";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
qcom,init-voltage = <824000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob7";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L7B:
pm6450_l7: regulator-pm6450-l7 {
regulator-name = "pm6450_l7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <830000>;
regulator-max-microvolt = <920000>;
qcom,init-voltage = <912000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-lmxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "lmx.lvl";
VDD_LPI_MX_LEVEL:
L8B_LEVEL:
pm6450_l8_level: regulator-pm6450-l8-level {
regulator-name = "pm6450_l8_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-ldob9 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob9";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L9B:
pm6450_l9: regulator-pm6450-l9 {
regulator-name = "pm6450_l9";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <504000>;
regulator-max-microvolt = <824000>;
qcom,init-voltage = <752000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob10 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob10";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L10B:
pm6450_l10: regulator-pm6450-l10 {
regulator-name = "pm6450_l10";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <824000>;
regulator-max-microvolt = <901000>;
qcom,init-voltage = <824000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob11 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob11";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L11B:
pm6450_l11: regulator-pm6450-l11 {
regulator-name = "pm6450_l11";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <752000>;
qcom,init-voltage = <348000>;
};
};
rpmh-regulator-ldob12 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob12";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L12B:
pm6450_l12: regulator-pm6450-l12 {
regulator-name = "pm6450_l12";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
qcom,init-voltage = <1080000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob13 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob13";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L13B:
pm6450_l13: regulator-pm6450-l13 {
regulator-name = "pm6450_l13";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob14 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob14";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L14B:
pm6450_l14: regulator-pm6450-l14 {
regulator-name = "pm6450_l14";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1245000>;
regulator-max-microvolt = <1304000>;
qcom,init-voltage = <1150000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob16 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob16";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L16B:
pm6450_l16: regulator-pm6450-l16 {
regulator-name = "pm6450_l16";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <1260000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob17 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob17";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L17B:
pm6450_l17: regulator-pm6450-l17 {
regulator-name = "pm6450_l17";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob18 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob18";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L18B:
pm6450_l18: regulator-pm6450-l18 {
regulator-name = "pm6450_l18";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
qcom,init-voltage = <1504000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob19 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob19";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L19B:
pm6450_l19: regulator-pm6450-l19 {
regulator-name = "pm6450_l19";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1950000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob20 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob20";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L20B:
pm6450_l20: regulator-pm6450-l20 {
regulator-name = "pm6450_l20";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
qcom,init-voltage = <1700000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob21 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob21";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L21B:
pm6450_l21: regulator-pm6450-l21 {
regulator-name = "pm6450_l21";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob22 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob22";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L22B:
pm6450_l22: regulator-pm6450-l22 {
regulator-name = "pm6450_l22";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob23 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob23";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L23B:
pm6450_l23: regulator-pm6450-l23 {
regulator-name = "pm6450_l23";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob24 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob24";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L24B:
pm6450_l24: regulator-pm6450-l24 {
regulator-name = "pm6450_l24";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <2700000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob25 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob25";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L25B:
pm6450_l25: regulator-pm6450-l25 {
regulator-name = "pm6450_l25";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <3072000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob26 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob26";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L26B:
pm6450_l26: regulator-pm6450-l26 {
regulator-name = "pm6450_l26";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <1620000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob27 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob27";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L27B:
pm6450_l27: regulator-pm6450-l27 {
regulator-name = "pm6450_l27";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <1620000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob28 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob28";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L28B:
pm6450_l28: regulator-pm6450-l28 {
regulator-name = "pm6450_l28";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <2700000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoe1 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe1";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>;
L1E:
pm8010l_l1: regulator-pm8010-l1 {
regulator-name = "pm8010_l1";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <864000>;
qcom,init-voltage = <530000>;
};
};
rpmh-regulator-ldoe3 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe3";
qcom,regulator-type = "pmic5-ldo";
/* mode voting is not allowed */
L3E:
pm8010l_l3: regulator-pm8010-l3 {
regulator-name = "pm8010_l3";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3300000>;
qcom,init-voltage = <2700000>;
};
};
rpmh-regulator-ldoe4 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe4";
qcom,regulator-type = "pmic5-ldo";
/* mode voting is not allowed */
L4E:
pm8010_l4: regulator-pm8010-l4 {
regulator-name = "pm8010_l4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <3312000>;
qcom,init-voltage = <2700000>;
};
};
rpmh-regulator-ldoe5 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe5";
qcom,regulator-type = "pmic5-ldo";
/* mode voting is not allowed */
L5E:
pm8010_l5: regulator-pm8010-l5 {
regulator-name = "pm8010_l5";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
/*
* Remove min/max voltages for this regulator as initial
* voltage of L5E is set to be 2.4v/2.96v during PON
* depending upon the UFS mode. UFS is the only client
* on this and this regulator will only be voted
* for enabling/disabling conditions.
*/
};
};
rpmh-regulator-ldoe6 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe6";
qcom,regulator-type = "pmic5-ldo";
/* mode voting is not allowed */
L6E:
pm8010_l6: regulator-pm8010-l6 {
regulator-name = "pm8010_l6";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3312000>;
qcom,init-voltage = <3000000>;
};
};
rpmh-regulator-ldoe7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoe7";
qcom,regulator-type = "pmic5-ldo";
/* mode voting is not allowed */
L7E:
pm8010_l7: regulator-pm8010-l7 {
regulator-name = "pm8010_l7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3544000>;
qcom,init-voltage = <3000000>;
};
};
rpmh-regulator-mxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "mx.lvl";
proxy-supply = <&VDD_MX_LEVEL>;
VDD_MX_LEVEL:
S1G_LEVEL:
pmg1110_s1_level: regulator-pmg1110-s1-level {
regulator-name = "pmg1110_s1_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-voltage =
<RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_MAX>;
};
};
rpmh-regulator-sf1-vreg-enable {
compatible = "qcom,rpmh-xob-regulator";
qcom,resource-name = "gpioi7";
status = "disabled";
sf1_vreg_enable: regulator-sf1-vreg-enable {
regulator-name = "sf1_vreg_enable";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
};
};
rpmh-regulator-sf1-vreg-mode {
compatible = "qcom,rpmh-xob-regulator";
qcom,resource-name = "gpioi10";
status = "disabled";
sf1_vreg_mode: regulator-sf1-vreg-mode {
regulator-name = "sf1_vreg_mode";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
};
};
rpmh-regulator-vrmsd {
compatible = "qcom,rpmh-pbs-regulator";
qcom,resource-name = "vrm.sd";
L24B_PBS:
pm6450_l24_pbs: regulator-pm6450-l24-pbs {
regulator-name = "pm6450_l24_pbs";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
/*
* min/max voltages are voted on L24B and this regulator will
* only be voted for enabling/disabling conditions.
*/
};
};
rpmh-regulator-vrmpx2 {
compatible = "qcom,rpmh-pbs-regulator";
qcom,resource-name = "vrm.px2";
L28B_PBS:
pm6450_l28_pbs: regulator-pm6450-l28-pbs {
regulator-name = "pm6450_l28_pbs";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
/*
* min/max voltages are voted on L28B and this regulator will
* only be voted for enabling/disabling conditions.
*/
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp_region@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x600000>;
};
xbl_dtlog_mem: xbl_dtlog_region@80600000 {
no-map;
reg = <0x0 0x80600000 0x0 0x40000>;
};
xbl_ramdump_mem: xbl_ramdump_region@80640000 {
no-map;
reg = <0x0 0x80640000 0x0 0x1c0000>;
};
aop_image_mem: aop_image_region@80800000 {
no-map;
reg = <0x0 0x80800000 0x0 0x60000>;
};
aop_cmd_db_mem: aop_cmd_db_region@80860000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x80860000 0x0 0x20000>;
};
aop_config_mem: aop_config_region@80880000 {
no-map;
reg = <0x0 0x80880000 0x0 0x20000>;
};
tme_crash_dump_mem: tme_crash_dump_region@808a0000 {
no-map;
reg = <0x0 0x808a0000 0x0 0x40000>;
};
tme_log_mem: tme_log_region@808e0000 {
no-map;
reg = <0x0 0x808e0000 0x0 0x4000>;
};
uefi_log_mem: uefi_log_region@808e4000 {
no-map;
reg = <0x0 0x808e4000 0x0 0x10000>;
};
chipinfo_mem: chipinfo_region@808f4000 {
no-map;
reg = <0x0 0x808f4000 0x0 0x1000>;
};
smem_mem: smem_region@80900000 {
no-map;
reg = <0x0 0x80900000 0x0 0x200000>;
};
cpucp_fw_mem: cpucp_fw_region@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
wlan_msa_mem: wlan_msa_mem_region@82a00000 {
no-map;
reg = <0x0 0x82a00000 0x0 0xc00000>;
};
camera_mem: camera_region@84b00000 {
no-map;
reg = <0x0 0x84b00000 0x0 0x800000>;
};
wpss_moselle_mem: wpss_moselle_region@85300000 {
no-map;
reg = <0x0 0x85300000 0x0 0x1900000>;
};
video_mem: video_region@86c00000 {
no-map;
reg = <0x0 0x86c00000 0x0 0x700000>;
};
adsp_mem: adsp_region@87300000 {
no-map;
reg = <0x0 0x87300000 0x0 0x2100000>;
};
ipa_fw_mem: ipa_fw_region@89400000 {
no-map;
reg = <0x0 0x89400000 0x0 0x10000>;
};
ipa_gsi_mem: ipa_gsi_region@89410000 {
no-map;
reg = <0x0 0x89410000 0x0 0xa000>;
};
gpu_microcode_mem: gpu_microcode_region@8941a000 {
no-map;
reg = <0x0 0x8941a000 0x0 0x2000>;
};
mpss_mem: mpss_region@8a000000 {
no-map;
reg = <0x0 0x8a000000 0x0 0xda00000>;
};
xbl_sc_mem: xbl_sc_region@a6e00000 {
no-map;
reg = <0x0 0xa6e00000 0x0 0x40000>;
};
global_sync_mem: global_sync_region@a6f00000 {
no-map;
reg = <0x0 0xa6f00000 0x0 0x100000>;
};
cpusys_vm_mem: cpusys_vm_region@e0600000 {
no-map;
reg = <0x0 0xe0600000 0x0 0x400000>;
};
trust_ui_vm_mem: trust_ui_vm_region@e0b00000 {
no-map;
reg = <0x0 0xe0b00000 0x0 0x4af3000>;
};
trust_ui_vm_qrtr: trust_ui_vm_qrtr@e55f3000 {
no-map;
reg = <0x0 0xe55f3000 0x0 0x9000>;
};
trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring@e55fc000 {
no-map;
reg = <0x0 0xe55fc000 0x0 0x4000>;
gunyah-label = <0x11>;
};
trust_ui_vm_swiotlb: trust_ui_vm_swiotlb@e5600000 {
no-map;
reg = <0x0 0xe5600000 0x0 0x100000>;
gunyah-label = <0x12>;
};
tz_stat_mem: tz_stat_region@e8800000 {
no-map;
reg = <0x0 0xe8800000 0x0 0x100000>;
};
tags_mem: tags_region@e8900000 {
no-map;
reg = <0x0 0xe8900000 0x0 0x680000>;
};
qtee_mem: qtee_region@e8f80000 {
no-map;
reg = <0x0 0xe8f80000 0x0 0x500000>;
};
trusted_apps_mem: trusted_apps_region@e9480000 {
no-map;
reg = <0x0 0xe9480000 0x0 0x1200000>;
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "ravelin-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin RUMI";
compatible = "qcom,ravelin-rumi", "qcom,ravelin", "qcom,rumi";
qcom,msm-id = <568 0x10000>;
qcom,board-id = <0x1000F 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/memreserve/ 0x90000000 0x00010000;
#include "ravelin.dtsi"
#include "ravelin-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin RUMI";
compatible = "qcom,ravelin-rumi", "qcom,ravelin", "qcom,rumi";
qcom,board-id = <0x1000F 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,sm4450-gcc.h>
#include <dt-bindings/gpio/gpio.h>
&soc {
timer {
clock-frequency = <500000>;
};
timer@17420000 {
clock-frequency = <500000>;
};
qcom,wdt@17410000 {
status = "disabled";
};
usb_emuphy: phy@a784000 {
compatible = "qcom,usb-emu-phy";
reg = <0x0a784000 0x9500>;
qcom,emu-init-seq = <0xfffff 0x4
0xffff0 0x4
0x100000 0x20
0x0 0x20
0x000001A0 0x20
0x00100000 0x3c
0x0 0x3c
0x0 0x4>;
};
bi_tcxo: bi_tcxo {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <4>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
bi_tcxo_ao: bi_tcxo_ao {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <4>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
};
&SILVER_CPU_OFF {
status = "nok";
};
&SILVER_CPU_RAIL_OFF {
status = "nok";
};
&GOLD_CPU_OFF {
status = "nok";
};
&GOLD_CPU_RAIL_OFF {
status = "nok";
};
&CLUSTER_OFF {
status = "nok";
};
&CX_RET {
status = "nok";
};
&disp_rsc {
status = "nok";
};
&usb0 {
dwc3@a600000 {
usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
dr_mode = "peripheral";
maximum-speed = "high-speed";
};
};
&qupv3_se7_2uart {
qcom,rumi_platform;
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qrbtc-sdm845";
vdda-phy-supply = <&L5B>;
vdda-pll-supply = <&L16B>;
vdda-phy-max-microamp = <85710>;
vdda-pll-max-microamp = <18330>;
status = "ok";
};
&ufshc_mem {
limit-tx-hs-gear = <1>;
limit-rx-hs-gear = <1>;
limit-rate = <2>; /* HS Rate-B */
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vdd-hba-fixed-regulator;
vcc-supply = <&L24B>;
vcc-max-microamp = <1056000>;
vccq-supply = <&L13B>;
vccq-max-microamp = <750000>;
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <70>;
qcom,disable-lpm;
rpm-level = <0>;
spm-level = <0>;
status = "ok";
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L5E>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L19B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 325000>;
/delete-property/ mmc-ddr-1_8v;
/delete-property/ mmc-hs200-1_8v;
/delete-property/ mmc-hs400-1_8v;
/delete-property/ mmc-hs400-enhanced-strobe;
max-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&sdhc_2 {
status = "ok";
vdd-supply = <&L24B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&L28B>;
qcom,vdd-io-voltage-level = <2960000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
is_rumi;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&gcc {
clocks = <&bi_tcxo>, <&sleep_clk>,
<&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
};
&camcc {
clocks = <&bi_tcxo>,
<&gcc GCC_CAMERA_AHB_CLK>;
};
&dispcc {
clocks = <&bi_tcxo>, <&bi_tcxo_ao>,
<&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
};
&gpucc {
clocks = <&bi_tcxo>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
};
&debugcc {
clocks = <&bi_tcxo>,
<&gcc 0>, <&camcc 0>,
<&dispcc 0>, <&gpucc 0>;
};
&rpmhcc {
compatible = "qcom,dummycc";
clock-output-names = "rpmhcc_clocks";
};
&cpufreq_hw {
clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;
};
&tsens0 {
status = "disabled";
};
&tsens1 {
status = "disabled";
};
&pcie0 {
reg = <0x01c00000 0x3000>,
<0x01c06000 0x2000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>,
<0x01c05000 0x1000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
"rumi";
qcom,target-link-speed = <0x1>;
qcom,link-check-max-count = <200>; /* 1 sec */
qcom,no-l1-supported;
qcom,no-l1ss-supported;
qcom,no-aux-clk-sync;
status = "ok";
};
&pcie0_msi {
status = "ok";
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
/ {
VDD_MODEM_LEVEL:
S1B_LEVEL:
pm6450_s1_level: regulator-pm6450-s1-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s1_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_MX_LEVEL:
S2B_LEVEL:
pm6450_s2_level: regulator-pm6450_s2_level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s2_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_CX_LEVEL:
S5B_LEVEL:
pm6450_s5_level: regulator-pm6450-s5-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s5_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_EBI_LEVEL:
S6B_LEVEL:
pm6450_s6: regulator-pm6450-s6-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s6_level";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
S7B:
pm6450_s7: regulator-pm6450-s7 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s7";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
};
S8B:
pm6450_s8: regulator-pm6450-s8 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s8";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <598000>;
regulator-max-microvolt = <1654000>;
};
S9B:
pm6450_s9: regulator-pm6450-s9 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_s9";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
};
L1B:
pm6450_l1: regulator-pm6450-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l1";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <650000>;
};
VDD_LPI_CX_LEVEL:
L2B_LEVEL:
pm6450_l2_level: regulator-pm6450-l2-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l2_level";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
L3B:
pm6450_l3: regulator-pm6450-l3 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l3";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
};
L5B:
pm6450_l5: regulator-pm6450-l5 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l5";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <830000>;
regulator-max-microvolt = <920000>;
};
L6B:
pm6450_l6: regulator-pm6450-l6 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l6";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
};
L7B:
pm6450_l7: regulator-pm6450-l7 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l7";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <830000>;
regulator-max-microvolt = <920000>;
};
VDD_LPI_MX_LEVEL:
L8B_LEVEL:
pm6450_l8_level: regulator-pm6450-l8-level {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l8_level";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
};
L9B:
pm6450_l9: regulator-pm6450-l9 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l9";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
};
L10B:
pm6450_l10: regulator-pm6450-l10 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l10";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <824000>;
regulator-max-microvolt = <901000>;
};
L11B:
pm6450_l11: regulator-pm6450-l11 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l11";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <348000>;
regulator-max-microvolt = <888000>;
};
L12B:
pm6450_l12: regulator-pm6450-l12 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l12";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1139000>;
regulator-max-microvolt = <1236000>;
};
L13B:
pm6450_l13: regulator-pm6450-l13 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l13";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
};
L14B:
pm6450_l14: regulator-pm6450-l14 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l14";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1170000>;
regulator-max-microvolt = <1304000>;
};
L15B:
pm6450_l15: regulator-pm6450-l15 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l15";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
};
L16B:
pm6450_l16: regulator-pm6450-l16 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l16";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
};
L17B:
pm6450_l17: regulator-pm6450-l17 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l17";
qcom,hpm-min-load = <30000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
L18B:
pm6450_l18: regulator-pm6450-l18 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l18";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
};
L19B:
pm6450_l19: regulator-pm6450-l19 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l19";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
};
L20B:
pm6450_l20: regulator-pm6450-l20 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l20";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
};
L21B:
pm6450_l21: regulator-pm6450-l21 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l21";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
};
L22B:
pm6450_l22: regulator-pm6450-l22 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l22";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1550000>;
regulator-max-microvolt = <2000000>;
};
L23B:
pm6450_l23: regulator-pm6450-l23 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l23";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1950000>;
};
L24B:
pm6450_l24: regulator-pm6450-l24 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l24";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
};
L25B:
pm6450_l25: regulator-pm6450-l25 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l25";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
};
L26B:
pm6450_l26: regulator-pm6450-l26 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l26";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
};
L27B:
pm6450_l27: regulator-pm6450-l27 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l27";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
};
L28B:
pm6450_l28: regulator-pm6450-l28 {
compatible = "qcom,stub-regulator";
regulator-name = "pm6450_l28";
qcom,hpm-min-load = <10000>;
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3300000>;
};
L1M: pm8010m_l1: regulator-pm8010m-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1200000>;
qcom,hpm-min-load = <30000>;
};
L2M: pm8010m_l2: regulator-pm8010m-l2 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l2";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,hpm-min-load = <30000>;
};
L3M: pm8010m_l3: regulator-pm8010m-l3 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l3";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3000000>;
qcom,hpm-min-load = <30000>;
};
L4M: pm8010m_l4: regulator-pm8010m-l4 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l4";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
qcom,hpm-min-load = <30000>;
};
L6M: pm8010m_l6: regulator-pm8010m-l6 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l6";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
qcom,hpm-min-load = <30000>;
};
L7M: pm8010m_l7: regulator-pm8010m-l7 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010m_l7";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3000000>;
qcom,hpm-min-load = <30000>;
};
L1N: pm8010n_l1: regulator-pm8010n-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010n_l1";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,hpm-min-load = <30000>;
};
L3N: pm8010n_l3: regulator-pm8010n-l3 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010n_l3";
regulator-min-microvolt = <1792000>;
regulator-max-microvolt = <1900000>;
qcom,hpm-min-load = <30000>;
};
L4N: pm8010n_l4: regulator-pm8010n-l4 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010n_l4";
regulator-min-microvolt = <1792000>;
regulator-max-microvolt = <1900000>;
qcom,hpm-min-load = <30000>;
};
L6N: pm8010n_l6: regulator-pm8010n-l6 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010n_l6";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
qcom,hpm-min-load = <30000>;
};
L1E: pm8010e_l1: regulator-pm8010e-l1 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010e_l1";
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
qcom,hpm-min-load = <30000>;
};
L4E: pm8010e_l4: regulator-pm8010e-l4 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010e_l4";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3312000>;
qcom,hpm-min-load = <30000>;
};
L5E: pm8010e_l5: regulator-pm8010e-l5 {
compatible = "qcom,stub-regulator";
regulator-name = "pm8010e_l5";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3544000>;
qcom,hpm-min-load = <30000>;
};
};

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qcom/ravelin-thermal-modem.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/thermal/thermal_qti.h>
&soc {
qmi-tmd-devices {
compatible = "qcom,qmi-cooling-devices";
modem {
qcom,instance-id = <QMI_MODEM_INST_ID>;
modem_lte_dsc: modem_lte_dsc {
qcom,qmi-dev-name = "modem_lte_dsc";
#cooling-cells = <2>;
};
modem_lte_sub1_dsc: modem_lte_sub1_dsc {
qcom,qmi-dev-name = "modem_lte_sub1_dsc";
#cooling-cells = <2>;
};
modem_nr_dsc: modem_nr_dsc {
qcom,qmi-dev-name = "modem_nr_dsc";
#cooling-cells = <2>;
};
modem_nr_sub1_dsc: modem_nr_sub1_dsc {
qcom,qmi-dev-name = "modem_nr_sub1_dsc";
#cooling-cells = <2>;
};
modem_nr_scg_dsc: modem_nr_scg_dsc {
qcom,qmi-dev-name = "modem_nr_scg_dsc";
#cooling-cells = <2>;
};
modem_nr_scg_sub1_dsc: modem_nr_scg_sub1_dsc {
qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc";
#cooling-cells = <2>;
};
sdr0_lte_dsc: sdr0_lte_dsc {
qcom,qmi-dev-name = "sdr0_lte_dsc";
#cooling-cells = <2>;
};
sdr1_lte_dsc: sdr1_lte_dsc {
qcom,qmi-dev-name = "sdr1_lte_dsc";
#cooling-cells = <2>;
};
sdr0_nr_dsc: sdr0_nr_dsc {
qcom,qmi-dev-name = "sdr0_nr_dsc";
#cooling-cells = <2>;
};
sdr1_nr_dsc: sdr1_nr_dsc {
qcom,qmi-dev-name = "sdr1_nr_dsc";
#cooling-cells = <2>;
};
pa_lte_sdr0_dsc: pa_lte_sdr0_dsc {
qcom,qmi-dev-name = "pa_lte_sdr0_dsc";
#cooling-cells = <2>;
};
pa_lte_sdr1_dsc: pa_lte_sdr1_dsc {
qcom,qmi-dev-name = "pa_lte_sdr1_dsc";
#cooling-cells = <2>;
};
pa_lte_sdr0_sub1_dsc: pa_lte_sdr0_sub1_dsc {
qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc";
#cooling-cells = <2>;
};
pa_lte_sdr1_sub1_dsc: pa_lte_sdr1_sub1_dsc {
qcom,qmi-dev-name = "pa_lte_sdr1_sub1_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr0_dsc: pa_nr_sdr0_dsc {
qcom,qmi-dev-name = "pa_nr_sdr0_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr1_dsc: pa_nr_sdr1_dsc {
qcom,qmi-dev-name = "pa_nr_sdr1_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr0_sub1_dsc: pa_nr_sdr0_sub1_dsc {
qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr1_sub1_dsc: pa_nr_sdr1_sub1_dsc {
qcom,qmi-dev-name = "pa_nr_sdr1_sub1_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr0_scg_dsc: pa_nr_sdr0_scg {
qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc";
#cooling-cells = <2>;
};
pa_nr_sdr1_scg_dsc: pa_nr_sdr1_scg {
qcom,qmi-dev-name = "pa_nr_sdr1_scg_dsc";
#cooling-cells = <2>;
};
qmi_wlan: wlan {
qcom,qmi-dev-name = "wlan";
#cooling-cells = <2>;
};
modem_vdd: modem_vdd {
qcom,qmi-dev-name = "cpuv_restriction_cold";
#cooling-cells = <2>;
};
};
};
qmi_sensor: qmi-ts-sensors {
compatible = "qcom,qmi-sensors";
#thermal-sensor-cells = <1>;
modem {
qcom,instance-id = <QMI_MODEM_INST_ID>;
qcom,qmi-sensor-names = "pa",
"pa_1",
"modem_bcl_warn",
"modem_cfg",
"lte_cc",
"mcg_fr1_cc",
"scg_fr1_cc",
"sub1_modem_cfg",
"sub1_lte_cc",
"sub1_mcg_fr1_cc",
"sub1_scg_fr1_cc",
"sdr0_pa0",
"sdr1_pa0",
"sdr0",
"sdr1";
};
};
};
&thermal_zones {
pa {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_PA)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
pa1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_PA_1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
bcl-warn {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_BCL_WARN)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
modem-cfg {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM2)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
lte-cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM3)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mcg-fr1-cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM4)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
scg-fr1-cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_EPM6)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1-modem-cfg {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_MODEM_CFG)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1-lte-cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_LTE_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1_mcg_fr1_cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_MCG_FR1_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sub1_scg_fr1_cc {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SUB1_SCG_FR1_CC)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0-pa {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0_PA)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1-pa {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1_PA)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

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qcom/ravelin-thermal-overlay.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/thermal/thermal_qti.h>
&thermal_zones {
pm6450_tz {
cooling-maps {
pm6450_lte {
trip = <&pm6450_trip0>;
cooling-device = <&modem_lte_dsc 255 255>;
};
pm6450_nr {
trip = <&pm6450_trip0>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
pm6450_cpu0 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu0_pause 1 1>;
};
pm6450_cpu1 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu1_pause 1 1>;
};
pm6450_cpu2 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu2_pause 1 1>;
};
pm6450_cpu3 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu3_pause 1 1>;
};
pm6450_cpu4 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu4_pause 1 1>;
};
pm6450_cpu5 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu5_pause 1 1>;
};
pm6450_cpu6_7 {
trip = <&pm6450_trip0>;
cooling-device = <&cpu_6_7_pause 1 1>;
};
pm6450_gpu {
trip = <&pm6450_trip0>;
cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
};
};
};
};

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