From 48372b8df63402d46381fc6b2c81d64d01a6a600 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Thu, 25 Apr 2024 14:32:37 +0800 Subject: [PATCH 01/59] ARM: dts: qcom: enable fan controller for SunP HDK Enable Fan Controller driver for SunP HDK. Change-Id: I635c98d89862ca5a7cb9c90fd5c8a4f0c663ea1d Signed-off-by: Minghao Zhang --- qcom/sunp-hdk.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/qcom/sunp-hdk.dtsi b/qcom/sunp-hdk.dtsi index f1fc1b16..b06d28f4 100644 --- a/qcom/sunp-hdk.dtsi +++ b/qcom/sunp-hdk.dtsi @@ -57,3 +57,36 @@ &tlmm 51 0 &tlmm 161 0 &tlmm 162 0x2008>; }; }; + +&tlmm { + fan_enable_pin { + mux { + pins = "gpio182"; + function = "gpio"; + }; + + config { + pins = "gpio182"; + bias-pull-up; + drive-strength = <16>; + }; + }; +}; + +&qupv3_se3_i2c { + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + + fancontroller: max31760@50 { + compatible = "maxim,max31760"; + reg = <0x50>; + #cooling-cells = <2>; + maxim,fan-num = <1>; + maxim,vdd-supply = <&BOB1>; + maxim,vcca-supply = <&L15B>; + regulator-name = "maxim,vdd", "maxim,vcca"; + maxim,pwr-en-gpio = <&tlmm 182 GPIO_ACTIVE_LOW>; + status = "ok"; + }; +}; From 4a42f43d353502a48fe66d2a400325b968de661d Mon Sep 17 00:00:00 2001 From: songrui Date: Fri, 26 Apr 2024 11:23:55 +0800 Subject: [PATCH 02/59] ARM: dts: qcom: add UIDs for QTEE service in sun OEMVM "CDF" is SecureImage in QTEE and it is for QTVM TA authentication. Signed-off-by: songrui --- qcom/sun-oemvm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun-oemvm.dtsi b/qcom/sun-oemvm.dtsi index f4efebdd..ee013fe1 100644 --- a/qcom/sun-oemvm.dtsi +++ b/qcom/sun-oemvm.dtsi @@ -69,7 +69,7 @@ vendor = "QTI"; image-name = "qcom,oemvm"; qcom,pasid = <0x0 0x22>; - qcom,qtee-config-info = "p=9,39,7C,8F,97,159,7F1;"; + qcom,qtee-config-info = "p=9,39,7C,8F,97,159,7F1,CDF;"; qcom,secdomain-ids = <49>; qcom,primary-vm-index = <0>; vm-uri = "vmuid/oemvm"; From 1a3f9c0ed56b077854792a8285eee0415a9bc77f Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Thu, 2 May 2024 19:33:02 +0530 Subject: [PATCH 03/59] ARM: dts: msm: Add ufs shutdown power supply for sun Add ufs proxy power supply to add an additional vote for VCCQ LDO. In case of ufs shutdown, UFS VCCQ LDO would be turned off by PMIC regulator itself. Change-Id: If55c56bcbe6a3b76dbe5703095bd5d98abdca8a6 Signed-off-by: Nitin Rawat --- qcom/sun-cdp.dtsi | 3 +++ qcom/sun-mtp.dtsi | 3 +++ qcom/sun-qrd.dtsi | 3 +++ 3 files changed, 9 insertions(+) diff --git a/qcom/sun-cdp.dtsi b/qcom/sun-cdp.dtsi index 3e00c2c8..4ded8949 100644 --- a/qcom/sun-cdp.dtsi +++ b/qcom/sun-cdp.dtsi @@ -177,6 +177,9 @@ qcom,vccq-parent-supply = <&pm_v8i_s7>; qcom,vccq-parent-max-microamp = <210000>; + qcom,vccq-proxy-vote-supply = <&pm_v8d_l1>; + qcom,vccq-proxy-vote-max-microamp = <1200000>; + reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; diff --git a/qcom/sun-mtp.dtsi b/qcom/sun-mtp.dtsi index bdea7207..2d503e83 100644 --- a/qcom/sun-mtp.dtsi +++ b/qcom/sun-mtp.dtsi @@ -238,6 +238,9 @@ vccq-supply = <&pm_v8d_l1>; vccq-max-microamp = <1200000>; + qcom,vccq-proxy-vote-supply = <&pm_v8d_l1>; + qcom,vccq-proxy-vote-max-microamp = <1200000>; + /* UFS Rst pin is always on. It is shared with VDD_PX14 */ qcom,vddp-ref-clk-supply = <&pm_v8i_l2>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/sun-qrd.dtsi b/qcom/sun-qrd.dtsi index 31d7dc91..94791b81 100644 --- a/qcom/sun-qrd.dtsi +++ b/qcom/sun-qrd.dtsi @@ -182,6 +182,9 @@ qcom,vccq-parent-supply = <&pm_v8i_s7>; qcom,vccq-parent-max-microamp = <210000>; + qcom,vccq-proxy-vote-supply = <&pm_v8d_l1>; + qcom,vccq-proxy-vote-max-microamp = <1200000>; + reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; From 01f747212c0710f9ce4d78b2d228d06010be4102 Mon Sep 17 00:00:00 2001 From: Amir Vajid Date: Thu, 9 May 2024 16:03:37 -0700 Subject: [PATCH 04/59] ARM: dts: qcom: add low power cpu to gold bwmon for sun Configure low power cpu on gold bwmon for sun. Change-Id: I323797604e76a5e872171ba359ee43cc155235c6 Signed-off-by: Amir Vajid --- qcom/sun.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 6e2bc13c..3c7a90f2 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3408,6 +3408,7 @@ qcom,count-unit = <0x10000>; qcom,target-dev = <&qcom_llcc_dcvs_hw>; qcom,second-vote = <&qcom_llcc_ddr_vote>; + qcom,low-power-cpu = <0>; }; bwmon_llcc_prime: qcom,bwmon-llcc-prime@240B7300 { From 38373dad544e105ee0a616f620c46f7836bfa4e1 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Mon, 13 May 2024 15:43:57 -0700 Subject: [PATCH 05/59] ARM: dts: msm: Update to memory map v5 for sun Update to the latest memory map v5. Change-Id: I16318dc43d3701a1678acbd2b616fddebc8e209e Signed-off-by: Patrick Daly --- qcom/sun.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 6172d633..3bf2cc9c 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3643,9 +3643,9 @@ reg = <0x0 0x89300000 0x0 0xa80000>; }; - mpss_mem: mpss_region@89e00000 { + mpss_mem: mpss_region@8ba00000 { no-map; - reg = <0x0 0x89e00000 0x0 0x11200000>; + reg = <0x0 0x8ba00000 0x0 0xf600000>; }; q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 { @@ -3712,27 +3712,27 @@ cdsp_mem: cdsp_region@9d200000 { no-map; - reg = <0x0 0x9d200000 0x0 0x2000000>; + reg = <0x0 0x9d200000 0x0 0x1900000>; }; - q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9f200000 { + q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9eb00000 { no-map; - reg = <0x0 0x9f200000 0x0 0x80000>; + reg = <0x0 0x9eb00000 0x0 0x80000>; }; - q6_adsp_dtb_mem: q6_adsp_dtb_region@9f280000 { + soccp_mem: soccp_region@9ec00000 { no-map; - reg = <0x0 0x9f280000 0x0 0x80000>; + reg = <0x0 0x9ec00000 0x0 0x180000>; }; - adspslpi_mem: adspslpi_region@9f300000 { + q6_adsp_dtb_mem: q6_adsp_dtb_region@9ed80000 { no-map; - reg = <0x0 0x9f300000 0x0 0x4080000>; + reg = <0x0 0x9ed80000 0x0 0x80000>; }; - soccp_mem: soccp_region@a3380000 { + adspslpi_mem: adspslpi_region@9ee00000 { no-map; - reg = <0x0 0xa3380000 0x0 0x180000>; + reg = <0x0 0x9ee00000 0x0 0x3a80000>; }; /* uefi region can be reused by apps */ From 1f72b5a0809691f8447916b1803b8ab8b7f1de05 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Mon, 8 Apr 2024 16:07:28 +0530 Subject: [PATCH 06/59] ARM: dts: msm: Add USB device nodes for tuna Enable USB related properties for USB functionality on tuna. Change-Id: Ia4270aa4860d8b894ab094dafbad61d278f7606f Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-rumi.dtsi | 28 ++++++++++++++++++++++ qcom/tuna-usb.dtsi | 57 +++++++++++++++++++++++++++++++++++++++++++++ qcom/tuna.dtsi | 1 + 3 files changed, 86 insertions(+) create mode 100644 qcom/tuna-usb.dtsi diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi index 9a0f3db9..9a5d1f6e 100644 --- a/qcom/tuna-rumi.dtsi +++ b/qcom/tuna-rumi.dtsi @@ -10,3 +10,31 @@ &memtimer { clock-frequency = <500000>; }; + +&soc { + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb_emuphy: phy@a784000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a784000 0x9500>; + + qcom,emu-init-seq = <0xfffff 0x4 + 0xffff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x000101F0 0x20 + 0x00100000 0x3c + 0x0 0x3c + 0x0 0x4>; + }; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emuphy>, <&usb_nop_phy>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + }; +}; diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi new file mode 100644 index 00000000..0d4c7684 --- /dev/null +++ b/qcom/tuna-usb.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + interrupts-extended = <&intc GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,core-clk-rate-disconnected = <133333333>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd93c>; + + interrupts = ; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,ssp-u3-u0-quirk; + tx-fifo-resize; + dr_mode = "otg"; + maximum-speed = "super-speed-plus"; + usb-role-switch; + }; + }; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 0cc30f4e..8b73f368 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -530,3 +530,4 @@ }; #include "tuna-pinctrl.dtsi" +#include "tuna-usb.dtsi" From 1fa61cd64607873b13df5cd1f6851ebbdd0b72bd Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Mon, 20 May 2024 15:08:56 +0530 Subject: [PATCH 07/59] bindings: interrupt-controller: Document PDC compatible for tuna Document PDC compatible for tuna. Change-Id: Icc2dab9784fdf7fb2dfcd38125be291216dbbdf1 Signed-off-by: Maulik Shah --- bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/interrupt-controller/qcom,pdc.yaml b/bindings/interrupt-controller/qcom,pdc.yaml index 7ca44441..35da8d13 100644 --- a/bindings/interrupt-controller/qcom,pdc.yaml +++ b/bindings/interrupt-controller/qcom,pdc.yaml @@ -36,6 +36,7 @@ properties: - qcom,sun-pdc - qcom,parrot-pdc - qcom,ravelin-pdc + - qcom,tuna-pdc - const: qcom,pdc reg: From 7b861d9e0f38bce0eed93b06596c71f1f467dee3 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Mon, 20 May 2024 11:59:38 +0530 Subject: [PATCH 08/59] ARM: dts: msm: Add support for debug info for parrot Reserve debug info region of 4KB for parrot. Change-Id: I59af5a2ebe09865c6134c38369f593cf9abf7517 Signed-off-by: Saranya R --- qcom/parrot.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 2c9b4bd1..a7265ad8 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -417,6 +417,12 @@ size = <0x0 0x2800000>; }; + kinfo_mem: debug_kinfo_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x1000>; + no-map; + }; + va_md_mem: va_md_mem_region { compatible = "shared-dma-pool"; alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; @@ -2727,6 +2733,11 @@ compatible = "qcom,logbuf-vendor-hooks"; }; + google,debug-kinfo { + compatible = "google,debug-kinfo"; + memory-region = <&kinfo_mem>; + }; + mini_dump_node { compatible = "qcom,minidump"; status = "ok"; From 43a2e6c759ae1891ff6ad1fcf1f7bbd9b8d1b6e4 Mon Sep 17 00:00:00 2001 From: Shilpa Suresh Date: Mon, 29 Apr 2024 15:15:56 +0530 Subject: [PATCH 09/59] ARM: dts: msm: Enable PM8010, flash, PON, PWM & other nodes for parrot Add compatible strings to PON, PWM-LPG, TRI-LED, VIBRATOR, FLASH-V2, PM8008/PM8010 regulator and AMOLED regulator DT nodes. These were removed from the bulk DT porting for Parrot on qcom-6.6 device-tree branch. While at it, remove the REVID Device node reference and the WLED and LCDB device nodes as they are not required for Parrot. These were initially added as a part of the bulk DT porting done for Parrot on qcom-6.6. Change-Id: I59666d86f449fd74366b1862bb23d8762b8abdad Signed-off-by: Shilpa Suresh --- qcom/parrot-pmic-overlay.dtsi | 16 ++------ qcom/pm6150l.dtsi | 72 +++-------------------------------- qcom/pm6450.dtsi | 1 + qcom/pm7250b.dtsi | 2 + qcom/pm8350b.dtsi | 1 + qcom/pmk8350.dtsi | 13 +++++++ 6 files changed, 27 insertions(+), 78 deletions(-) diff --git a/qcom/parrot-pmic-overlay.dtsi b/qcom/parrot-pmic-overlay.dtsi index 3a2c1a20..59248e27 100644 --- a/qcom/parrot-pmic-overlay.dtsi +++ b/qcom/parrot-pmic-overlay.dtsi @@ -169,10 +169,6 @@ }; }; -&pm6150l_revid { - status = "disabled"; -}; - &pm6150l_4 { qcom,power-on@800 { status = "disabled"; @@ -422,16 +418,13 @@ pinctrl-0 = <&pm8010i_active>; pm8010-chip@900 { + compatible = "qcom,pm8008-chip"; reg = <0x900>; PM8010I_EN: qcom,pm8008-chip-en { regulator-name = "pm8010i-chip-en"; }; }; - - qcom,revid@100 { - reg = <0x100>; - }; }; pm8010i@9 { @@ -441,6 +434,7 @@ #size-cells = <0>; qcom,pm8010i-regulator { + compatible = "qcom,pm8010-regulator"; #address-cells = <1>; #size-cells = <0>; @@ -517,16 +511,13 @@ pinctrl-0 = <&pm8010j_active>; pm8010-chip@900 { + compatible = "qcom,pm8008-chip"; reg = <0x900>; PM8010J_EN: qcom,pm8008-chip-en { regulator-name = "pm8010j-chip-en"; }; }; - - qcom,revid@100 { - reg = <0x100>; - }; }; pm8010j@d { @@ -536,6 +527,7 @@ #size-cells = <0>; qcom,pm8010j-regulator { + compatible = "qcom,pm8010-regulator"; #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/pm6150l.dtsi b/qcom/pm6150l.dtsi index 5f476b01..eeca9757 100644 --- a/qcom/pm6150l.dtsi +++ b/qcom/pm6150l.dtsi @@ -20,11 +20,8 @@ #address-cells = <1>; #size-cells = <0>; - pm6150l_revid: qcom,revid@100 { - reg = <0x100>; - }; - qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; reg = <0x800>; }; @@ -124,45 +121,15 @@ pm6150l_pwm_1: qcom,pwms@bc00 { status = "disabled"; + compatible = "qcom,pwm-lpg"; reg = <0xbc00>; reg-names = "lpg-base"; qcom,num-lpg-channels = <1>; #pwm-cells = <2>; }; - pm6150l_lcdb: qcom,lcdb@ec00 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0xec00>; - interrupts = <0x5 0xec 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "sc-irq"; - qcom,pmic-revid = <&pm6150l_revid>; - qcom,voltage-step-ramp; - status = "disabled"; - - lcdb_ldo_vreg: ldo { - label = "ldo"; - regulator-name = "lcdb_ldo"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - }; - - lcdb_ncp_vreg: ncp { - label = "ncp"; - regulator-name = "lcdb_ncp"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - }; - - lcdb_bst_vreg: bst { - label = "bst"; - regulator-name = "lcdb_bst"; - regulator-min-microvolt = <4700000>; - regulator-max-microvolt = <6275000>; - }; - }; - flash_led: qcom,leds@d300 { + compatible = "qcom,pm6150l-flash-led-v2"; status = "disabled"; reg = <0xd300>; label = "flash"; @@ -179,7 +146,6 @@ qcom,thermal-derate-en; qcom,thermal-derate-current = <200 500 1000>; qcom,isc-delay = <192>; - qcom,pmic-revid = <&pm6150l_revid>; pm6150l_flash0: qcom,flash_0 { label = "flash"; @@ -280,36 +246,8 @@ }; }; - pm6150l_wled: qcom,wled@d800 { - reg = <0xd800>, <0xd900>; - reg-names = "wled-ctrl-base", "wled-sink-base"; - label = "backlight"; - interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, - <0x5 0xd8 0x4 IRQ_TYPE_EDGE_BOTH>, - <0x5 0xd8 0x5 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "ovp-irq", "pre-flash-irq", - "flash-irq"; - qcom,auto-calibration; - status = "disabled"; - - wled_flash: qcom,wled-flash { - label = "flash"; - qcom,default-led-trigger = "wled_flash"; - }; - - wled_torch: qcom,wled-torch { - label = "torch"; - qcom,default-led-trigger = "wled_torch"; - qcom,wled-torch-timer = <1200>; - }; - - wled_switch: qcom,wled-switch { - label = "switch"; - qcom,default-led-trigger = "wled_switch"; - }; - }; - pm6150l_lpg: qcom,pwms@b100 { + compatible = "qcom,pwm-lpg"; reg = <0xb100>, <0xb000>; reg-names = "lpg-base", "lut-base"; #pwm-cells = <2>; @@ -351,6 +289,7 @@ }; pm6150l_rgb_led: qcom,leds@d000 { + compatible = "qcom,tri-led"; reg = <0xd000>; red { label = "red"; @@ -375,6 +314,7 @@ }; pm6150a_amoled: qcom,amoled { + compatible = "qcom,amoled-regulator"; status = "disabled"; oledb_vreg: oledb@e000 { diff --git a/qcom/pm6450.dtsi b/qcom/pm6450.dtsi index 3c08ec15..936d2c03 100644 --- a/qcom/pm6450.dtsi +++ b/qcom/pm6450.dtsi @@ -36,6 +36,7 @@ pm6450_pwm_1: qcom,pwms@e800 { status = "disabled"; + compatible = "qcom,pwm-lpg"; reg = <0xe800>; reg-names = "lpg-base"; qcom,num-lpg-channels = <1>; diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index 4559bd12..d5f00e24 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -21,6 +21,7 @@ #size-cells = <0>; qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; reg = <0x800>; }; @@ -199,6 +200,7 @@ #size-cells = <0>; pm7250b_vib: qcom,vibrator@5300 { + compatible = "qcom,qpnp-vibrator-ldo"; reg = <0x5300>; qcom,vib-ldo-volt-uv = <3000000>; qcom,disable-overdrive; diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi index 06c66741..df01c429 100644 --- a/qcom/pm8350b.dtsi +++ b/qcom/pm8350b.dtsi @@ -180,6 +180,7 @@ }; pm8350b_amoled: qcom,amoled { + compatible = "qcom,amoled-regulator"; #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/pmk8350.dtsi b/qcom/pmk8350.dtsi index 2c947449..a7d14676 100644 --- a/qcom/pmk8350.dtsi +++ b/qcom/pmk8350.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -25,16 +26,28 @@ #size-cells = <0>; pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; reg = <0x800>; qcom,system-reset; qcom,store-hard-reset-reason; }; pmk8350_pon: pon_hlos@1300 { + compatible = "qcom,qpnp-power-on"; reg = <0x1300>; interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>, <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "kpdpwr", "resin"; + + qcom,pon_1 { + qcom,pon-type = ; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + linux,code = ; + }; }; pmk8350_vadc: vadc@3100 { From ffeb9a13a682eab983a5220cb06070217004b66c Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Fri, 17 May 2024 20:19:30 +0530 Subject: [PATCH 10/59] ARM: dts: msm:Uncomment compatible string for rpm-smd-regulator Uncomment compatible string qcom,rpm-smd-regulator,qcom, rpm-smd-regulator-resource and qcom,regulator-cooling-device from monaco-regulators.dtsi and pm5100-rpm-regulator.dtsi. Change-Id: Ie73e721dc9636b2bd2ca73bce9daaa05b53b7afe Signed-off-by: Ayyagari Ushasreevalli --- qcom/monaco-regulators.dtsi | 16 ++-- qcom/pm5100-rpm-regulator.dtsi | 146 ++++++++++++++++----------------- 2 files changed, 81 insertions(+), 81 deletions(-) diff --git a/qcom/monaco-regulators.dtsi b/qcom/monaco-regulators.dtsi index 344e82fd..614f9cf2 100644 --- a/qcom/monaco-regulators.dtsi +++ b/qcom/monaco-regulators.dtsi @@ -15,7 +15,7 @@ proxy-supply = <&VDD_CX_LEVEL>; VDD_CX_LEVEL: S1A_LEVEL: pm5100_s1_level: regulator-s1-level { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_s1_level"; qcom,set = <3>; regulator-min-microvolt = @@ -34,7 +34,7 @@ VDD_CX_FLOOR_LEVEL: S1A_FLOOR_LEVEL: pm5100_s1_floor_level: regulator-s1-floor-level { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_s1_floor_level"; qcom,set = <3>; regulator-min-microvolt = @@ -47,7 +47,7 @@ VDD_CX_LEVEL_AO: S1A_LEVEL_AO: pm5100_s1_level_ao: regulator-s1-level-ao { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_s1_level_ao"; qcom,set = <1>; regulator-min-microvolt = @@ -103,7 +103,7 @@ qcom,resource-id = <0>; VDD_LPI_CX_LEVEL: L4A_LEVEL: pm5100_l4_level: regulator-l4-level { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l4_level"; qcom,set = <3>; regulator-min-microvolt = @@ -121,7 +121,7 @@ qcom,resource-id = <0>; VDD_LPI_MX_LEVEL: L5A_LEVEL: pm5100_l5_level: regulator-l5-level { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l5_level"; qcom,set = <3>; regulator-min-microvolt = @@ -163,7 +163,7 @@ VDD_EBI_LEVEL: L3A_LEVEL: pm5100_l3_level: regulator-pm5100-l3-level { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l3_level"; qcom,set = <3>; regulator-min-microvolt = @@ -182,7 +182,7 @@ VDD_EBI_LEVEL_AO: L3A_LEVEL_AO: pm5100_l3_level_ao: regulator-pm5100-l3-level-ao { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l3_level_ao"; qcom,set = <1>; regulator-min-microvolt = @@ -193,7 +193,7 @@ }; mx_cdev: mx-cdev-lvl { - /* compatible = "qcom,regulator-cooling-device"; */ + compatible = "qcom,regulator-cooling-device"; regulator-cdev-supply = <&VDD_MXA_LEVEL>; regulator-levels = ; diff --git a/qcom/pm5100-rpm-regulator.dtsi b/qcom/pm5100-rpm-regulator.dtsi index 7ff6ec7f..74bcffcc 100644 --- a/qcom/pm5100-rpm-regulator.dtsi +++ b/qcom/pm5100-rpm-regulator.dtsi @@ -5,7 +5,7 @@ &rpm_bus { rpm-regulator-smpa1 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "smpa"; qcom,resource-id = <1>; qcom,regulator-type = <1>; @@ -13,7 +13,7 @@ status = "disabled"; regulator-s1 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_s1"; qcom,set = <3>; status = "disabled"; @@ -21,7 +21,7 @@ }; rpm-regulator-smpa2 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "smpa"; qcom,resource-id = <2>; qcom,regulator-type = <1>; @@ -29,7 +29,7 @@ status = "disabled"; regulator-s2 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_s2"; qcom,set = <3>; status = "disabled"; @@ -37,7 +37,7 @@ }; rpm-regulator-smpa3 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "smpa"; qcom,resource-id = <3>; qcom,regulator-type = <1>; @@ -45,7 +45,7 @@ status = "disabled"; regulator-s3 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_s3"; qcom,set = <3>; status = "disabled"; @@ -53,7 +53,7 @@ }; rpm-regulator-smpa4 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "smpa"; qcom,resource-id = <4>; qcom,regulator-type = <1>; @@ -61,7 +61,7 @@ status = "disabled"; regulator-s4 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_s4"; qcom,set = <3>; status = "disabled"; @@ -69,7 +69,7 @@ }; rpm-regulator-smpa5 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "smpa"; qcom,resource-id = <5>; qcom,regulator-type = <1>; @@ -77,7 +77,7 @@ status = "disabled"; regulator-s5 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_s5"; qcom,set = <3>; status = "disabled"; @@ -85,7 +85,7 @@ }; rpm-regulator-ldoa1 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <1>; qcom,regulator-type = <0>; @@ -94,7 +94,7 @@ status = "disabled"; regulator-l1 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l1"; qcom,set = <3>; status = "disabled"; @@ -102,7 +102,7 @@ }; rpm-regulator-ldoa2 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <2>; qcom,regulator-type = <0>; @@ -111,7 +111,7 @@ status = "disabled"; regulator-l2 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l2"; qcom,set = <3>; status = "disabled"; @@ -119,7 +119,7 @@ }; rpm-regulator-ldoa3 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <3>; qcom,regulator-type = <0>; @@ -128,7 +128,7 @@ status = "disabled"; regulator-l3 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l3"; qcom,set = <3>; status = "disabled"; @@ -136,7 +136,7 @@ }; rpm-regulator-ldoa4 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <4>; qcom,regulator-type = <0>; @@ -145,7 +145,7 @@ status = "disabled"; regulator-l4 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l4"; qcom,set = <3>; status = "disabled"; @@ -153,7 +153,7 @@ }; rpm-regulator-ldoa5 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <5>; qcom,regulator-type = <0>; @@ -162,7 +162,7 @@ status = "disabled"; regulator-l5 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l5"; qcom,set = <3>; status = "disabled"; @@ -170,7 +170,7 @@ }; rpm-regulator-ldoa6 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <6>; qcom,regulator-type = <0>; @@ -179,7 +179,7 @@ status = "disabled"; regulator-l6 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l6"; qcom,set = <3>; status = "disabled"; @@ -187,7 +187,7 @@ }; rpm-regulator-ldoa7 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <7>; qcom,regulator-type = <0>; @@ -196,7 +196,7 @@ status = "disabled"; regulator-l7 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l7"; qcom,set = <3>; status = "disabled"; @@ -204,7 +204,7 @@ }; rpm-regulator-ldoa8 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <8>; qcom,regulator-type = <0>; @@ -213,7 +213,7 @@ status = "disabled"; regulator-l8 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l8"; qcom,set = <3>; status = "disabled"; @@ -221,7 +221,7 @@ }; rpm-regulator-ldoa9 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <9>; qcom,regulator-type = <0>; @@ -230,7 +230,7 @@ status = "disabled"; regulator-l9 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l9"; qcom,set = <3>; status = "disabled"; @@ -238,7 +238,7 @@ }; rpm-regulator-ldoa10 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <10>; qcom,regulator-type = <0>; @@ -247,7 +247,7 @@ status = "disabled"; regulator-l10 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l10"; qcom,set = <3>; status = "disabled"; @@ -255,7 +255,7 @@ }; rpm-regulator-ldoa11 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <11>; qcom,regulator-type = <0>; @@ -264,7 +264,7 @@ status = "disabled"; regulator-l11 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l11"; qcom,set = <3>; status = "disabled"; @@ -272,7 +272,7 @@ }; rpm-regulator-ldoa12 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <12>; qcom,regulator-type = <0>; @@ -281,7 +281,7 @@ status = "disabled"; regulator-l12 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l12"; qcom,set = <3>; status = "disabled"; @@ -289,7 +289,7 @@ }; rpm-regulator-ldoa13 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <13>; qcom,regulator-type = <0>; @@ -298,7 +298,7 @@ status = "disabled"; regulator-l13 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l13"; qcom,set = <3>; status = "disabled"; @@ -306,7 +306,7 @@ }; rpm-regulator-ldoa14 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <14>; qcom,regulator-type = <0>; @@ -315,7 +315,7 @@ status = "disabled"; regulator-l14 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l14"; qcom,set = <3>; status = "disabled"; @@ -323,7 +323,7 @@ }; rpm-regulator-ldoa15 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <15>; qcom,regulator-type = <0>; @@ -332,7 +332,7 @@ status = "disabled"; regulator-l15 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l15"; qcom,set = <3>; status = "disabled"; @@ -340,7 +340,7 @@ }; rpm-regulator-ldoa16 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <16>; qcom,regulator-type = <0>; @@ -349,7 +349,7 @@ status = "disabled"; regulator-l16 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l16"; qcom,set = <3>; status = "disabled"; @@ -357,7 +357,7 @@ }; rpm-regulator-ldoa17 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <17>; qcom,regulator-type = <0>; @@ -366,7 +366,7 @@ status = "disabled"; regulator-l17 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l17"; qcom,set = <3>; status = "disabled"; @@ -374,7 +374,7 @@ }; rpm-regulator-ldoa18 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <18>; qcom,regulator-type = <0>; @@ -383,7 +383,7 @@ status = "disabled"; regulator-l18 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l18"; qcom,set = <3>; status = "disabled"; @@ -391,7 +391,7 @@ }; rpm-regulator-ldoa19 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <19>; qcom,regulator-type = <0>; @@ -400,7 +400,7 @@ status = "disabled"; regulator-l19 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l19"; qcom,set = <3>; status = "disabled"; @@ -408,7 +408,7 @@ }; rpm-regulator-ldoa20 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <20>; qcom,regulator-type = <0>; @@ -417,7 +417,7 @@ status = "disabled"; regulator-l20 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l20"; qcom,set = <3>; status = "disabled"; @@ -425,7 +425,7 @@ }; rpm-regulator-ldoa21 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <21>; qcom,regulator-type = <0>; @@ -434,7 +434,7 @@ status = "disabled"; regulator-l21 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l21"; qcom,set = <3>; status = "disabled"; @@ -442,7 +442,7 @@ }; rpm-regulator-ldoa22 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <22>; qcom,regulator-type = <0>; @@ -451,7 +451,7 @@ status = "disabled"; regulator-l22 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l22"; qcom,set = <3>; status = "disabled"; @@ -459,7 +459,7 @@ }; rpm-regulator-ldoa23 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <23>; qcom,regulator-type = <0>; @@ -468,7 +468,7 @@ status = "disabled"; regulator-l23 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l23"; qcom,set = <3>; status = "disabled"; @@ -476,7 +476,7 @@ }; rpm-regulator-ldoa24 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <24>; qcom,regulator-type = <0>; @@ -485,7 +485,7 @@ status = "disabled"; regulator-l24 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l24"; qcom,set = <3>; status = "disabled"; @@ -493,7 +493,7 @@ }; rpm-regulator-ldoa25 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <25>; qcom,regulator-type = <0>; @@ -502,7 +502,7 @@ status = "disabled"; regulator-l25 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l25"; qcom,set = <3>; status = "disabled"; @@ -510,7 +510,7 @@ }; rpm-regulator-ldoa26 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <26>; qcom,regulator-type = <0>; @@ -519,7 +519,7 @@ status = "disabled"; regulator-l26 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l26"; qcom,set = <3>; status = "disabled"; @@ -527,7 +527,7 @@ }; rpm-regulator-ldoa27 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <27>; qcom,regulator-type = <0>; @@ -536,7 +536,7 @@ status = "disabled"; regulator-l27 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l27"; qcom,set = <3>; status = "disabled"; @@ -544,7 +544,7 @@ }; rpm-regulator-ldoa28 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <28>; qcom,regulator-type = <0>; @@ -553,7 +553,7 @@ status = "disabled"; regulator-l28 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l28"; qcom,set = <3>; status = "disabled"; @@ -561,7 +561,7 @@ }; rpm-regulator-ldoa29 { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "ldoa"; qcom,resource-id = <29>; qcom,regulator-type = <0>; @@ -570,7 +570,7 @@ status = "disabled"; regulator-l29 { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_l29"; qcom,set = <3>; status = "disabled"; @@ -578,7 +578,7 @@ }; rpm-regulator-boba { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "boba"; qcom,resource-id = <1>; qcom,regulator-type = <4>; @@ -587,14 +587,14 @@ status = "disabled"; regulator-pm5100a-bob { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100a_bob"; qcom,set = <3>; status = "disabled"; }; regulator-pm5100a-bob-ao { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100a_bob_ao"; qcom,set = <1>; status = "disabled"; @@ -602,7 +602,7 @@ }; rpm-regulator-chg-boost { - /* compatible = "qcom,rpm-smd-regulator-resource"; */ + compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "bsta"; qcom,resource-id = <1>; qcom,regulator-type = <1>; @@ -610,7 +610,7 @@ status = "disabled"; regulator-chg-boost { - /* compatible = "qcom,rpm-smd-regulator"; */ + compatible = "qcom,rpm-smd-regulator"; regulator-name = "pm5100_chg_boost"; qcom,set = <3>; status = "disabled"; From 8eb1a2d085ad191df7ce89b4ea04daf2ae595cb6 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 23 May 2024 17:03:00 +0530 Subject: [PATCH 11/59] bindings: soc: qcom: Document crm_b_pt register Document crm_b_pt register. Change-Id: Iec8522f68d516bd26c59924be0fe68be13d3a5e8 Signed-off-by: Maulik Shah --- bindings/soc/qcom/qcom,crm.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/soc/qcom/qcom,crm.yaml b/bindings/soc/qcom/qcom,crm.yaml index 99050074..4351a2ca 100644 --- a/bindings/soc/qcom/qcom,crm.yaml +++ b/bindings/soc/qcom/qcom,crm.yaml @@ -41,12 +41,13 @@ properties: - qcom,disp-crm-v2 reg: - minItems: 5 + minItems: 6 reg-names: items: - const: base - const: crm_b + - const: crm_b_pt - const: crm_c - const: crm_v - const: common From 404e2df2ce687a105d2265db8e74bb3b730be6c3 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 23 May 2024 17:00:26 +0530 Subject: [PATCH 12/59] ARM: dts: msm: Add CRMB_PT reg for sun CRMB_PT is used to dump TCS and FSM status. Change-Id: Ic5e72f8db923a3d009ecc25cdbe193401f7af091 Signed-off-by: Maulik Shah --- qcom/sun.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index ad1704e8..6e3f5fe7 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -1328,9 +1328,9 @@ disp_crm: crm@af21000 { label = "disp_crm"; compatible = "qcom,disp-crm-v2"; - reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27800 0x2000>, - <0xaf29800 0x700>, <0xaf29f00 0x100>; - reg-names = "base", "crm_b", "crm_c", "crm_v", "common"; + reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27400 0x400>, + <0xaf27800 0x2000>, <0xaf29800 0x700>, <0xaf29f00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; interrupts = , , , @@ -1351,9 +1351,9 @@ cam_crm: crm@adcb000 { label = "cam_crm"; compatible = "qcom,cam-crm-v2"; - reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd600 0x2000>, - <0xadcf600 0x700>, <0xadcfd00 0x100>; - reg-names = "base", "crm_b", "crm_c", "crm_v", "common"; + reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd200 0x400>, + <0xadcd600 0x2000>, <0xadcf600 0x700>, <0xadcfd00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; interrupts = ; interrupt-names = "cam_crm_drv0"; clocks = <&camcc CAM_CC_DRV_AHB_CLK>; @@ -1364,9 +1364,9 @@ pcie_crm: crm@1d01000 { label = "pcie_crm"; compatible = "qcom,pcie-crm-v2"; - reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03800 0x2000>, - <0x1d05800 0x700>, <0x1d05f00 0x100>; - reg-names = "base", "crm_b", "crm_c", "crm_v", "common"; + reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03400 0x400>, + <0x1d03800 0x2000>, <0x1d05800 0x700>, <0x1d05f00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; interrupts = ; interrupt-names = "pcie_crm_drv0"; clocks = <&pcie_0_pipe_clk>; From d66bf7fb83bf6e3200586db01f39adf2ddb4fd3b Mon Sep 17 00:00:00 2001 From: Visweswara Tanuku Date: Tue, 7 May 2024 00:34:20 -0700 Subject: [PATCH 13/59] dt-bindings: buses: Add new property in MSM geni serial bindings for Sun Change https://lore.kernel.org/all/20230525113034.46880-1-tony@atomide.com registers serial core controller as a child of msm uart device. Since child should suspend first, due to the child's auto suspend delay (SERIAL_PORT_AUTOSUSPEND_DELAY_MS), additional 500msecs delay is added during msm_geni_serial_runtime_suspend. Added new optional dtsi property 'qcom,suspend-ignore-children' which when set ignores dependencies on children by PM framework, this helps to exit quickly from msm_geni_serial_runtime_suspend and save power. Change-Id: I36b239cf19293ee7b1ebecf32cdd0ad0749dbca1 Signed-off-by: Visweswara Tanuku --- bindings/serial/qcom,serial-geni-msm.yaml | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/bindings/serial/qcom,serial-geni-msm.yaml b/bindings/serial/qcom,serial-geni-msm.yaml index e8f0d5dd..0dc0bc99 100644 --- a/bindings/serial/qcom,serial-geni-msm.yaml +++ b/bindings/serial/qcom,serial-geni-msm.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/serial/qcom,msm-geni-uart.yaml#" +$id: "http://devicetree.org/schemas/serial/qcom,serial-geni-msm.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Qualcomm Technologies, Inc. Serial UART for GENI based cores @@ -34,9 +34,8 @@ properties: - const: qup-memory interrupts: - minItems: 1 - items: - - description: UART core irq + description: first irq for UART core & second irq for host wake up + maxItems: 2 operating-points-v2: true @@ -59,9 +58,10 @@ properties: reg: maxItems: 1 - interrupts: - items: - - description: byte which is used for waking up. + # Optional property + qcom,suspend-ignore-children: + type: boolean + description: When set ignores dependencies on children by PM framework required: - compatible @@ -101,5 +101,6 @@ examples: pinctrl-3 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>, <&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>; qcom,wakeup-byte = <0xFD>; + qcom,suspend-ignore-children; }; ... From 1593cbeaee17ab75703843369be149849a492a8d Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Tue, 30 Apr 2024 16:21:07 +0530 Subject: [PATCH 14/59] dt-bindings: clock: qcom: add GCC and TCSRCC bindings on tuna Add GCC and TCSRCC clock bindings on tuna device. Change-Id: I0a5233ed94699c23d5b073de4ef9a59e89a72ab8 Signed-off-by: Ajit Pandey --- bindings/clock/qcom,gcc-sun.yaml | 7 +++++-- bindings/clock/qcom,tcsrcc.yaml | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/bindings/clock/qcom,gcc-sun.yaml b/bindings/clock/qcom,gcc-sun.yaml index c15ec607..29ca3d1a 100644 --- a/bindings/clock/qcom,gcc-sun.yaml +++ b/bindings/clock/qcom,gcc-sun.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,gcc-sun.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. Global Clock & Reset Controller Binding for SUN +title: Qualcomm Technologies, Inc. Global Clock & Reset Controller maintainers: - Xubin Bai @@ -15,10 +15,13 @@ description: | See also: - dt-bindings/clock/qcom,gcc-sun.h + - dt-bindings/clock/qcom,gcc-tuna.h properties: compatible: - const: qcom,gcc-sun + enum: + - qcom,gcc-sun + - qcom,tuna-gcc clocks: items: diff --git a/bindings/clock/qcom,tcsrcc.yaml b/bindings/clock/qcom,tcsrcc.yaml index 2cfa2181..18ada41c 100644 --- a/bindings/clock/qcom,tcsrcc.yaml +++ b/bindings/clock/qcom,tcsrcc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,tcsrcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. Top-Level CSR Clock & Reset Controller Binding +title: Qualcomm Technologies, Inc. Top-Level CSR Clock & Reset Controller maintainers: - Xubin Bai @@ -21,6 +21,7 @@ properties: enum: - qcom,pineapple-tcsrcc - qcom,sun-tcsrcc + - qcom,tuna-tcsrcc required: - compatible From 04c3732f8f7568ffc3d8e88c80092af16b18581d Mon Sep 17 00:00:00 2001 From: Varshitha H N Date: Fri, 24 May 2024 14:13:49 +0530 Subject: [PATCH 15/59] dt-bindings: leds: Add snapshot of qcom,leds-qpnp-flash-v2 bindings Add DT bindings for QPNP Flash LED v2 device that supports camera flash operation. Change-Id: I9169dacfec3bddffc830d9c744ea364d1cf977d1 Signed-off-by: Varshitha H N --- bindings/leds/qcom,leds-qpnp-flash-v2.yaml | 338 +++++++++++++++++++++ 1 file changed, 338 insertions(+) create mode 100644 bindings/leds/qcom,leds-qpnp-flash-v2.yaml diff --git a/bindings/leds/qcom,leds-qpnp-flash-v2.yaml b/bindings/leds/qcom,leds-qpnp-flash-v2.yaml new file mode 100644 index 00000000..0c547d1d --- /dev/null +++ b/bindings/leds/qcom,leds-qpnp-flash-v2.yaml @@ -0,0 +1,338 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/qcom,leds-qpnp-flash-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc. Plug-N-Play v2 Flash LED + +maintainers: + - Rakesh Kota + - Subbaraman Narayanamurthy + - Kamal Wadhwa + +description: | + QPNP (Qualcomm Technologies Inc. Plug N Play) Flash LED (Light + Emitting Diode) driver v2 is used to provide illumination to + camera sensor when background light is dim to capture good + picture. It can also be used for flashlight/torch application. + It is part of PMIC on Qualcomm Technologies Inc. reference platforms. + +properties: + compatible: + enum: + - qcom,pm6150l-flash-led-v2 + - qcom,pmi632-flash-led-v2 + + reg: + description: | + Base address and size for flash LED modules + maxItems: 1 + + interrupts: + description: | + Specifies the interrupts associated with this device. + + interrupt-names: + description: | + Specify the interrupt names associated with interrupts. + items: + - const: led-fault-irq + - const: mitigation-irq + - const: flash-timer-exp-irq + - const: all-ramp-down-done-irq + - const: all-ramp-up-done-irq + - const: led3-ramp-up-done-irq + - const: led2-ramp-up-done-irq + - const: led1-ramp-up-done-irq + + qcom,hdrm-auto-mode: + description: | + Boolean type to select headroom auto mode enabled or not + type: boolean + + qcom,isc-delay-us: + description: | + Integer type to specify short circuit delay. Valid values are 32, 64, + 128, 192. Unit is uS. + maxItems: 1 + +patternProperties: + '^switch[0-9]-supply$': + description: | + phandle of the regulator that needs to be used + as a supply for flash switch_X device. + + '^qcom,flash_[0-9]$': + type: object + properties: + label: + $ref: /schemas/types.yaml#/definitions/string-array + description: | + Specifies type of LED that will be used. + const: flash + + qcom,led-name: + description: | + Name of the LED. + $ref: /schemas/types.yaml#/definitions/string + + qcom,id: + description: | + Specifies the LED channel number for flash device. + It depends on hardware and starts with an index 0. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + + qcom,default-led-trigger: + description: | + Trigger for camera flash device. + $ref: /schemas/types.yaml#/definitions/string + + qcom,max-current: + description: | + Maximum current allowed on this LED. Valid values should be + integer from 0 to 1500 inclusive. Flash 2 should have maximum current of + 750 per hardware requirement. Unit is mA. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 1500 + + qcom,duration-ms: + description: | + Default time duration for flash LED device. Unit is ms. + minimum: 10 + maximum: 1280 + + qcom,ires-ua: + description: | + Current resolution for flash LED device. Unit is uA. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 5000, 12500 ] + + required: + - label + - qcom,led-name + - qcom,default-led-trigger + - qcom,id + - qcom,max-current + - qcom,duration-ms + + '^qcom,torch_[0-9]$': + type: object + properties: + label: + description: | + Specifies type of LED that will be used. + $ref: /schemas/types.yaml#/definitions/string-array + const: torch + + qcom,led-name: + description: | + Name of the LED. + $ref: /schemas/types.yaml#/definitions/string + + qcom,id: + description: | + Specifies the LED channel number for torch device. + It depends on hardware and starts with an index 0. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + qcom,default-led-trigger: + description: | + Trigger for torch device. + $ref: /schemas/types.yaml#/definitions/string + + qcom,max-current: + description: | + Maximum current allowed for torch device. Unit is mA. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 500 + default: 500 + + qcom,ires-ua: + description: | + Current resolution for torch device. Unit is uA. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 5000, 12500 ] + + required: + - label + - qcom,led-name + - qcom,default-led-trigger + - qcom,id + - qcom,max-current + + '^qcom,switch_[0-9]$': + type: object + properties: + label: + description: | + Specifies type of LED that will be used. + $ref: /schemas/types.yaml#/definitions/string-array + const: switch + + qcom,led-name: + description: | + Name of the LED. + $ref: /schemas/types.yaml#/definitions/string + + qcom,default-led-trigger: + description: | + Trigger for switch device. + $ref: /schemas/types.yaml#/definitions/string + + qcom,led-mask: + description: | + Required property for switch nodes. Bitmask to indicate which leds are + controlled by this switch node. Accepted values are in the range 1 to 7, + inclusive. Example qcom,led-mask = <4>; + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,symmetry-en: + description: | + Boolean property to specify if the flash LEDs under a + switch node are controlled symmetrically. This needs + to be specified if a group of flash LED channels are + connected to a single LED. + type: boolean + + required: + - label + - qcom,led-name + - qcom,default-led-trigger + - qcom,led-mask + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + qcom,leds@d300 { + compatible = "qcom,pm6150l-flash-led-v2"; + status = "okay"; + reg = <0xd300 0x100>; + interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xd3 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xd3 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xd3 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xd3 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xd3 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xd3 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xd3 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "led-fault-irq", + "mitigation-irq", + "flash-timer-exp-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq", + "led3-ramp-up-done-irq", + "led2-ramp-up-done-irq", + "led1-ramp-up-done-irq"; + qcom,hdrm-auto-mode; + qcom,isc-delay-us = <192>; + switch0-supply = <&pmi8998_bob>; + + qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,current = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + pinctrl-names = "led_enable","led_disable"; + pinctrl-0 = <&led_enable>; + pinctrl-1 = <&led_disable>; + }; + + qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,current = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + pinctrl-names = "led_enable","led_disable"; + pinctrl-0 = <&led_enable>; + pinctrl-1 = <&led_disable>; + }; + + qcom,switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + qcom,symmetry-en; + }; + + qcom,switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <4>; + qcom,default-led-trigger = "switch1_trigger"; + }; + }; +... From c1aa352dc493b96eccc97c79a7d084aab70f0a98 Mon Sep 17 00:00:00 2001 From: Varshitha H N Date: Sat, 25 May 2024 14:29:17 +0530 Subject: [PATCH 16/59] dt-bindings: leds: Add bindings for leds-qti-tri-led driver Add devicetree bindings for the leds-qti-tri-led driver. Change-Id: I31e2711220857c9d959b082057309390d4d2c3c0 Signed-off-by: Varshitha H N --- bindings/leds/qcom,leds-qti-tri-led.yaml | 38 +++++++++++++++--------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/bindings/leds/qcom,leds-qti-tri-led.yaml b/bindings/leds/qcom,leds-qti-tri-led.yaml index d11b4647..64ca5f9e 100644 --- a/bindings/leds/qcom,leds-qti-tri-led.yaml +++ b/bindings/leds/qcom,leds-qti-tri-led.yaml @@ -27,25 +27,33 @@ properties: nvmem: description: Phandle of the nvmem device name to access SDAM to do PBS trigger. This is required only for HR_LEDs. +patternProperties: + "^led@[0-9a-z]+$": + type: object + $ref: common.yaml# + unevaluatedProperties: false - pwms: - description: The PWM device (phandle) used for controlling LED. + properties: + pwms: + description: The PWM device (phandle) used for controlling LED. - led-sources: - description: see Documentation/devicetree/bindings/leds/common.txt; + led-sources: + description: see Documentation/devicetree/bindings/leds/common.txt; Device current output identifiers are 0 - LED1_EN, 1 - LED2_EN, 2 - LED3_EN. - label: - description: see Documentation/devicetree/bindings/leds/common.txt; + label: + description: see Documentation/devicetree/bindings/leds/common.txt; - linux,default-trigger: - description: see Documentation/devicetree/bindings/leds/common.txt; + linux,default-trigger: + description: see Documentation/devicetree/bindings/leds/common.txt; + + required: + - pwms + - led-sources required: - compatible - reg - - pwms - - led-sources allOf: - $ref: common.yaml# @@ -54,21 +62,23 @@ additionalProperties: false examples: - | - pmi8998_rgb: tri-led@d000{ + #include + + pmi8998_rgb: tri-led@d000 { compatible = "qcom,tri-led"; reg = <0xd000>; - red { + led@1 { label = "red"; pwms = <&pmi8998_lpg 4 1000000>; led-sources = <0>; }; - green { + led@2 { label = "green"; pwms = <&pmi8998_lpg 3 1000000>; led-sources = <1>; }; - blue { + led@3 { label = "blue"; pwms = <&pmi8998_lpg 2 1000000>; led-sources = <2>; From bb1bd0a9ff6a2a23eff28ba04cc6b38b6245bc92 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 8 May 2024 11:22:50 +0530 Subject: [PATCH 17/59] dt-bindings: regulator: Add bindings for PM8008 device Add bindings for PM8008 devices. This snapshot is taken from qclinux.1.0 branch commit 93af7f1c6008a ("QCLINUX: arm64: dts: qcom: Add bindings for qcom-i2c-pmic and PM8008 devices"). Change-Id: I8b1e88426bfe7f77c276922df8756be450237f77 Signed-off-by: Jishnu Prakash Signed-off-by: Varshitha H N --- bindings/regulator/qcom,pm8008-chip.yaml | 67 +++++++ bindings/regulator/qcom,pm8008-regulator.yaml | 185 ++++++++++++++++++ 2 files changed, 252 insertions(+) create mode 100644 bindings/regulator/qcom,pm8008-chip.yaml create mode 100644 bindings/regulator/qcom,pm8008-regulator.yaml diff --git a/bindings/regulator/qcom,pm8008-chip.yaml b/bindings/regulator/qcom,pm8008-chip.yaml new file mode 100644 index 00000000..fc98e1b1 --- /dev/null +++ b/bindings/regulator/qcom,pm8008-chip.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/qcom,pm8008-chip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. PM8008 Regulator's top-level chip + +maintainers: + - Umang Chheda + +description: | + PM8008 is an I2C based PMIC regulator chip. + +properties: + compatible: + const: qcom,pm8008-chip + + reg: + description: + Base address of the device. + + maxItems: 1 + +patternProperties: + "^qcom,pm8008-chip-en+$": + type: object + $ref: /schemas/regulator/regulator.yaml# + + description: | + Chip enable regulator device to control chip enable functionality. + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + i2c1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pm8008i_chip: pm8008i@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008i_active>; + + pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + reg = <0x900>; + + PM8008I_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008i-chip-en"; + }; + }; + }; + }; + +... diff --git a/bindings/regulator/qcom,pm8008-regulator.yaml b/bindings/regulator/qcom,pm8008-regulator.yaml new file mode 100644 index 00000000..f989e06a --- /dev/null +++ b/bindings/regulator/qcom,pm8008-regulator.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/qcom,pm8008-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. PM8008 Regulator + +maintainers: + - Umang Chheda + +description: | + PM8008 chips contain 7 LDO regulators along with a top-level chip sleep feature. + +properties: + compatible: + enum: + - qcom,pm8008-regulator + - qcom,pm8010-regulator + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + pm8008_en-supply: + description: + Reference to PM8008 chip enable regulator, which manages + chip enable functionlity of PM8008. + + vdd_l1_l2-supply: + description: + Parent supply for LDO1/LDO2 of PM8008. + + vdd_l3_l4-supply: + description: + Parent supply for LDO3/LDO4 of PM8008. + + vdd_l5-supply: + description: + Parent supply for LDO5 of PM8008. + + vdd_l6-supply: + description: + Parent supply for LDO6 of PM8008. + + vdd_l7-supply: + description: + Parent supply for LDO7 of PM8008. + +patternProperties: + "^regulator@[0-9a-f]+$": + type: object + $ref: /schemas/regulator/regulator.yaml# + + description: | + Individual regulator devices under PM8008 chip. + + properties: + reg: + maxItems: 1 + description: | + Base address of individual LDO. + + qcom,hpm-min-load: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Load current in uA which corresponds to the minimum load + which requires the regulator to be in high power mode. + + qcom,min-dropout-voltage: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Specifies the minimum voltage in microvolts that the parent + supply regulator must output above the output of this + regulator. It is only meaningful if the corresponding parent + supply property has been specified in the first level node. + + qcom,init-voltage: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Specifies the initial voltage in microvolts to for a regulator. + + required: + - reg + +required: + - compatible + - pm8008_en-supply + +additionalProperties: false + +examples: + - | + #include + + i2c1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pm8008i_ldo: pm8008i@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + + qcom,pm8008i-regulator { + compatible = "qcom,pm8008-regulator"; + #address-cells = <1>; + #size-cells = <0>; + + pm8008_en-supply = <&PM8008I_EN>; + vdd_l1_l2-supply = <&vreg_s8b_1p2>; + vdd_l3_l4-supply = <&vreg_bob>; + vdd_l5-supply = <&vreg_s1b_1p8>; + vdd_l6-supply = <&vreg_bob>; + vdd_l7-supply = <&vreg_bob>; + + + L1I: pm8008i_l1: regulator@4000 { + reg = <0x4000>; + regulator-name = "pm8008i_l1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + qcom,min-dropout-voltage = <160000>; + qcom,hpm-min-load = <30000>; + }; + + L2I: pm8008i_l2: regulator@4100 { + reg = <0x4100>; + regulator-name = "pm8008i_l2"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <128000>; + qcom,hpm-min-load = <30000>; + }; + + L3I: pm8008i_l3: regulator@4200 { + reg = <0x4200>; + regulator-name = "pm8008i_l3"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,min-dropout-voltage = <144000>; + }; + + L4I: pm8008i_l4: regulator@4300 { + reg = <0x4300>; + regulator-name = "pm8008i_l4"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <128000>; + }; + + L5I: pm8008i_l5: regulator@4400 { + reg = <0x4400>; + regulator-name = "pm8008i_l5"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,min-dropout-voltage = <136000>; + }; + + L6I: pm8008i_l6: regulator@4500 { + reg = <0x4500>; + regulator-name = "pm8008i_l6"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,min-dropout-voltage = <128000>; + }; + + L7I: pm8008i_l7: regulator@4600 { + reg = <0x4600>; + regulator-name = "pm8008i_l7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,min-dropout-voltage = <312000>; + }; + + }; + }; + }; + +... From bb99201e08ad9acd8f39f0e389b4b63622993973 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Mon, 27 May 2024 12:30:56 +0530 Subject: [PATCH 18/59] dt-bindings: Add new compatible v2, v3 for cpuss sleep stats Add new compatible qcom,cpuss-sleep-stats-v2 and qcom,cpuss-sleep-stats-v3. Change-Id: I3efb27195f81efc0b46d653cd9b0253eb495ff29 Signed-off-by: Minghao Zhang --- bindings/soc/qcom/cpuss-sleep-stats.yaml | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/bindings/soc/qcom/cpuss-sleep-stats.yaml b/bindings/soc/qcom/cpuss-sleep-stats.yaml index 46b007d3..5d592662 100644 --- a/bindings/soc/qcom/cpuss-sleep-stats.yaml +++ b/bindings/soc/qcom/cpuss-sleep-stats.yaml @@ -21,6 +21,8 @@ properties: compatible: enum: - qcom,cpuss-sleep-stats + - qcom,cpuss-sleep-stats-v2 + - qcom,cpuss-sleep-stats-v3 - qcom,cpuss-sleep-stats-v4 reg: @@ -97,6 +99,30 @@ examples: num-cpus = <8>; }; + - | + cpuss-sleep-stats@18000054 { + compatible = "qcom,cpuss-sleep-stats-v2"; + reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>, + <0x17830054 0x4>, <0x17880098 0x4>, <0x178C0000 0x10000>; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", + "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", + "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; + num-cpus = <4>; + }; + + - | + cpuss-sleep-stats@17800054 { + compatible = "qcom,cpuss-sleep-stats-v3"; + reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>, + <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>, + <0x17880098 0x4>, <0x178C0000 0x10000>; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", + "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", + "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", + "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; + num-cpus = <6>; + }; + - | cpuss-sleep-stats@17850000 { compatible = "qcom,cpuss-sleep-stats-v4"; From 6b293c7197c9d35a189d3db318794b0278826e13 Mon Sep 17 00:00:00 2001 From: Varshitha H N Date: Mon, 27 May 2024 12:07:07 +0530 Subject: [PATCH 19/59] dt-bindings: input: Add bindings for qpnp-power-on driver Add devicetree bindings for the qpnp-power-on driver. Change-Id: I826698a4413ac5ea6f438c238a5d936e0ec4fea7 Signed-off-by: Varshitha H N --- bindings/input/qcom,qpnp-power-on.yaml | 323 ++++++++++++------------- 1 file changed, 159 insertions(+), 164 deletions(-) diff --git a/bindings/input/qcom,qpnp-power-on.yaml b/bindings/input/qcom,qpnp-power-on.yaml index a95132e6..a2e5556c 100644 --- a/bindings/input/qcom,qpnp-power-on.yaml +++ b/bindings/input/qcom,qpnp-power-on.yaml @@ -9,7 +9,7 @@ title: Qualcomm Technologies, Inc. QPNP Power-on PMIC Peripheral maintainers: - David Collins -description: > +description: | qpnp-power-on devices support the power-on (PON) peripheral found on Qualcomm Technologies, Inc. PMICs. The supported functionality includes power on/off reason, kerelease detection, PMIC reset configurations and other @@ -22,117 +22,102 @@ properties: const: qcom,qpnp-power-on reg: - description: Specifies the SPMI base address for this - PON (power-on) peripheral. For PMICs that have - PON peripheral (GEN3) split into PON_HLOS and - PON_PBS, this can hold addresses of both. - PON_PBS base address needs to be specified for - such devices if "qcom,kdpwr-sw-debounce" is specified. + description: | + Specifies the SPMI base address for this PON (power-on) peripheral. + For PMICs that have PON peripheral (GEN3) split into PON_HLOS and + PON_PBS, this can hold addresses of both. PON_PBS base address needs + to be specified for such devices if "qcom,kdpwr-sw-debounce" is specified. reg-names: - description: For PON GEN1 and GEN2, it should be "pon". - and for PON GEN3, it should include "pon_hlos" and - optionally "pon_pbs". + description: | + For PON GEN1 and GEN2, it should be "pon". and for PON GEN3, it should + include "pon_hlos" and optionally "pon_pbs". interrupts: - description: Specifies the interrupts associated with PON. + description: | + Specifies the interrupts associated with PON. interrupt-names: - description: Specifies the interrupt names associated with - the interrupts property. Must be a subset of - "kpdpwr", "kpdpwr-bark", "resin", "resin-bark", - "cblpwr", "kpdpwr-resin-bark", and - "pmic-wd-bark". Bark interrupts are associated - with system reset configuration to allow default - reset configuration to be activated. If system - reset configuration is not supported then bark - interrupts are nops. Additionally, the - "pmic-wd-bark" interrupt can be added if the - system needs to handle PMIC watchdog barks. + description: | + Specifies the interrupt names associated with the interrupts property. + Must be a subset of "kpdpwr", "kpdpwr-bark", "resin", "resin-bark", + "cblpwr", "kpdpwr-resin-bark", and "pmic-wd-bark". Bark interrupts are + associated with system reset configuration to allow default reset + configuration to be activated. If system reset configuration is not supported + then bark interrupts are nops. Additionally, the "pmic-wd-bark" interrupt + can be added if the system needs to handle PMIC watchdog barks. qcom,pon-dbc-delay: - description: The debounce delay for the power-key interrupt - specified in us. - Possible values for GEN1 PON are - 15625, 31250, 62500, 125000, 250000, 500000, - 1000000 and 2000000. - Possible values for GEN2 PON are - 62, 123, 245, 489, 977, 1954, 3907, 7813, - 15625, 31250, 62500, 125000 and 250000. - Intermediate value is rounded down to the - nearest valid value. + description: | + The debounce delay for the power-key interrupt specified in us. + Possible values for GEN1 PON are 15625, 31250, 62500, 125000, 250000, 500000, + 1000000 and 2000000. Possible values for GEN2 PON are 62, 123, 245, 489, 977, + 1954, 3907, 7813, 15625, 31250, 62500, 125000 and 250000. + Intermediate value is rounded down to the nearest valid value. $ref: /schemas/types.yaml#/definitions/uint32 qcom,system-reset: - description: Boolean which specifies that this PON peripheral - can be used to reset the system. This property - can only be used by one device on the system. It - is an error to include it more than once. + description: | + Boolean which specifies that this PON peripheral can be used to reset the system. + This property can only be used by one device on the system. It is an error to + include it more than once. type: boolean qcom,modem-reset: - description: Boolean which specifies that this PON peripheral - can be used to reset the attached modem chip. - This property can only be used by one PON device - on the system. qcom,modem-reset and - qcom,system-reset cannot be specified for the - same PON device. + description: | + Boolean which specifies that this PON peripheral can be used to reset the attached + modem chip. This property can only be used by one PON device on the system. + qcom,modem-reset and qcom,system-reset cannot be specified for the same PON device. type: boolean qcom,s3-debounce: - description: The debounce delay for stage 3 reset trigger in - secs. The values range from 0 to 128. + description: | + The debounce delay for stage 3 reset trigger in secs. The values range from 0 to 128. $ref: /schemas/types.yaml#/definitions/uint32 qcom,s3-src: - description: The source for stage 3 reset. It can be one of - "kpdpwr", "resin", "kpdpwr-or-resin" or - "kpdpwr-and-resin". + description: | + The source for stage 3 reset. It can be one of "kpdpwr", "resin", "kpdpwr-or-resin" or + "kpdpwr-and-resin". $ref: /schemas/types.yaml#/definitions/uint32 qcom,clear-warm-reset: - description: Boolean which specifies that the WARM_RESET - reason registers need to be cleared for this - target. The property is used for the targets - which have a hardware feature to catch resets - which aren't triggered by the application - processor. In such cases clearing WARM_REASON - registers across processor resets keeps the - registers in a useful state. + description: | + Boolean which specifies that the WARM_RESET reason registers need to be cleared for this + target. The property is used for the targets which have a hardware feature to catch resets + which aren't triggered by the application processor. In such cases clearing WARM_REASON + registers across processor resets keeps the registers in a useful state. type: boolean qcom,secondary-pon-reset: - description: Boolean property which indicates that the PON - peripheral is a secondary PON device which - needs to be configured during reset in addition - to the primary PON device that is configured - for system reset through qcom,system-reset - property. - This should not be defined along with the - qcom,system-reset or qcom,modem-reset property. + description: | + Boolean property which indicates that the PON peripheral is a secondary PON device which + needs to be configured during reset in addition to the primary PON device that is configured + for system reset through qcom,system-reset property. + This should not be defined along with the qcom,system-reset or qcom,modem-reset property. type: boolean qcom,store-hard-reset-reason: - description: Boolean property which if set will store the - hardware reset reason to SOFT_RB_SPARE register - of the core PMIC PON peripheral. + description: | + Boolean property which if set will store the hardware reset reason to SOFT_RB_SPARE + register of the core PMIC PON peripheral. type: boolean qcom,hard-reset-poweroff-type: - description: Same description as - qcom,warm-reset-poweroff-type but this applies - for the system hard reset case. + description: | + Same description as qcom,warm-reset-poweroff-type but this applies for the system + hard reset case. type: boolean qcom,kpdpwr-sw-debounce: - description: Boolean property to enable the debounce logic - on the KPDPWR_N rising edge. + description: | + Boolean property to enable the debounce logic on the KPDPWR_N rising edge. type: boolean qcom,pon_X: - description: These PON child nodes correspond to features - supported by the PON peripheral including reset - configurations, pushbutton keys, and regulators. + description: | + These PON child nodes correspond to features supported by the PON peripheral + including reset configurations, pushbutton keys, and regulators. type: boolean required: @@ -140,29 +125,31 @@ required: - reg patternProperties: - "^pon-[0-9]+$": + '^qcom,pon_[0-9]$': type: object $ref: input.yaml# unevaluatedProperties: false properties: regulator-name: - description: Regulator name for the PON regulator that is being configured. + description: | + Regulator name for the PON regulator that is being configured. qcom,pon-spare-reg-addr: - description: Register offset from the base address of the - PON peripheral that needs to be configured for - the regulator being controlled. + description: | + Register offset from the base address of the PON peripheral that needs to be + configured for the regulator being controlled. $ref: /schemas/types.yaml#/definitions/uint32 qcom,pon-spare-reg-bit: - description: Bit position in the specified register that - needs to be configured for the regulator being - controlled. + description: | + Bit position in the specified register that needs to be configured for the + regulator being controlled. $ref: /schemas/types.yaml#/definitions/uint32 qcom,pon-type: - description: The type of PON/RESET source. Supported values are + description: | + The type of PON/RESET source. Supported values are 0 = KPDPWR 1 = RESIN 2 = CBLPWR @@ -172,12 +159,13 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32 qcom,pull-up: - description: Boolean flag indicating if a pull-up resistor - should be enabled for the input. + description: | + Boolean flag indicating if a pull-up resistor should be enabled for the input. type: boolean qcom,support-reset: - description: Indicates if this PON source supports + description: | + Indicates if this PON source supports reset functionality. 0 = Not supported 1 = Supported @@ -186,33 +174,32 @@ patternProperties: type: boolean qcom,use-bark: - description: Specify if this PON type needs to handle a bark - interrupt. + description: | + Specify if this PON type needs to handle a bark interrupt. type: boolean linux,code: - description: The input key-code associated with the reset - source. The reset source in its default - configuration can be used to support standard keys. + description: | + The input key-code associated with the reset source. The reset source in its + default configuration can be used to support standard keys. qcom,s1-timer: - description: The debounce timer for the BARK interrupt for - the reset source. Value is specified in ms. - Supported values are - 0, 32, 56, 80, 128, 184, 272, 408, 608, 904, - 1352, 2048, 3072, 4480, 6720, 10256 + description: | + The debounce timer for the BARK interrupt for the reset source. Value is + specified in ms. Supported values are 0, 32, 56, 80, 128, 184, 272, 408, 608, 904, + 1352, 2048, 3072, 4480, 6720, 10256 type: boolean qcom,s2-timer: - description: The debounce timer for the S2 reset specified - in ms. On the expiry of this timer, the PMIC - executes the reset sequence. - Supported values are - 0, 10, 50, 100, 250, 500, 1000, 2000 + description: | + The debounce timer for the S2 reset specified in ms. On the expiry of this timer, + the PMIC executes the reset sequence. Supported values are 0, 10, 50, 100, 250, + 500, 1000, 2000 type: boolean qcom,s2-type: - description: The type of reset associated with this source. + description: | + The type of reset associated with this source. Supported values 0 = SOFT_RESET (legacy) 1 = WARM_RESET @@ -242,76 +229,84 @@ additionalProperties: false examples: - | + #include + #include + #include + qcom,power-on@800 { - compatible = "qcom,qpnp-power-on"; - reg = <0x800>; - interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x8 0x4 IRQ_TYPE_EDGE_RISING>, - <0x0 0x8 0x5 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "kpdpwr", "resin", "resin-bark", - "kpdpwr-resin-bark"; - qcom,pon-dbc-delay = <15625>; - qcom,system-reset; - qcom,s3-debounce = <32>; - qcom,s3-src = "resin"; - qcom,clear-warm-reset; - qcom,store-hard-reset-reason; - qcom,pon_1 { - qcom,pon-type = ; - qcom,pull-up; - linux,code = ; - }; - qcom,pon_2 { - qcom,pon-type = ; - qcom,support-reset = <1>; - qcom,pull-up; - qcom,s1-timer = <0>; - qcom,s2-timer = <2000>; - qcom,s2-type = ; - linux,code = ; - qcom,use-bark; - }; - qcom,pon_3 { - qcom,pon-type = ; - qcom,support-reset = <1>; - qcom,s1-timer = <6720>; - qcom,s2-timer = <2000>; - qcom,s2-type = ; - qcom,pull-up; - qcom,use-bark; - }; + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x8 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x8 0x5 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "kpdpwr", "resin", "resin-bark", + "kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,s3-debounce = <32>; + qcom,s3-src = "resin"; + qcom,clear-warm-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,support-reset = <1>; + qcom,pull-up; + qcom,s1-timer = <0>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + linux,code = ; + qcom,use-bark; + }; + + qcom,pon_3 { + qcom,pon-type = ; + qcom,support-reset = <1>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + qcom,use-bark; + }; }; - | qcom,power-on@800 { - compatible = "qcom,qpnp-power-on"; - reg = <0x800>; - qcom,secondary-pon-reset; - qcom,hard-reset-poweroff-type = ; + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + qcom,secondary-pon-reset; + qcom,hard-reset-poweroff-type = ; - pon_perph_reg:qcom,pon_perph_reg { - regulator-name = "pon_spare_reg"; - qcom,pon-spare-reg-addr = <0x8c>; - qcom,pon-spare-reg-bit = <1>; - }; + pon_perph_reg:qcom,pon_perph_reg { + regulator-name = "pon_spare_reg"; + qcom,pon-spare-reg-addr = <0x8c>; + qcom,pon-spare-reg-bit = <1>; + }; }; - | pon_hlos@1300 { - compatible = "qcom,qpnp-power-on"; - reg = <0x1300>, <0x800>; - reg-names = "pon_hlos", "pon_pbs"; - interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH> - <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "kpdpwr", "resin"; - qcom,kpdpwr-sw-debounce; + compatible = "qcom,qpnp-power-on"; + reg = <0x1300>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,kpdpwr-sw-debounce; - qcom,pon_1 { - qcom,pon-type = ; - linux,code = ; - }; - qcom,pon_2 { - qcom,pon-type = ; - linux,code = ; - }; + qcom,pon_1 { + qcom,pon-type = ; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + linux,code = ; + }; }; ... From 77348a1ad7dc8f66b995008fea4354df4b51b2e6 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Mon, 27 May 2024 12:26:12 +0530 Subject: [PATCH 20/59] ARM: dts: msm: Update IRQ number for TUNA usb Currently, IRQ is set to IRQ = IRQ -2 for E2 builds, but for the E3 build IRQ number should be set according to document. Change-Id: I18cc6f3172b61cdb0af868b59db48e151a15fb2c Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index 0d4c7684..cb065d25 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -28,7 +28,7 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; - interrupts-extended = <&intc GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event_irq"; qcom,core-clk-rate = <200000000>; @@ -39,7 +39,7 @@ compatible = "snps,dwc3"; reg = <0xa600000 0xd93c>; - interrupts = ; + interrupts = ; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; From f89b0efd16ba49ad48453df871c852cda86bb989 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 8 Apr 2024 19:11:15 +0530 Subject: [PATCH 21/59] ARM: dts: msm: Add stub regulator devices for tuna Add stub regulator devices for the SMPS, LDO, and BOB regulators found on the PMICs used on tuna boards to allow the regulator clients to vote on them. Change-Id: I577485fa57f78e71d91fa1e783f20722113d957f Signed-off-by: Kavya Nunna --- qcom/tuna-stub-regulators.dtsi | 694 +++++++++++++++++++++++++++++++++ qcom/tuna.dtsi | 1 + 2 files changed, 695 insertions(+) create mode 100644 qcom/tuna-stub-regulators.dtsi diff --git a/qcom/tuna-stub-regulators.dtsi b/qcom/tuna-stub-regulators.dtsi new file mode 100644 index 00000000..c246692a --- /dev/null +++ b/qcom/tuna-stub-regulators.dtsi @@ -0,0 +1,694 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + + S1B: + pmxr2230_s1: regulator-pmxr2230-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2100000>; + }; + + S2B: + pmxr2230_s2: regulator-pmxr2230-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_s2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <2100000>; + }; + + S3B: + pmxr2230_s3: regulator-pmxr2230-s3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_s3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <690000>; + regulator-max-microvolt = <2100000>; + }; + + L1B: + pmxr2230_l1: regulator-pmxr2230-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <958000>; + }; + + L2B: + pmxr2230_l2: regulator-pmxr2230-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + }; + + L3B: + pmxr2230_l3: regulator-pmxr2230-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <831000>; + regulator-max-microvolt = <919000>; + }; + + L4B: + pmxr2230_l4: regulator-pmxr2230-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + }; + + L5B: + pmxr2230_l5: regulator-pmxr2230-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1980000>; + }; + + L6B: + pmxr2230_l6: regulator-pmxr2230-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1370000>; + }; + + L7B: + pmxr2230_l7: regulator-pmxr2230-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1980000>; + }; + + L8B: + pmxr2230_l8: regulator-pmxr2230-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + L9B: + pmxr2230_l9: regulator-pmxr2230-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <756000>; + regulator-max-microvolt = <816000>; + }; + + L10B: + pmxr2230_l10: regulator-pmxr2230-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <931000>; + }; + + L11B: + pmxr2230_l11: regulator-pmxr2230-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L12B: + pmxr2230_l12: regulator-pmxr2230-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + L13B: + pmxr2230_l13: regulator-pmxr2230-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + }; + + L14B: + pmxr2230_l14: regulator-pmxr2230-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l14"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + }; + + L15B: + pmxr2230_l15: regulator-pmxr2230-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l15"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L16B: + pmxr2230_l16: regulator-pmxr2230-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l16"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3544000>; + }; + + L17B: + pmxr2230_l17: regulator-pmxr2230-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L18B: + pmxr2230_l18: regulator-pmxr2230-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3544000>; + }; + + L19B: + pmxr2230_l19: regulator-pmxr2230-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3544000>; + }; + + L20B: + pmxr2230_l20: regulator-pmxr2230-l20 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l20"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + }; + + L21B: + pmxr2230_l21: regulator-pmxr2230-l21 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l21"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + }; + + L22B: + pmxr2230_l22: regulator-pmxr2230-l22 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l22"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3400000>; + }; + + L23B: + pmxr2230_l23: regulator-pmxr2230-l23 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmxr2230_l23"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + VDD_MODEM_LEVEL: + S1D_LEVEL: + pm_v6d_s1_level: regulator-pm_v6d-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MXC_LEVEL: + VDD_MM_MXC_VOTER_LEVEL: + VDD_GFX_MXC_VOTER_LEVEL: + S2D_LEVEL: + pm_v6d_s2_level: regulator-pm_v6d-s2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s2_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MXC_LEVEL_AO: + S2D_LEVEL_AO: + pm_v6d_s2_level_ao: regulator-pm_v6d-s2-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s2_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + S3D: + pm_v6d_s3: regulator-pm_v6d-s3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + VDD_NSP1_LEVEL: + S4D_LEVEL: + pm_v6d_s4_level: regulator-pm_v6d-s4-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_s4_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L1D: + pm_v6d_l1: regulator-pm_v6d-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <2000000>; + }; + + VDD_LPI_MX_LEVEL: + L2D_LEVEL: + pm_v6d_l2_level: regulator-pm_v6d-l2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_l2_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L3D: + pm_v6d_l3: regulator-pm_v6d-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6d_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1030000>; + regulator-max-microvolt = <1350000>; + }; + + VDD_CX_LEVEL: + S1F_LEVEL: + pm_v8f_s1_level: regulator-pm_v8f-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v8f_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL_AO: + S1F_LEVEL_AO: + pm_v8f_s1_level_ao: regulator-pm_v8f-s1-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v8f_s1_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MM_LEVEL: + S2F: + pm_v8f_s2: regulator-pm_v8f-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v8f_s2_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + S4F: + pm_v8f_s4: regulator-pm_v8f-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v8f_s4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + }; + + VDD_GFX_LEVEL: + S5F_LEVEL: + pm_v8f_s5_level: regulator-pm_v8f-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v8f_s5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MX_LEVEL: + S8F_LEVEL: + pm_v8f_s8_level: regulator-pm_v8f-s8-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v8f_s8_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MX_LEVEL_AO: + S8F_LEVEL_AO: + pm_v8f_s8_level_ao: regulator-pm_v8f-s8-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v8f_s8_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L1F: + pm_v8f_l1: regulator-pm_v8f-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v8f_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <958000>; + }; + + VDD_LPI_CX_LEVEL: + L2F_LEVEL: + pm_v8f_l2_level: regulator-pm_v8f-l2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v8f_l2_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L3F: + pm_v8f_l3: regulator-pm_v8f-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v8f_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + S1G: + pm_v6g_s1: regulator-pm_v6g-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2156000>; + regulator-max-microvolt = <2400000>; + }; + + S2G: + pm_v6g_s2: regulator-pm_v6g-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_s2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + VDD_EBI_LEVEL: + S3G_LEVEL: + pm_v6g_s3_level: regulator-pm_v6g-s3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_s3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L1G: + pm_v6g_l1: regulator-pm_v6g-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <2000000>; + }; + + L2G: + pm_v6g_l2: regulator-pm_v6g-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <2000000>; + }; + + L3G: + pm_v6g_l3: regulator-pm_v6g-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm_v6g_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + S1I: + pmg1110i_s1: regulator-pmg1110i-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmg1110i_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1352000>; + }; + + S1J: + pmg1110j_s1: regulator-pmg1110j-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmg1110j_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <868000>; + }; + + L1K: + pmr735b_l1: regulator-pmr735b-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <912000>; + }; + + L2K: + pmr735b_l2: regulator-pmr735b-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <969000>; + }; + + L3K: + pmr735b_l3: regulator-pmr735b-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1350000>; + }; + + L4K: + pmr735b_l4: regulator-pmr735b-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1950000>; + }; + + L5K: + pmr735b_l5: regulator-pmr735b-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <868000>; + }; + + L6K: + pmr735b_l6: regulator-pmr735b-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2000000>; + }; + + L7K: + pmr735b_l7: regulator-pmr735b-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735b_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <868000>; + }; + + L1M: + pm8010m_l1: regulator-pm8010m-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + L2M: + pm8010m_l2: regulator-pm8010m-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + }; + + L3M: + pm8010m_l3: regulator-pm8010m-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + L4M: + pm8010m_l4: regulator-pm8010m-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + L5M: + pm8010m_l5: regulator-pm8010m-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1980000>; + }; + + L6M: + pm8010m_l6: regulator-pm8010m-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + L7M: + pm8010m_l7: regulator-pm8010m-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + }; + + L1N: + pm8010n_l1: regulator-pm8010n-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + L2N: + pm8010n_l2: regulator-pm8010n-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + }; + + L3N: + pm8010n_l3: regulator-pm8010n-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1792000>; + regulator-max-microvolt = <1900000>; + }; + + L4N: + pm8010n_l4: regulator-pm8010n-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1792000>; + regulator-max-microvolt = <3312000>; + }; + + L5N: + pm8010n_l5: regulator-pm8010n-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + L6N: + pm8010n_l6: regulator-pm8010n-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + L7N: + pm8010n_l7: regulator-pm8010n-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3130000>; + regulator-max-microvolt = <3470000>; + }; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 8b73f368..2a8e2d8a 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -530,4 +530,5 @@ }; #include "tuna-pinctrl.dtsi" +#include "tuna-stub-regulators.dtsi" #include "tuna-usb.dtsi" From e3338c688564b0c267fb891079cb693ab73c63de Mon Sep 17 00:00:00 2001 From: Chetan C R Date: Mon, 8 Apr 2024 18:34:31 +0530 Subject: [PATCH 22/59] dt-bindings: clock: Add clock controller bindings for SM4450 Add clock controller bindings for RPMHCC/CAMCC/GCC/DISPCC/GPUCC and DEBUGCC on SM4450 Platform. Change-Id: I779f0915c24a12664e6566ac386cf4ac4dd911e6 Signed-off-by: Chetan C R --- bindings/clock/qcom,debugcc.yaml | 1 + bindings/clock/qcom,gpucc.yaml | 2 + bindings/clock/qcom,rpmhcc.yaml | 1 + bindings/clock/qcom,sm4450-camcc.yaml | 63 +++++++++++++++++++++++ bindings/clock/qcom,sm4450-dispcc.yaml | 71 ++++++++++++++++++++++++++ bindings/clock/qcom,sm4450-gcc.yaml | 55 ++++++++++++++++++++ 6 files changed, 193 insertions(+) create mode 100644 bindings/clock/qcom,sm4450-camcc.yaml create mode 100644 bindings/clock/qcom,sm4450-dispcc.yaml create mode 100644 bindings/clock/qcom,sm4450-gcc.yaml diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index 4f3b0dd8..1f057273 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -19,6 +19,7 @@ properties: - qcom,pineapple-debugcc - qcom,sun-debugcc - qcom,parrot-debugcc + - qcom,sm4450-debugcc clocks: items: diff --git a/bindings/clock/qcom,gpucc.yaml b/bindings/clock/qcom,gpucc.yaml index bfcedac6..81f6a9dc 100644 --- a/bindings/clock/qcom,gpucc.yaml +++ b/bindings/clock/qcom,gpucc.yaml @@ -18,6 +18,7 @@ description: | dt-bindings/clock/qcom,gpucc-sc7180.h dt-bindings/clock/qcom,gpucc-sc7280.h dt-bindings/clock/qcom,gpucc-sc8280xp.h + dt-bindings/clock/qcom,sm4450-gpucc.h dt-bindings/clock/qcom,gpucc-sm6350.h dt-bindings/clock/qcom,gpucc-sm8150.h dt-bindings/clock/qcom,gpucc-sm8250.h @@ -33,6 +34,7 @@ properties: - qcom,sc7280-gpucc - qcom,sc8180x-gpucc - qcom,sc8280xp-gpucc + - qcom,sm4450-gpucc - qcom,sm6350-gpucc - qcom,sm8150-gpucc - qcom,sm8250-gpucc diff --git a/bindings/clock/qcom,rpmhcc.yaml b/bindings/clock/qcom,rpmhcc.yaml index d87b775d..5088a111 100644 --- a/bindings/clock/qcom,rpmhcc.yaml +++ b/bindings/clock/qcom,rpmhcc.yaml @@ -25,6 +25,7 @@ properties: - qcom,sdm845-rpmh-clk - qcom,sdx55-rpmh-clk - qcom,sdx65-rpmh-clk + - qcom,sm4450-rpmh-clk - qcom,sm6350-rpmh-clk - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk diff --git a/bindings/clock/qcom,sm4450-camcc.yaml b/bindings/clock/qcom,sm4450-camcc.yaml new file mode 100644 index 00000000..1eda3fba --- /dev/null +++ b/bindings/clock/qcom,sm4450-camcc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Camera Clock & Reset Controller on SM4450 + +maintainers: + - Ajit Pandey + - Taniya Das + +description: | + Qualcomm Technologies, Inc. camera clock control module provides the clocks, resets and power + domains on SM4450 + + See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h + +properties: + compatible: + const: qcom,sm4450-camcc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Camera AHB clock source from GCC + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + clock-controller@ade0000 { + compatible = "qcom,sm4450-camcc"; + reg = <0x0ade0000 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,sm4450-dispcc.yaml b/bindings/clock/qcom,sm4450-dispcc.yaml new file mode 100644 index 00000000..150f63b8 --- /dev/null +++ b/bindings/clock/qcom,sm4450-dispcc.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Display Clock & Reset Controller on SM4450 + +maintainers: + - Ajit Pandey + - Taniya Das + +description: | + Qualcomm Technologies, Inc. display clock control module provides the clocks, resets and power + domains on SM4450 + + See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h + +properties: + compatible: + const: qcom,sm4450-dispcc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Display AHB clock source from GCC + - description: sleep clock source + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + clock-controller@af00000 { + compatible = "qcom,sm4450-dispcc"; + reg = <0x0af00000 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&dsi0_phy_pll_out_byteclk>, + <&dsi0_phy_pll_out_dsiclk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,sm4450-gcc.yaml b/bindings/clock/qcom,sm4450-gcc.yaml new file mode 100644 index 00000000..4fd7fab6 --- /dev/null +++ b/bindings/clock/qcom,sm4450-gcc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on SM4450 + +maintainers: + - Ajit Pandey + - Taniya Das + +description: | + Qualcomm Technologies, Inc. global clock control module provides the clocks, resets and power + domains on SM4450 + + See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h + +properties: + compatible: + const: qcom,sm4450-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: UFS Phy Rx symbol 0 clock source + - description: UFS Phy Rx symbol 1 clock source + - description: UFS Phy Tx symbol 0 clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,sm4450-gcc"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, <&usb_1_qmpphy>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... From ae5340a38806a9949ab7f47b86466cbce446378f Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Tue, 21 May 2024 16:22:32 +0530 Subject: [PATCH 23/59] dt-bindings: rpm-smd-regulator: Add bindings for rpm-smd regulator Add DT Bindings for rpm-smd regulator driver. Change-Id: I304c932cbf69799bd056ad3adaf00f4576d299f4 Signed-off-by: Ayyagari Ushasreevalli Signed-off-by: Umang Chheda --- bindings/regulator/rpm-smd-regulator.yaml | 548 ++++++++++++++++++++++ 1 file changed, 548 insertions(+) create mode 100644 bindings/regulator/rpm-smd-regulator.yaml diff --git a/bindings/regulator/rpm-smd-regulator.yaml b/bindings/regulator/rpm-smd-regulator.yaml new file mode 100644 index 00000000..9672de58 --- /dev/null +++ b/bindings/regulator/rpm-smd-regulator.yaml @@ -0,0 +1,548 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/rpm-smd-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. RPM Regulators + +maintainers: + - David Collins + - Kamal Wadhwa + - Jishnu Prakash + +description: | + rpm-regulator-smd is a regulator driver which supports regulators inside of + PMICs which are controlled by the RPM processor. Communication with the RPM + processor takes place over SMD. + + Required Node Structure: + + RPM regulators must be described in two levels of devices nodes. The first + level describes the interface with the RPM. The second level describes + properties of one regulator framework interface (of potentially many) to + the regulator. + +properties: + compatible: + const: qcom,rpm-smd-regulator-resource + + qcom,resource-name: + description: | + Resource name string for this regulator to be used in RPM + transactions. Length is 4 characters max. + $ref: /schemas/types.yaml#/definitions/string + + qcom,resource-id: + description: | + Resource instance ID for this regulator to be used in RPM + transactions. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,regulator-type: + description: | + Type of this regulator. Supported values are 0 = LDO, 1 = SMPS + 2 = VS, 3 = NCP, 4 = Buck or Boost (BoB) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 4 + + qcom,allow-atomic: + description: | + Boolean flag specifying if atomic access is allowed for this + regulator. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,enable-time: + description: + Time in us to delay after enabling the regulator + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hpm-min-load: + description: | + Load current in uA which corresponds to the minimum load + which requires the regulator to be in high power mode. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,apps-only: + description: | + Boolean flag which indicates that the regulator only has + consumers on the application processor. If this flag + is specified, then voltage and current updates are + only sent to the RPM if the regulator is enabled. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,always-wait-for-ack: + description: | + Boolean flag which indicates that the application processor + must wait for an ACK or a NACK from RPMh for every request + sent for this regulator including those which are for a + strictly lower power state. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,regulator-hw-type: + description: | + Specifies the regulator LDO hardware type. This + property must be specified if "qcom,regulator-type" + has been specified with a value of 0 (LDO). + + enum: + - pmic4-ldo + - pmic5-ldo + + qcom,supported-modes: + description: | + A list of integers specifying the PMIC regulator modes + supported by this regulator. Supported values are + RPMH_REGULATOR_MODE_* (i.e. 0 to 4). Elements must be + specified in order from lowest to highest. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 5 + items: + minimum: 0 + maximum: 4 + + qcom,mode-threshold-currents: + description: | + A list of integers specifying minimum allowed current in + microamps for each of the modes listed in qcom,supported-modes. + The first element should always be 0. Elements must be specified + in order from lowest to highest. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 5 + +additionalProperties: false + +required: + - compatible + - qcom,resource-name + - qcom,resource-id + - qcom,regulator-type + +patternProperties: + "^regulator.*$": + type: object + $ref: regulator.yaml# + description: regulator client voting interface node(s). + + properties: + compatible: + const: qcom,rpm-smd-regulator + + regulator-name: + description: A string used as a descriptive name for regulator output + + regulator-min-microvolt: + description: | + For VRM resources, this is the minimum supported voltage in + microvolts. For ARC resources, this is the minimum + supported voltage level from RPMH_REGULATOR_LEVEL_*. + + regulator-max-microvolt: + description: | + For VRM resources, this is the maximum supported voltage in + microvolts. For ARC resources, this is the maximum + supported voltage level from RPMH_REGULATOR_LEVEL_*. + + parent-supply: + description: | + phandle to the parent supply/regulator node. + + qcom,set: + description: | + Specifies which sets that requests made with this + regulator interface should be sent to. Regulator + requests sent in the active set take effect immediately. + Requests sent in the sleep set take effect when the Apps + processor transitions into RPM assisted power collapse. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 3 + + qcom,system-load: + description: | + Load in uA present on regulator that is not + captured by any consumer request. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,use-voltage-corner: + description: | + Flag that signifies if regulator_set_voltage + calls should modify the corner parameter instead + of the voltage parameter. When used, voltages + specified inside of the regulator framework + represent corners that have been incremented by + 1. This value shift is necessary to work around + limitations in the regulator framework which + treat 0 uV as an error. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,use-voltage-floor-corner: + description: | + Flag that signifies if regulator_set_voltage + calls should modify the floor corner parameter + instead of the voltage parameter. When used, + voltages specified inside of the regulator + framework represent corners that have been + incremented by 1. The properties + qcom,use-voltage-corner and + qcom,use-voltage-floor-corner are mutually + exclusive. Only one may be specified for a + given regulator. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,use-voltage-level: + description: | + Flag that signifies if regulator_set_voltage + calls should modify the level parameter instead + of the voltage parameter. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,use-voltage-floor-level: + description: | + Flag that signifies if regulator_set_voltage + calls should modify the floor level parameter + instead of the voltage parameter. + The properties qcom,use-voltage-level and + qcom,use-voltage-floor-level are mutually + exclusive. Only one may be specified for a + given regulator. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,use-pin-ctrl-voltage1: + description: | + Flag which indicates that updates to voltage + should be sent to the pin control voltage 1 + parameter. Only one pin may be specified per + regulator. This property only applies to BoB + type regulators. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,use-pin-ctrl-voltage2: + description: | + Flag which indicates that updates to voltage + should be sent to the pin control voltage 2 + parameter. Only one pin may be specified per + regulator. This property only applies to BoB + type regulators. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,use-pin-ctrl-voltage3: + description: | + Flag which indicates that updates to voltage + should be sent to the pin control voltage 3 + parameter. Only one pin may be specified per + regulator. This property only applies to BoB + type regulators. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,always-send-voltage: + description: | + Flag which indicates that updates to the + voltage, voltage corner or voltage level set + point should always be sent immediately to the + RPM. If this flag is not specified, then + voltage set point updates are only sent if the + given regulator has also been enabled by a + Linux consumer. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,always-send-current: + description: | + Flag which indicates that updates to the load + current should always be sent immediately to the + RPM. If this flag is not specified, then load + current updates are only sent if the given + regulator has also been enabled by a Linux + consumer. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,send-defaults: + description: | + Boolean flag which indicates that the initial + parameter values should be sent to the RPM + before consumers make their own requests. If + this flag is not specified, then initial + parameters values will only be sent after some + consumer makes a request. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,enable-with-pin-ctrl: + description: | + Double in which the first element corresponds to + the pin control enable parameter value to send + when all consumers have requested the regulator + to be disabled. The second element corresponds + to the pin control enable parameter value to + send when any consumer has requested the + regulator to be enabled. Each element supports + the same set of values as the + qcom,init-pin-ctrl-enable property listed below. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-enable: + description: | + Specifies the initial enable state to request for a VRM + regulator: 0 = disabled and 1 = enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 1 + + qcom,init-voltage: + description: Voltage in uV. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-current: + description: Current in mA. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-ldo-mode: + description: | + Operating mode to be used with LDO regulators + Supported values are 0 = mode determined by current requests + 1 = force HPM (NPM) + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-smps-mode: + description: | + Operating mode to be used with SMPS regulators + Supported values are: + 0 = auto; hardware determines mode + 1 = mode determined by current requests + 2 = force HPM (PWM) + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-bob-mode: + description: | + Operating mode to be used with BoB regulators + Supported values are: + 0 = pass; use priority order + 1 = force PFM + 2 = auto; hardware determines mode + 3 = force PWM + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-pin-ctrl-enable: + description: | + Bit mask specifying which hardware pins should be + used to enable the regulator, if any; supported + bits are: + 0 = ignore all hardware enable signals + BIT(0) = follow HW0_EN signal + BIT(1) = follow HW1_EN signal + BIT(2) = follow HW2_EN signal + BIT(3) = follow HW3_EN signal + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-pin-ctrl-mode: + description: | + Bit mask specifying which hardware pins should be + used to force the regulator into high power + mode, if any. Supported bits are: + 0 = ignore all hardware enable signals + BIT(0) = follow HW0_EN signal + BIT(1) = follow HW1_EN signal + BIT(2) = follow HW2_EN signal + BIT(3) = follow HW3_EN signal + BIT(4) = follow PMIC awake state + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-pin-ctrl-voltage1: + description: | + Minimum voltage in micro-volts to use while pin + control 1 is enabled. This property only + applies to BoB type regulators. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-pin-ctrl-voltage2: + description: | + Minimum voltage in micro-volts to use while pin + control 2 is enabled. This property only + applies to BoB type regulators. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-pin-ctrl-voltage3: + description: | + Minimum voltage in micro-volts to use while pin + control 3 is enabled. This property only + applies to BoB type regulators. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-frequency: + description: | + Switching frequency divisor for SMPS regulators. + Supported values are n = 0 to 31 where + freq = 19.2 MHz / (n + 1). + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-head-room: + description: | + Voltage head room in mV required for the + regulator. This head room value should be used + in situations where the device connected to the + output of the regulator has low noise tolerance. + Note that the RPM independently enforces a + safety head room value for subregulated LDOs + which is sufficient to account for LDO drop-out + voltage. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-quiet-mode: + description: | + Specify that quiet mode is needed for an SMPS + regulator in order to have lower output noise. + Supported values are: + 0 = No quiet mode + 1 = Quiet mode + 2 = Super quiet mode + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-freq-reason: + description: | + Consumer requiring specified frequency for an + SMPS regulator. Supported values are: + 0 = None + 1 = Bluetooth + 2 = GPS + 4 = WLAN + 8 = WAN + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-voltage-corner: + description: | + Performance corner to use in order to determine + voltage set point. This value corresponds to + the actual value that will be sent and is not + incremented by 1 like the values used inside of + the regulator framework. The meaning of corner + values is set by the RPM. It is possible that + different regulators on a given platform or + similar regulators on different platforms will + utilize different corner values. These are + corner values supported on MSM8974 for PMIC + PM8841 SMPS 2 (VDD_Dig); nominal voltages for + these corners are also shown: + 0 = None (don't care) + 1 = Retention (0.5000 V) + 2 = SVS Krait (0.7250 V) + 3 = SVS SOC (0.8125 V) + 4 = Normal (0.9000 V) + 5 = Turbo (0.9875 V) + 6 = Super Turbo (1.0500 V) + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-disallow-bypass: + description: | + Specify that bypass mode should not be used for a + given LDO regulator. When in bypass mode, an + LDO performs no regulation and acts as a simple + switch. The RPM can utilize this mode for an + LDO that is subregulated from an SMPS when it is + possible to reduce the SMPS voltage to the + desired LDO output level. Bypass mode may be + disallowed if lower LDO output noise is + required. Supported values are: + 0 = Allow RPM to utilize LDO bypass mode + if possible + 1 = Disallow LDO bypass mode + $ref: /schemas/types.yaml#/definitions/flag + + qcom,init-voltage-floor-corner: + description: | + Minimum performance corner to use if any + processor in the system is awake.This property + supports the same values as + qcom,init-voltage-corner. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-voltage-level: + description: | + Performance level to use in order to determine + voltage set point. The meaning of level + values is set by the RPM. It is possible that + different regulators on a given platform or + similar regulators on different platforms will + utilize different level values. These are + level values supported on MSM8952 for PMIC + PM8952 SMPS 2 (VDD_Dig); nominal voltages for + these level are also shown: + 16 = Retention (0.5000 V) + 128 = SVS (1.0500 V) + 192 = SVS+ (1.1550 V) + 256 = Normal (1.2250 V) + 320 = Normal+ (1.2875 V) + 384 = Turbo (1.3500 V) + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,init-voltage-floor-level: + description: | + Minimum performance level to use if any + processor in the system is awake. This property + supports the same values as + qcom,init-voltage-level + $ref: /schemas/types.yaml#/definitions/uint32 + + additionalProperties: false + + required: + - compatible + - regulator-name + - qcom,set + +examples: + - | + + rpm-regulator-smpb1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + + pm8841_s1: regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8841_s1"; + qcom,set = <3>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1150000>; + qcom,init-voltage = <1150000>; + }; + + pm8841_s1_ao: regulator-s1-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8841_s1_ao"; + qcom,set = <1>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1150000>; + }; + + pm8841_s1_corner: regulator-s1-corner { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8841_s1_corner"; + qcom,set = <3>; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <6>; + qcom,init-voltage-corner = <3>; + qcom,use-voltage-corner; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,hpm-min-load = <10000>; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "8941_l2"; + qcom,set = <3>; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,init-voltage = <1225000>; + }; + }; +... From 015ec04111aa747987801a96741dc9252287fee5 Mon Sep 17 00:00:00 2001 From: Nitesh Kumar Date: Mon, 27 May 2024 16:00:26 +0530 Subject: [PATCH 24/59] ARM: dts: qcom: update thermal zone shutdown trip type for parrot Use "hot" trip type for thermal zone software shutdown trip for all thermal zones. It just notifies userspace thermal manager which in turn triggers a graceful shutdown. Change-Id: I9c8d9e2db08941a93683993711c17705a78c8e3a Signed-off-by: Nitesh Kumar --- qcom/parrot-thermal.dtsi | 248 +++++++++++++++++++-------------------- qcom/pm6150l.dtsi | 6 +- qcom/pm6450.dtsi | 6 +- qcom/pm7250b.dtsi | 8 +- 4 files changed, 134 insertions(+), 134 deletions(-) diff --git a/qcom/parrot-thermal.dtsi b/qcom/parrot-thermal.dtsi index 2bbd3506..5f8de85c 100644 --- a/qcom/parrot-thermal.dtsi +++ b/qcom/parrot-thermal.dtsi @@ -257,8 +257,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -276,8 +276,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -295,8 +295,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -318,17 +318,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu4_emerg0: cpu4-emerg0-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; }; @@ -349,17 +349,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu4_emerg1: cpu4-emerg1-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; }; @@ -380,17 +380,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu5_emerg0: cpu5-emerg0-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -418,17 +418,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu5_emerg1: cpu5-emerg1-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -456,17 +456,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu6_emerg0: cpu6-emerg0-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -494,17 +494,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu6_emerg1: cpu6-emerg1-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -532,17 +532,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu7_emerg0: cpu7-emerg0-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -570,17 +570,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu7_emerg1: cpu7-emerg1-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -608,17 +608,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - gpu0_tj_cfg: tj_cfg { temperature = <95000>; hysteresis = <5000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -646,17 +646,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - gpu1_tj_cfg: tj_cfg { temperature = <95000>; hysteresis = <5000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -680,8 +680,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -699,8 +699,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -722,17 +722,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu0_emerg: cpu0-emerg-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -760,17 +760,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu1_emerg: cpu1-emerg-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -798,17 +798,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu2_emerg: cpu2-emerg-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -836,17 +836,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu3_emerg: cpu3-emerg-cfg { temperature = <110000>; hysteresis = <10000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -874,17 +874,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - nspss_0_config: junction-config { temperature = <95000>; hysteresis = <5000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -913,17 +913,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - nspss_1_config: junction-config { temperature = <95000>; hysteresis = <5000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -952,17 +952,17 @@ type = "passive"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - nspss_2_config: junction-config { temperature = <95000>; hysteresis = <5000>; type = "passive"; }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; }; cooling-maps { @@ -987,8 +987,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -1012,8 +1012,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; @@ -1062,8 +1062,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -1081,8 +1081,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -1100,8 +1100,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; @@ -1119,8 +1119,8 @@ reset-mon-cfg { temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + hysteresis = <0>; + type = "hot"; }; }; }; diff --git a/qcom/pm6150l.dtsi b/qcom/pm6150l.dtsi index 5f476b01..804052e8 100644 --- a/qcom/pm6150l.dtsi +++ b/qcom/pm6150l.dtsi @@ -421,16 +421,16 @@ type = "passive"; }; - pm6150l_trip1: trip1 { + trip1 { temperature = <115000>; hysteresis = <0>; - type = "passive"; + type = "hot"; }; trip2 { temperature = <145000>; hysteresis = <0>; - type = "passive"; + type = "critical"; }; }; }; diff --git a/qcom/pm6450.dtsi b/qcom/pm6450.dtsi index 3c08ec15..7199ac74 100644 --- a/qcom/pm6450.dtsi +++ b/qcom/pm6450.dtsi @@ -58,16 +58,16 @@ type = "passive"; }; - pm6450_trip1: trip1 { + trip1 { temperature = <115000>; hysteresis = <0>; - type = "passive"; + type = "hot"; }; trip2 { temperature = <145000>; hysteresis = <0>; - type = "passive"; + type = "critical"; }; }; }; diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index 4559bd12..dc5792bf 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -220,16 +220,16 @@ type = "passive"; }; - pm7250b_trip1: trip1 { + trip1 { temperature = <115000>; hysteresis = <0>; - type = "passive"; + type = "hot"; }; - pm7250b_trip2: trip2 { + trip2 { temperature = <145000>; hysteresis = <0>; - type = "passive"; + type = "critical"; }; }; }; From 7e2eb2e2e866338b22a23e667121e21a7e4c5245 Mon Sep 17 00:00:00 2001 From: Vinoth Jayaram Date: Tue, 21 May 2024 16:05:33 +0530 Subject: [PATCH 25/59] dt-bindings: Add dt binding for new touch drivers Add device tree binding document for Novatek, focal and Goodix touch drivers. Change-Id: Ic5e2b28dbee78860a00f715047bf99cd4e019b75 Signed-off-by: Vinoth Jayaram Signed-off-by: Raghavendra Ambadas --- .../input/touchscreen/focaltech,fts_ts.yaml | 107 ++++++++++++++++++ bindings/input/touchscreen/goodix_ts_i2c.yaml | 78 +++++++++++++ .../input/touchscreen/novatek_nt36xxx.yaml | 71 ++++++++++++ 3 files changed, 256 insertions(+) create mode 100644 bindings/input/touchscreen/focaltech,fts_ts.yaml create mode 100644 bindings/input/touchscreen/goodix_ts_i2c.yaml create mode 100644 bindings/input/touchscreen/novatek_nt36xxx.yaml diff --git a/bindings/input/touchscreen/focaltech,fts_ts.yaml b/bindings/input/touchscreen/focaltech,fts_ts.yaml new file mode 100644 index 00000000..265cc026 --- /dev/null +++ b/bindings/input/touchscreen/focaltech,fts_ts.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/focaltech,fts_ts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FocalTech touch controller DTB + +maintainers: + - Maulik Shah + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - focaltech,fts_ts + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: irq gpio + + focaltech,reset-gpio: + maxItems: 1 + + focaltech,irq-gpio: + description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin + as output to reset the device. + + irq-flags: + description: IRQ trigger type config. + 1 - rising edge, + 2 - falling edge, + 4 - high level, + 5 - low level. + + focaltech,max-touch-number: + description: maximum number of touches support + $ref: /schemas/types.yaml#/definitions/uint32 + + focaltech,display-coords: + description: display resolution in pixels. A four tuple consisting of minX, minY, maxX and maxY. + $ref: /schemas/types.yaml#/definitions/uint32 + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - focaltech,irq-gpio + - focaltech,reset-gpio + - focaltech,max-touch-number + - focaltech,display-coords + +examples: + - | + #include + #include + + i2c@f9927000 { + #address-cells = <1>; + #size-cells = <0>; + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&msm_gpio>; + interrupts = <13 0x02>; + focaltech,reset-gpio = <&msm_gpio 12 0x01>; + focaltech,irq-gpio = <&msm_gpio 13 0x02>; + focaltech,max-touch-number = <10>; + focaltech,display-coords = <0 0 1080 1920>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + /* + focaltech,have-key; + focaltech,key-number = <3>; + focaltech,keys = <139 102 158>; + focaltech,key-x-coords = <200 600 800>; + focaltech,key-y-coords = <2000 2000 2000>; + */ + }; + }; + + spi@78b9000 { + focaltech@0 { + compatible = "focaltech,fts_ts"; + reg = <0x0>; + spi-max-frequency = <6000000>; + interrupt-parent = <&msm_gpio>; + interrupts = <13 0x2>; + focaltech,reset-gpio = <&msm_gpio 12 0x01>; + focaltech,irq-gpio = <&msm_gpio 13 0x02>; + focaltech,max-touch-number = <10>; + focaltech,display-coords = <0 0 1080 1920>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + }; + }; diff --git a/bindings/input/touchscreen/goodix_ts_i2c.yaml b/bindings/input/touchscreen/goodix_ts_i2c.yaml new file mode 100644 index 00000000..f134fd2e --- /dev/null +++ b/bindings/input/touchscreen/goodix_ts_i2c.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/goodix_ts_i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ChipOne ICN8318 Touchscreen Controller DTB + +maintainers: + - Maulik Shah + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - goodix,gt9916 + - goodix,gt9966 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + irq-gpio: + description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin + as output to reset the device. + + irq-flags: + description: IRQ trigger type config. + 1 - rising edge, + 2 - falling edge, + 4 - high level, + 5 - low level. + + interrupts: + maxItems: 1 + + vdd-supply: + description: Power supply regulator for the chip + + vddio-supply: + description: Power supply regulator for the I2C bus + +unevaluatedProperties: false + +required: + - compatible + - reg + - reset-gpios + - irq-gpio + - irq-flags + - interrupts + - touchscreen-size-x + - touchscreen-size-y + - touchscreen-size-w + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + touchscreen@5d { + compatible = "goodix,gt9916"; + reg = <0x5d>; + reset-gpio = <&msm_gpio 12 0x0>; + irq-gpio = <&msm_gpio 13 0x2800>; + irq-flags = <2>; /* 1:trigger rising, 2:trigger falling;*/ + touchscreen-max-x = <720>; + touchscreen-max-y = <1280>; + touchscreen-max-w = <255>; + }; + }; diff --git a/bindings/input/touchscreen/novatek_nt36xxx.yaml b/bindings/input/touchscreen/novatek_nt36xxx.yaml new file mode 100644 index 00000000..73812c4b --- /dev/null +++ b/bindings/input/touchscreen/novatek_nt36xxx.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/novatek_nt36xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek nt36xxx touch controller DTB + +maintainers: + - Maulik Shah + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - novatek,NVT-ts + + reg: + maxItems: 1 + + novatek,reset-gpios: + maxItems: 1 + + novatek,irq-gpio: + description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin + as output to reset the device. + + irq-flags: + description: IRQ trigger type config. + 1 - rising edge, + 2 - falling edge, + 4 - high level, + 5 - low level. + + vdd-supply: + description: digital voltage power supply needed to power device. + + avdd-supply: + description: analog voltage power supply needed to power device + +unevaluatedProperties: false + +required: + - compatible + - reg + - vdd-supply + - avdd-supply + - reset-gpios + - irq-gpio + +examples: + - | + #include + #include + + i2c_1 { + #address-cells = <1>; + #size-cells = <0>; + /* Novatek device tree node */ + novatek@62 { + compatible = "novatek,NVT-ts"; + reg = <0x62>; + status = "ok"; + vdd-supply = <&pm8994_lvs2>; + avdd-supply = <&pm8994_l22>; + novatek,reset-gpio = <&msm_gpio 102 0x00>; + novatek,irq-gpio = <&msm_gpio 65 0x2001>; + }; + }; From 359a23fcde78f8918dcfb850aa28d86443604326 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Mon, 20 May 2024 15:10:20 +0530 Subject: [PATCH 26/59] ARM: dts: msm: Add cmd-db, RSC and PDC devices for tuna Add cmd-db, APPS RSC, Camera RSC, Display RSC and APSS PDC devices for RPMH communication and wakeup interrupt support. Change-Id: I6983b7a7711e728085d3125102ce95632ca6d9ad Signed-off-by: Maulik Shah --- qcom/tuna-rumi.dtsi | 8 +++ qcom/tuna.dtsi | 163 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 171 insertions(+) diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi index 9a5d1f6e..d378dc43 100644 --- a/qcom/tuna-rumi.dtsi +++ b/qcom/tuna-rumi.dtsi @@ -38,3 +38,11 @@ maximum-speed = "high-speed"; }; }; + +&cam_rsc { + status = "disabled"; +}; + +&disp_rsc { + status = "disabled"; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 8b73f368..e744a899 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Tuna"; @@ -292,6 +293,155 @@ }; }; + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x17a00000 0x10000>, + <0x17a10000 0x10000>, + <0x17a20000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + qcom,drv-count = <3>; + interrupts = , + , + ; + + apps_rsc_drv2: drv@2 { + qcom,drv-id = <2>; + qcom,tcs-offset = <0xd00>; + qcom,tcs-distance = <0x2a0>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + }; + }; + + cam_rsc: rsc@adc8000 { + label = "cam_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xadc8000 0x1000>, + <0xadc9000 0x1000>, + <0xadca000 0x1000>; + reg-names = "drv-0", "drv-1", "drv-2"; + qcom,drv-count = <3>; + qcom,hw-channel; + interrupts = , + , + ; + clocks = <&camcc CAM_CC_DRV_AHB_CLK>; + + cam_rsc_drv0: drv@0 { + qcom,drv-id = <0>; + qcom,tcs-offset = <0x520>; + qcom,tcs-distance = <0x150>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + channel@1 { + qcom,tcs-config = , + , + , + , + ; + }; + }; + + cam_rsc_drv1: drv@1 { + qcom,drv-id = <1>; + qcom,tcs-offset = <0x520>; + qcom,tcs-distance = <0x150>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + channel@1 { + qcom,tcs-config = , + , + , + , + ; + }; + }; + + cam_rsc_drv2: drv@2 { + qcom,drv-id = <2>; + qcom,tcs-offset = <0x520>; + qcom,tcs-distance = <0x150>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + channel@1 { + qcom,tcs-config = , + , + , + , + ; + }; + }; + }; + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x1000>; + reg-names = "drv-0"; + qcom,drv-count = <1>; + interrupts = ; + clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + + disp_rsc_drv0: drv@0 { + qcom,drv-id = <0>; + qcom,tcs-offset = <0x520>; + qcom,tcs-distance = <0x150>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,tuna-pdc", "qcom,pdc"; + reg = <0xb220000 0x10000>, <0x17c000f0 0x60>; + qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>, + <10 230 1>, <11 724 1>, <12 716 1>, + <13 727 1>, <14 720 1>, <15 726 1>, + <16 721 1>, <17 262 1>, <18 70 1>, + <19 723 1>, <20 234 1>, <22 725 1>, + <23 231 1>, <24 504 14>, <40 520 6>, + <51 531 4>, <58 538 2>, <61 541 4>, + <67 547 27>, <94 609 31>, <125 63 1>, + <126 366 2>, <128 374 1>, <129 378 1>, + <130 428 1>, <131 434 2>, <133 437 1>, + <134 452 2>, <136 458 2>, <138 464 11>, + <149 671 1>, <150 688 1>, <151 714 2>, + <153 722 1>, <154 255 1>, <155 269 2>, + <157 276 1>, <158 287 1>, <159 306 4>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,tuna-tlmm"; reg = <0x0f000000 0x1000000>; @@ -300,6 +450,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pdc>; }; ipcc_mproc: qcom,ipcc@406000 { @@ -529,5 +680,17 @@ status = "ok"; }; +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aop_cmd_db_mem: aop_cmd_db_region@81c60000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x81c60000 0x0 0x20000>; + }; +}; + #include "tuna-pinctrl.dtsi" #include "tuna-usb.dtsi" From 9e0a737bb6cc67c9bc0cf379da2e8a870aa29067 Mon Sep 17 00:00:00 2001 From: Varshitha H N Date: Mon, 27 May 2024 15:15:24 +0530 Subject: [PATCH 27/59] dt-bindings: pwm-qti-lpg: Fix a typo Replace a colon added mistakenly at a line end with a semicolon. Change-Id: I41a51db834489c9fad7ece35a58eccadd35d3a20 Signed-off-by: Varshitha H N --- bindings/pwm/qcom,pwm-qti-lpg.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/pwm/qcom,pwm-qti-lpg.yaml b/bindings/pwm/qcom,pwm-qti-lpg.yaml index b1fb34b5..53f9904a 100644 --- a/bindings/pwm/qcom,pwm-qti-lpg.yaml +++ b/bindings/pwm/qcom,pwm-qti-lpg.yaml @@ -280,7 +280,7 @@ examples: qcom,lut-patterns = <0 14 28 42 56 70 84 100 100 84 70 56 42 28 14 0>; lpg@1 { - qcom,lpg-sdam-base = <0x48>: + qcom,lpg-sdam-base = <0x48>; qcom,lpg-chan-id = <1>; qcom,ramp-step-ms = <200>; qcom,ramp-low-index = <0>; From ae76661b027d7029de3627f203fb413a57f3c645 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Tue, 28 May 2024 20:28:53 +0530 Subject: [PATCH 28/59] ARM: dts: msm: Remove redundant device nodes Cpu and logbuf vendor hook module moved to simple helper loadable modules and now there is no need of them to have device node in device tree. Change-Id: I97b79f76eef5743755746c684e8d306c11c9a507 Signed-off-by: Mukesh Ojha --- qcom/sun.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 6e3f5fe7..3ef9a243 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2149,10 +2149,6 @@ mem-type = <2>; }; - logbuf: qcom,logbuf-vendor-hooks { - compatible = "qcom,logbuf-vendor-hooks"; - }; - qcom,mpm2-sleep-counter@c221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; @@ -3101,10 +3097,6 @@ qcom,rx-chans = <0x20>; }; - vendor_hooks: qcom,cpu-vendor-hooks { - compatible = "qcom,cpu-vendor-hooks"; - }; - scmi: qcom,scmi { #address-cells = <1>; #size-cells = <0>; From b2b3ef52b1da102c2e0bfe91e9f1964c5b96a4b1 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Mon, 27 May 2024 13:02:12 +0530 Subject: [PATCH 29/59] ARM: dts: msm: Use "iommu-addresses" property for parrot qup Use upstream compatible DT property "iommu-addresses" instead of "qcom,iommu-dma-addr-pool" for qup which describes the addresses that qup cannot use. Change-Id: I3d678df7b9ee4687e86bc7eb914235a780deec0c Signed-off-by: Saranya R --- qcom/parrot-qupv3.dtsi | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/qcom/parrot-qupv3.dtsi b/qcom/parrot-qupv3.dtsi index 96b058e9..ad42a88c 100644 --- a/qcom/parrot-qupv3.dtsi +++ b/qcom/parrot-qupv3.dtsi @@ -19,6 +19,13 @@ * Qup1 5: SE 11 */ + qup_iommu_region: qup_iommu_region { + iommu-addresses = <&gpi_dma0 0x0 0x100000>, <&gpi_dma0 0x200000 0xffe00000>, + <&qupv3_0 0x0 0x40000000>, <&qupv3_0 0x50000000 0xb0000000>, + <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xffe00000>, + <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>; + }; + /* GPI Instance */ gpi_dma0: qcom,gpi-dma@900000 { compatible = "qcom,gpi-dma"; @@ -41,7 +48,7 @@ ; qcom,gpii-mask = <0x3f>; qcom,ev-factor = <2>; - qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + memory-region = <&qup_iommu_region>; dma-coherent; qcom,gpi-ee-offset = <0x10000>; status = "ok"; @@ -57,7 +64,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; iommus = <&apps_smmu 0x163 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + memory-region = <&qup_iommu_region>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; dma-coherent; @@ -343,7 +350,7 @@ qcom,static-gpii-mask = <0x1>; qcom,gpii-mask = <0x3e>; qcom,ev-factor = <2>; - qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + memory-region = <&qup_iommu_region>; dma-coherent; qcom,gpi-ee-offset = <0x10000>; status = "ok"; @@ -359,7 +366,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; iommus = <&apps_smmu 0x403 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + memory-region = <&qup_iommu_region>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; dma-coherent; From 22c0a29a7bdb94b8c0d3180399b37c606d7c2e46 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Mon, 27 May 2024 13:05:44 +0530 Subject: [PATCH 30/59] ARM: dts: msm: Use "iommu-addresses" property for parrot dwc3 Use upstream compatible DT property "iommu-addresses" instead of "qcom,iommu-dma-addr-pool" for dwc3 which describes the addresses that dwc3 cannot use. Extend the address and size cells to ensure that IOMMU returns a 32 bit address, in order to define a region that will block 0xf0000000--0xffffffffffffffff. Change-Id: Idb5640a5a63bfa50c7fac61e785012df733e82c6 Signed-off-by: Saranya R --- qcom/parrot-usb.dtsi | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/qcom/parrot-usb.dtsi b/qcom/parrot-usb.dtsi index b67043a5..3c70d4a7 100644 --- a/qcom/parrot-usb.dtsi +++ b/qcom/parrot-usb.dtsi @@ -12,8 +12,8 @@ reg = <0xa600000 0x100000>; reg-names = "core_base"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; @@ -53,13 +53,13 @@ <&aggre1_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>, <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>; - dwc3@a600000 { + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xd800>; + reg = <0x0 0xa600000 0x0 0xd800>; iommus = <&apps_smmu 0x80 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + memory-region = <&dwc3_mem_region>; dma-coherent; interrupts = ; @@ -79,6 +79,12 @@ }; + dwc3_mem_region: dwc3_mem_region { + iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>, + <&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>; + }; + + /* USB port related High Speed PHY */ usb2_phy0: hsphy@88e3000 { compatible = "qcom,usb-hsphy-snps-femto"; From b0287b59fd16cd9d53be92a242537676216f147d Mon Sep 17 00:00:00 2001 From: Koushik Immadisetty Date: Wed, 29 May 2024 15:06:22 +0530 Subject: [PATCH 31/59] dt-bindings: Add device-tree bindings for aon spi & interface drivers Add snapshot of device-tree bindings for AON spi, interface and it's corresponding rpmsg drivers from msm-5.15.c2 in YAML format. Snapshot is taken from msm-5.15.c2 kernel commit 95ffcf910eee ("ARM: dts: msm: add aon-rma glink node"). Change-Id: I5c66e660b674fee78f541b267027a34f92717e0c Signed-off-by: Koushik Immadisetty --- .../soc/qcom/qcom,slatecom_interface.yaml | 38 +++++++++++++++ bindings/soc/qcom/qcom,slatecom_rpmsg.yaml | 46 +++++++++++++++++++ bindings/soc/qcom/qcom,slatecom_spi.yaml | 37 +++++++++++++++ 3 files changed, 121 insertions(+) create mode 100644 bindings/soc/qcom/qcom,slatecom_interface.yaml create mode 100644 bindings/soc/qcom/qcom,slatecom_rpmsg.yaml create mode 100644 bindings/soc/qcom/qcom,slatecom_spi.yaml diff --git a/bindings/soc/qcom/qcom,slatecom_interface.yaml b/bindings/soc/qcom/qcom,slatecom_interface.yaml new file mode 100644 index 00000000..518b700e --- /dev/null +++ b/bindings/soc/qcom/qcom,slatecom_interface.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,slatecom_interface.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Slatecom Interface Driver + +maintainers: + - Praveen koya + +description: | + slatecom_interface driver creates a slate_com_dev device + node for user space communication. Single user space + client can open device node for communication from hardware. + Hardware will provide access to read/write registers or AHB + memory in the device. + +properties: + compatible: + const: qcom,slate-daemon + + qcom,platform-reset-gpio: + description: This gpio state used to make boot decision for slate subsystem. + +required: + - compatible + - qcom,platform-reset-gpio + +additionalProperties: false + +examples: + - | + qcom,slate-daemon { + compatible = "qcom,slate-daemon"; + qcom,platform-reset-gpio = <&pm5100_gpios 15 0>; + }; + diff --git a/bindings/soc/qcom/qcom,slatecom_rpmsg.yaml b/bindings/soc/qcom/qcom,slatecom_rpmsg.yaml new file mode 100644 index 00000000..2e46ad0c --- /dev/null +++ b/bindings/soc/qcom/qcom,slatecom_rpmsg.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,slatecom_rpmsg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Slatecom RPMSG Driver + +maintainers: + - Praveen koya + +description: | + slatecom_rpmsg driver provides functionality + to send and receive data over Glink from slate co processor. + +properties: + compatible: + const: qcom,slatecom-rpmsg + + qcom,glink-channels: + $ref: '/schemas/types.yaml#/definitions/string' + description: specifies the glink channel name + + qcom,glinkpkt-edge: + $ref: '/schemas/types.yaml#/definitions/string' + description: specifies the glink edge to match + + intents: + description: specifies the size and count of intents to glink + +required: + - compatible + - qcom,glink-channels + - qcom,glinkpkt-edge + +additionalProperties: false + +examples: + - | + qcom,slatecom-rpmsg { + compatible = "qcom,slatecom-rpmsg"; + qcom,glink-channels = "slate_ctrl"; + qcom,glinkpkt-edge = "slate"; + intents = <0x200 1>; + }; + diff --git a/bindings/soc/qcom/qcom,slatecom_spi.yaml b/bindings/soc/qcom/qcom,slatecom_spi.yaml new file mode 100644 index 00000000..d8414156 --- /dev/null +++ b/bindings/soc/qcom/qcom,slatecom_spi.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,slatecom_spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Slate Coprocessor Communication Driver + +maintainers: + - Praveen koya + +description: | + slatecom_spi driver provides a set of apis to perform + register, fifo, ahb read and write operations with slate + over spi interface. It also reads slate status and + sends events to the registered clients. + +properties: + compatible: + const: qcom,slate-spi + + qcom,irq-gpio: + description: IRQ used by the slate to inturrupt MSM. + +required: + - compatible + +additionalProperties: false + +examples: + - | + qcom,slate-spi { + compatible = "qcom,slate-spi"; + interrupt-parent = <&tlmm>; + /* IRQ from slate */ + qcom,irq-gpio = <&tlmm 104 1>; + }; From b912e1e0ac37e0ae57f16c9e40db2e46626c287c Mon Sep 17 00:00:00 2001 From: Koushik Immadisetty Date: Wed, 29 May 2024 15:44:00 +0530 Subject: [PATCH 32/59] dt-bindings: Add device-tree bindings for AON event bridge driver Add snapshot of device-tree bindings for AON event bridge and respective rpmsg drivers from msm-5.15.c2 in YAML format. Snapshot is taken from msm-5.15.c2 kernel commit 95ffcf910eee ("ARM: dts: msm: add aon-rma glink node"). Change-Id: I695cab16e872800d558ccf269c1cb32bbe9bb2f0 Signed-off-by: Koushik Immadisetty --- .../soc/qcom/qcom,slate_events_bridge.yaml | 30 ++++++++++++ .../qcom/qcom,slate_events_bridge_rpmsg.yaml | 46 +++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 bindings/soc/qcom/qcom,slate_events_bridge.yaml create mode 100644 bindings/soc/qcom/qcom,slate_events_bridge_rpmsg.yaml diff --git a/bindings/soc/qcom/qcom,slate_events_bridge.yaml b/bindings/soc/qcom/qcom,slate_events_bridge.yaml new file mode 100644 index 00000000..ce958966 --- /dev/null +++ b/bindings/soc/qcom/qcom,slate_events_bridge.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,slate_events_bridge.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Slate Events Bridge Driver + +maintainers: + - Praveen koya + +description: | + slate_events_bridge driver provides a set of apis for clients + to receive events from slate co processor. The events are + received over Glink. + +properties: + compatible: + const: qcom,slate-events-bridge + +required: + - compatible + +additionalProperties: false + +examples: + - | + qcom,slate-events-bridge { + compatible = "qcom,slate-events-bridge"; + }; diff --git a/bindings/soc/qcom/qcom,slate_events_bridge_rpmsg.yaml b/bindings/soc/qcom/qcom,slate_events_bridge_rpmsg.yaml new file mode 100644 index 00000000..80d3373e --- /dev/null +++ b/bindings/soc/qcom/qcom,slate_events_bridge_rpmsg.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,slate_events_bridge_rpmsg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Slate Events Bridge RPMSG Driver + +maintainers: + - Praveen koya + +description: | + slate_events_bridge_rpmsg driver provides functionality + to send and receive data over Glink from slate co processor. + +properties: + compatible: + const: qcom,slate-events-bridge-rpmsg + + qcom,glink-channels: + $ref: '/schemas/types.yaml#/definitions/string' + description: specifies the glink channel name + + qcom,glinkpkt-edge: + $ref: '/schemas/types.yaml#/definitions/string' + description: specifies the glink edge to match + + intents: + description: specifies the size and count of intents to glink + +required: + - compatible + - qcom,glink-channels + - qcom,glinkpkt-edge + +additionalProperties: false + +examples: + - | + qcom,slate-events-bridge-rpmsg { + compatible = "qcom,slate-events-bridge-rpmsg"; + qcom,glink-channels = "slate_events"; + qcom,glinkpkt-edge = "slate"; + intents = <0x200 5>; + }; + From cf17fb59752a5c66727df911a60fe45ce698aff9 Mon Sep 17 00:00:00 2001 From: Koushik Immadisetty Date: Wed, 29 May 2024 15:52:06 +0530 Subject: [PATCH 33/59] dt-bindings: Add device-tree bindings for aon RSB driver Add snapshot of device-tree bindings for AON RSB driver and corresponding rpmsg driver from msm-5.15.c2 in YAML format. Snapshot is taken from msm-5.15.c2 kernel commit 95ffcf910eee ("ARM: dts: msm: add aon-rma glink node"). Change-Id: I73bbb30403a488a053ba2b8a3aaf456190162506 Signed-off-by: Koushik Immadisetty --- bindings/soc/qcom/qcom,slate_rsb.yaml | 30 ++++++++++++++ bindings/soc/qcom/qcom,slatersb_rpmsg.yaml | 47 ++++++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 bindings/soc/qcom/qcom,slate_rsb.yaml create mode 100644 bindings/soc/qcom/qcom,slatersb_rpmsg.yaml diff --git a/bindings/soc/qcom/qcom,slate_rsb.yaml b/bindings/soc/qcom/qcom,slate_rsb.yaml new file mode 100644 index 00000000..d287df2f --- /dev/null +++ b/bindings/soc/qcom/qcom,slate_rsb.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,slate_rsb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm technologies, Inc. slate-rsb + +maintainers: + - Praveen koya + +description: | + slate-rsb is used to communicate with Slate over Glink + to configure the RSB eventsslate-rsb send commands over glink to + send configure, enable/disable RSB to Slate + +properties: + compatible: + const: qcom,slate-rsb + +required: + - compatible + +additionalProperties: false + +examples: + - | + qcom,slate-rsb { + compatible = "qcom,slate-rsb"; + }; diff --git a/bindings/soc/qcom/qcom,slatersb_rpmsg.yaml b/bindings/soc/qcom/qcom,slatersb_rpmsg.yaml new file mode 100644 index 00000000..f1c64c37 --- /dev/null +++ b/bindings/soc/qcom/qcom,slatersb_rpmsg.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,slatersb_rpmsg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm technologies, Inc. slatersb-rpmsg + +maintainers: + - Praveen koya + +description: | + slatersb-rpmsg is used as an interface between slate-rsb + and slate for Glink communication.slate-rsb is used to communicate with + Slate over Glink to configure the RSB events. + +properties: + compatible: + const: qcom,slatersb-rpmsg + + qcom,glink-channels: + $ref: '/schemas/types.yaml#/definitions/string' + description: specifies the glink channel name + + qcom,glinkpkt-edge: + $ref: '/schemas/types.yaml#/definitions/string' + description: specifies the glink edge to match + + intents: + description: specifies the size and count of intents to glink + +required: + - compatible + - qcom,glink-channels + - qcom,glinkpkt-edge + - intents + +additionalProperties: false + +examples: + - | + qcom,slatersb-rpmsg { + compatible = "qcom,slatersb-rpmsg"; + qcom,glink-channels = "RSB_CTRL"; + qcom,glinkpkt-edge = "slate"; + intents = <0x200 1>; + }; From 21931c9f8fc1e8734b5cd1806f07e3777be2fe44 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Mon, 22 Apr 2024 17:25:39 +0530 Subject: [PATCH 34/59] ARM: dts: msm: Add support for dummy clocks/GDSCs for kera Add the dummy clock and gdsc handles for clients to be able to request on them for kera platform. Change-Id: I24fa8bf818483947760c8b87497b25bcf40be84c Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 229 ++++++++++++++++++++++++++++++++++++++++++++ qcom/tuna-gdsc.dtsi | 31 ++++++ 2 files changed, 260 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 47451b2e..a235c5d8 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -3,6 +3,14 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include +#include +#include +#include +#include +#include +#include #include #include @@ -293,6 +301,227 @@ #interrupt-cells = <3>; #mbox-cells = <2>; }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + pcie_0_pipe_clk: pcie_0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_1_pipe_clk: pcie_1_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + }; + + rpmhcc: clock-controller { + compatible = "fixed-clock"; + clock-output-names = "rpmh_clocks"; + clock-frequency = <19200000>; + #clock-cells = <1>; + }; + + cambistmclkcc: clock-controller@1760000 { + compatible = "qcom,dummycc"; + clock-output-names = "cambistmclkcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,dummycc"; + clock-output-names = "camcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,dummycc"; + clock-output-names = "gpucc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + tcsrcc: clock-controller@1f40000 { + compatible = "qcom,dummycc"; + clock-output-names = "tcsrcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,dummycc"; + clock-output-names = "videocc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; + +#include "tuna-gdsc.dtsi" + +&cam_cc_ipe_0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_ofe_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_tfe_0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_tfe_1_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_tfe_2_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&cam_cc_titan_top_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&disp_cc_mdss_core_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_pcie_0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_pcie_0_phy_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_pcie_1_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_pcie_1_phy_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_ufs_mem_phy_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gcc_usb3_phy_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&gpu_cc_cx_gdsc_hw_ctrl { + reg = <0x3d99124 0x4>; +}; + +&gpu_cc_cx_gdsc { + compatible = "regulator-fixed"; + reg = <0x3d99110 0x4>; + status = "ok"; +}; + +&gpu_cc_gx_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&video_cc_mvs0_gdsc { + compatible = "regulator-fixed"; + status = "ok"; +}; + +&video_cc_mvs0c_gdsc { + compatible = "regulator-fixed"; + status = "ok"; }; #include "kera-pinctrl.dtsi" diff --git a/qcom/tuna-gdsc.dtsi b/qcom/tuna-gdsc.dtsi index 8524ab0f..d01386f7 100644 --- a/qcom/tuna-gdsc.dtsi +++ b/qcom/tuna-gdsc.dtsi @@ -138,6 +138,28 @@ status = "disabled"; }; + gcc_pcie_1_gdsc: qcom,gdsc@1ac004 { + compatible = "qcom,gdsc"; + reg = <0x1ac004 0x4>; + regulator-name = "gcc_pcie_1_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gcc_pcie_1_phy_gdsc: qcom,gdsc@1ad000 { + compatible = "qcom,gdsc"; + reg = <0x1ad000 0x4>; + regulator-name = "gcc_pcie_1_phy_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 { compatible = "qcom,gdsc"; reg = <0x19e000 0x4>; @@ -201,6 +223,15 @@ status = "disabled"; }; + gpu_cc_gx_gdsc: qcom,gdsc@3d9905c { + compatible = "regulator-fixed"; + reg = <0x3d9905c 0x4>; + regulator-name = "gpu_cc_gx_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + /* GX_CLKCTL GDSCs */ gx_clkctl_gx_gdsc: qcom,gdsc@3d68024 { compatible = "qcom,gdsc"; From b3aca64a1416246c8167b1078cf13a6526d67a10 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Thu, 23 May 2024 21:37:29 +0530 Subject: [PATCH 35/59] ARM: dts: qcom: Enable UFS MCQ on Pineapple platforms Enable the UFS MCQ feature on the Pineapple platforms. Change-Id: I205f0c0444d5579333cac28a504a89985b95b469 Signed-off-by: Manish Pandey --- qcom/pineapple.dtsi | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/qcom/pineapple.dtsi b/qcom/pineapple.dtsi index df5c84db..5b41ab58 100644 --- a/qcom/pineapple.dtsi +++ b/qcom/pineapple.dtsi @@ -1479,11 +1479,20 @@ }; }; + ufshc_dma_resv: ufshc_dma_resv_region { + /* + * Restrict IOVA mappings for UFSHC buffers to the 3 GB region + * from 0x1000 - 0xffffffff. + */ + iommu-addresses = <&ufshc_mem 0x0 0x1000>; + }; + ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, - <0x1d88000 0x18000>; - reg-names = "ufs_mem", "ice"; + <0x1d88000 0x18000>, + <0x1da5000 0x2000>, <0x1da4000 0x10>; + reg-names = "ufs_mem", "ice", "mcq_sqd", "mcq_vs"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; @@ -1492,7 +1501,7 @@ qcom,ice-use-hwkm; qcom,prime-mask = <0x80>; qcom,silver-mask = <0x0f>; - qcom,esi-affinity-mask = <0xf0>; + qcom,esi-affinity-mask = <0xe0>; lanes-per-direction = <2>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ @@ -1594,11 +1603,17 @@ iommus = <&apps_smmu 0x60 0x0>; qcom,iommu-dma = "fastmap"; + qcom,iommu-msi-size = <0x1000>; + memory-region = <&ufshc_dma_resv>; shared-ice-cfg = <&ice_cfg>; dma-coherent; qcom,bypass-pbl-rst-wa; + msi-parent = <&gic_its 0x60>; + qcom,max-cpus = <8>; + qcom,broken-ahit-wa; + status = "disabled"; qos0 { From c89ee097754a48a92a426d5e3763496d2627062e Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Fri, 31 May 2024 11:01:11 +0530 Subject: [PATCH 36/59] dt-bindings: qcom-pm8xxx-rtc: Document qcom,pm5100-rtc for pm8xxx-rtc Add compatible qcom,pm5100-rtc for qcom-pm8xxx-rtc bindings. Change-Id: Icfea70a16f60dba921a67c1788bfa04e853b3eed Signed-off-by: Ayyagari Ushasreevalli --- bindings/rtc/qcom-pm8xxx-rtc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/rtc/qcom-pm8xxx-rtc.yaml b/bindings/rtc/qcom-pm8xxx-rtc.yaml index 23ab5bb4..861733d6 100644 --- a/bindings/rtc/qcom-pm8xxx-rtc.yaml +++ b/bindings/rtc/qcom-pm8xxx-rtc.yaml @@ -17,6 +17,7 @@ properties: - qcom,pm8941-rtc - qcom,pm8018-rtc - qcom,pmk8350-rtc + - qcom,pm5100-rtc reg: minItems: 1 From d85f0b015f8d915747a4d62f627c33b79c8b0c56 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Fri, 31 May 2024 16:36:47 +0800 Subject: [PATCH 37/59] dt-bindings: pinctrl: Correct the documentation path for x1e80100 TLMM block Correct the documentation path for x1e80100 TLMM block. Change-Id: I89b18586c0a0d40c3aa82a746c1478f6f20f24fe Signed-off-by: Lijuan Gao --- .../bindings => bindings}/pinctrl/qcom,x1e80100-tlmm.yaml | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename {Documentation/devicetree/bindings => bindings}/pinctrl/qcom,x1e80100-tlmm.yaml (100%) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml b/bindings/pinctrl/qcom,x1e80100-tlmm.yaml similarity index 100% rename from Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml rename to bindings/pinctrl/qcom,x1e80100-tlmm.yaml From 3d5331410a751587e289275fce965fb3f7ab50fd Mon Sep 17 00:00:00 2001 From: Nageswara reddy Karnati Date: Wed, 6 Mar 2024 02:31:40 -0800 Subject: [PATCH 38/59] dt-bindings: Add dt binding for qseecom Addition of dt binding file for qseecom node. Change-Id: I0e0443352915559e5e5a4cdc32d92f0fb48e221a Signed-off-by: Nageswara reddy Karnati --- bindings/qseecom/qcom,qseecom.yaml | 143 +++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 bindings/qseecom/qcom,qseecom.yaml diff --git a/bindings/qseecom/qcom,qseecom.yaml b/bindings/qseecom/qcom,qseecom.yaml new file mode 100644 index 00000000..3fa58a85 --- /dev/null +++ b/bindings/qseecom/qcom,qseecom.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/qseecom/qcom,qseecom.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: "QSEECOM driver to provide transport between TZ and Linux." + +description: | + The QSEECOM driver facilitates the communication and data transfer between + Trust Zone and Linux OS. + +maintainers: + - Vikas Kumar Sharma + +properties: + compatible: + const: qcom,qseecom + reg: + description: "Should contain memory region address reserved for loading secure apps." + maxItems: 2 + + qcom,disk-encrypt-pipe-pair: + description: "Indicates what CE HW pipe pair is used for disk encryption." + $ref: "/schemas/types.yaml#/definitions/uint32" + + qcom,file-encrypt-pipe-pair: + description: "Indicates what CE HW pipe pair is used for file encryption." + $ref: "/schemas/types.yaml#/definitions/uint32" + + qcom,support-multiple-ce-hw-instance: + description: "Indicates if multicore CE support is supported." + type: boolean + + qcom,hlos-num-ce-hw-instances: + description: "Indicates number of CE HW instances hlos can use." + $ref: "/schemas/types.yaml#/definitions/uint32" + + qcom,qsee-ce-hw-instance: + description: "Indicates what CE HW is used by secure domain (TZ) crypto driver." + $ref: "/schemas/types.yaml#/definitions/uint32" + + qcom,msm_bus,name: + description: "Should be 'qseecom-noc'." + const: "qseecom-noc" + + qcom,msm_bus,num_cases: + description: "Depends on the use cases for bus scaling." + $ref: "/schemas/types.yaml#/definitions/uint32" + + qcom,msm_bus,num_paths: + description: "The paths for source and destination ports." + $ref: "/schemas/types.yaml#/definitions/uint32" + + qcom,msm_bus,vectors: + description: "Vectors for bus topology." + $ref: "/schemas/types.yaml#/definitions/uint32-array" + + qcom,ce-opp-freq: + description: "Indicates the CE operating frequency in Hz, changes from target to target." + $ref: "/schemas/types.yaml#/definitions/uint32" + + qcom,full-disk-encrypt-info: + description: "Vectors defining full disk encryption unit, crypto engine, pipe pair configuration in ." + $ref: "/schemas/types.yaml#/definitions/uint32-array" + + qcom,per-file-encrypt-info: + description: "Vectors defining per file encryption unit, crypto engine, pipe pair configuration in ." + $ref: "/schemas/types.yaml#/definitions/uint32-array" + + qcom,support-bus-scaling: + description: "Indicates if driver supports scaling the bus for crypto operation." + type: boolean + + qcom,support-fde: + description: "Indicates if driver supports key managing for full disk encryption feature." + type: boolean + + qcom,support-pfe: + description: "Indicates if driver supports key managing for per file encryption feature." + type: boolean + + qcom,no-clock-support: + description: "Indicates clocks are not handled by qseecom (could be handled by RPM)." + type: boolean + + qcom,appsbl-qseecom-support: + description: "Indicates if there is qseecom support in apps bootloader." + type: boolean + + qcom,qsee-reentrancy-support: + description: "Indicates the qsee reentrancy phase supported by the target." + type: boolean + + qcom,commonlib64-loaded-by-uefi: + description: "Indicates commonlib64 is loaded by UEFI already." + type: boolean + + qcom,fde-key-size: + description: "Indicates which FDE key size is used in device." + type: boolean + +required: + - compatible + - reg + - qcom,disk-encrypt-pipe-pair + - qcom,file-encrypt-pipe-pair + - qcom,support-multiple-ce-hw-instance + - qcom,hlos-num-ce-hw-instances + - qcom,qsee-ce-hw-instance + - qcom,msm_bus,name + - qcom,msm_bus,num_cases + - qcom,msm_bus,num_paths + - qcom,msm_bus,vectors + - qcom,ce-opp-freq + - qcom,full-disk-encrypt-info + - qcom,per-file-encrypt-info + +additionalProperties: false + +examples: + - | + qcom,qseecom@7f00000: + compatible: "qcom,qseecom" + reg: <0x7f00000 0x500000> + reg-names: "secapp-region" + qcom,disk-encrypt-pipe-pair: <2> + qcom,file-encrypt-pipe-pair: <0> + qcom,support-multiple-ce-hw-instance: true + qcom,hlos-num-ce-hw-instances: <2> + qcom,qsee-ce-hw-instance: <0> + qcom,support-fde: true + qcom,support-pfe: true + qcom,msm_bus,name: "qseecom-noc" + qcom,msm_bus,num_cases: <4> + qcom,msm_bus,active_only: <0> + qcom,msm_bus,num_paths: <1> + qcom,no-clock-support: true + qcom,appsbl-qseecom-support: true + qcom,fde-key-size: true + qcom,msm_bus,vectors: [<55, 512, 0, 0>, <55, 512, 3936000000, 393600000>, <55, 512, 3936000000, 393600000>, <55, 512, 3936000000, 393600000>] + qcom,ce-opp-freq: <100000000> + vdd-hba-supply: "&gdsc_ufs" From 323c7decbab16ca616c48ebf870881bff84e465a Mon Sep 17 00:00:00 2001 From: Syed Ahmed Date: Sat, 1 Jun 2024 12:11:46 +0530 Subject: [PATCH 39/59] ARM: dts: qcom: Novatek touch screen compatible string added for parrot Added compatible string for touch screen novatek,NVT-ts for parrot. Change-Id: I25f19eb2ce731e05c979ab1fdbfd1af85ef87733 Signed-off-by: Syed Ahmed --- qcom/parrot-idp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/parrot-idp.dtsi b/qcom/parrot-idp.dtsi index cdc545c5..eca7841f 100644 --- a/qcom/parrot-idp.dtsi +++ b/qcom/parrot-idp.dtsi @@ -43,6 +43,7 @@ novatek@62 { reg = <0x62>; + compatible = "novatek,NVT-ts"; interrupt-parent = <&tlmm>; interrupts = <13 0x2008>; From bd5fa79a770b8a1db4dd6b02212491c66202065b Mon Sep 17 00:00:00 2001 From: Nageswara reddy Karnati Date: Fri, 31 May 2024 02:15:31 -0700 Subject: [PATCH 40/59] ARM: dts: msm: parrot: Add qseecom compatible Add dt support for qseecom for Parrot SOC. Change-Id: Idfca637295821e47183e865fd257e44cb4a4dc58 Signed-off-by: Nageswara reddy Karnati --- qcom/parrot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 72be3bec..cde29e0e 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -1772,6 +1772,7 @@ }; qcom_qseecom: qseecom@c1700000 { + compatible = "qcom,qseecom"; memory-region = <&qseecom_mem>; qseecom_mem = <&qseecom_mem>; qseecom_ta_mem = <&qseecom_ta_mem>; From 24e6ec54d7ceb3c4ab50dd123df2d5d56bc7d75e Mon Sep 17 00:00:00 2001 From: Prerna Singh Date: Tue, 30 Apr 2024 11:22:23 +0530 Subject: [PATCH 41/59] dt-bindings: clock: Add clock controller bindings for Monaco Add clock controller bindings for GCC/GPUCC/DISPCC/DEBUGCC on Monaco Platform. Add clock controller bindings for RPMCC for Monaco, Khaje and Holi platform. Change-Id: I98e6b2094daabc6e6b8b450a397ea3c19799b50a Signed-off-by: Prerna Singh --- bindings/clock/qcom,debugcc.yaml | 1 + bindings/clock/qcom,dispcc-monaco.yaml | 75 ++++++++++++++++++++++++++ bindings/clock/qcom,gcc-monaco.yaml | 69 ++++++++++++++++++++++++ bindings/clock/qcom,gpucc.yaml | 2 + bindings/clock/qcom,rpmcc.yaml | 3 ++ 5 files changed, 150 insertions(+) create mode 100644 bindings/clock/qcom,dispcc-monaco.yaml create mode 100644 bindings/clock/qcom,gcc-monaco.yaml diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index 1f057273..2de7c538 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -20,6 +20,7 @@ properties: - qcom,sun-debugcc - qcom,parrot-debugcc - qcom,sm4450-debugcc + - qcom,monaco-debugcc clocks: items: diff --git a/bindings/clock/qcom,dispcc-monaco.yaml b/bindings/clock/qcom,dispcc-monaco.yaml new file mode 100644 index 00000000..10273f77 --- /dev/null +++ b/bindings/clock/qcom,dispcc-monaco.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-monaco.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Display Clock & Reset Controller + +maintainers: + - Taniya Das + +description: | + Qualcomm Technologies, Inc. display clock control module which supports the clocks and + power domains on Monaco. + + See also: + dt-bindings/clock/qcom,dispcc-monaco.h + +properties: + compatible: + enum: + - qcom,monaco-dispcc + + clocks: + items: + - description: Brard XO source + - description: Brard XO_AO source + - description: Sleep clock source + - description: GPLL0 OUT MAIN clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: gpll0_out_main + + vdd_cx-supply: + description: Phandle pointer to the vdd_cx logic rail supply + + vdd_mxa-supply: + description: Phandle pointer to the vdd_mxa logic rail supply + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + dispcc: clock-controller@5f00000 { + compatible = "qcom,monaco-dispcc", "syscon"; + reg = <0x05f00000 0x20000>; + reg-names = "cc_base"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main", + "sleep_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GPLL0>, <&sleep_clk>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,gcc-monaco.yaml b/bindings/clock/qcom,gcc-monaco.yaml new file mode 100644 index 00000000..34224d72 --- /dev/null +++ b/bindings/clock/qcom,gcc-monaco.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-monaco.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Global Clock & Reset Controller + +maintainers: + - Taniya Das + +description: | + Global clock control module which supports the clocks, resets and + power domains on Monaco. + + See also: + - dt-bindings/clock/qcom,gcc-monaco.h + +properties: + compatible: + const: qcom,monaco-gcc + + clocks: + items: + - description: Board XO source + - description: Board XO_AO source + - description: Sleep clock source + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + minItems: 2 + + vdd_cx-supply: + description: Phandle pointer to the vdd_cx logic rail supply + + vdd_mxa-supply: + description: Phandle pointer to the vdd_mxa logic rail supply + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: "qcom,gcc.yaml#" + +unevaluatedProperties: false + +examples: + - | + #include + gcc: clock-controller@1410000 { + compatible = "qcom,monaco-gcc", "syscon"; + reg = <0x1400000 0x1e0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,gpucc.yaml b/bindings/clock/qcom,gpucc.yaml index 81f6a9dc..ecf3cd6a 100644 --- a/bindings/clock/qcom,gpucc.yaml +++ b/bindings/clock/qcom,gpucc.yaml @@ -25,6 +25,7 @@ description: | dt-bindings/clock/qcom,gpucc-pineapple.h dt-bindings/clock/qcom,gpucc-sun.h dt-bindings/clock/qcom,gpucc-parrot.h + dt-bindings/clock/qcom,gpucc-monaco.h properties: compatible: @@ -41,6 +42,7 @@ properties: - qcom,pineapple-gpucc - qcom,sun-gpucc - qcom,parrot-gpucc + - qcom,monaco-gpucc clocks: items: diff --git a/bindings/clock/qcom,rpmcc.yaml b/bindings/clock/qcom,rpmcc.yaml index 2a95bf86..0bac78a7 100644 --- a/bindings/clock/qcom,rpmcc.yaml +++ b/bindings/clock/qcom,rpmcc.yaml @@ -45,6 +45,9 @@ properties: - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 - qcom,rpmcc-sm6375 + - qcom,rpmcc-holi + - qcom,rpmcc-khaje + - qcom,rpmcc-monaco - const: qcom,rpmcc '#clock-cells': From 18c5b67de5db54bcd5eae3ced92ccc2d13978634 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 16 May 2024 23:36:09 +0800 Subject: [PATCH 42/59] ARM: dts: msm: Use reserved memory instead of CMA Use reserved memory instead of CMA for memdump node. The dump entries are divided into two groups, one is static_dump, entries in this group are enabled by default during startup. dynamic_dump is the other group, entries in this group can be enabled/disabled after startup and disabled on perf build. Change-Id: I4f40cc29e2920cd0b2dd6b6b7285a770f1b39b3e Signed-off-by: Yuanfang Zhang --- qcom/sun-debug.dtsi | 544 +++++++++++++++++++++++--------------------- 1 file changed, 281 insertions(+), 263 deletions(-) diff --git a/qcom/sun-debug.dtsi b/qcom/sun-debug.dtsi index 822e5e5f..5d4d91d3 100644 --- a/qcom/sun-debug.dtsi +++ b/qcom/sun-debug.dtsi @@ -10,12 +10,9 @@ #size-cells = <2>; ranges; - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; + dump_mem: dump_mem_region { alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x5800000>; + size = <0x0 0x5a00000>; }; }; @@ -610,289 +607,310 @@ compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; - c0_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x0>; + static_dump { + qcom,static-mem-dump; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + etf_slpi { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf3>; + }; + + etfslpi_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x103>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + + scandump_smmu { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x220>; + }; + + scandump_gpu { + qcom,dump-size = <0x300000>; + qcom,dump-id = <0x221>; + }; + + spr_cpu0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f0>; + }; + + spr_cpu1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f1>; + }; + + spr_cpu2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f2>; + }; + + spr_cpu3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f3>; + }; + + spr_cpu4 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f4>; + }; + + spr_cpu5 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f5>; + }; + + spr_cpu6 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f6>; + }; + + spr_cpu7 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f7>; + }; + + cpuss_reg { + qcom,dump-size = <0xa00000>; + qcom,dump-id = <0xef>; + }; }; - c100_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x1>; - }; + dynamic_mem_dump { + qcom,dynamic-mem-dump; - c200_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x2>; - }; + cpuss_cpu { + cpuss_cpu0 { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x280>; + }; - c300_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x3>; - }; + cpuss_cpu1 { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x281>; + }; - c400_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x4>; - }; + cpuss_cpu2 { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x282>; + }; - c500_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x5>; - }; + cpuss_cpu3 { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x283>; + }; - c600_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x6>; - }; + cpuss_cpu4 { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x284>; + }; - c700_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x7>; - }; + cpuss_cpu5 { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x285>; + }; - cpuss_cpu0 { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x280>; - }; + cpuss_cpu6 { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x286>; + }; - cpuss_cpu1 { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x281>; - }; + cpuss_cpu7 { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x287>; + }; + }; - cpuss_cpu2 { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x282>; - }; + cpuss_cluster { + cpuss_cluster0 { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x270>; + }; - cpuss_cpu3 { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x283>; - }; + cpuss_cluster1 { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x271>; + }; + }; - cpuss_cpu4 { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x284>; - }; + cpucp { + cpucp { + qcom,dump-size = <0x80000>; + qcom,dump-id = <0xf5>; + }; + }; - cpuss_cpu5 { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x285>; - }; + apps_scandump { + scandump_apps { + qcom,dump-size = <0x380000>; + qcom,dump-id = <0x130>; + }; + }; - cpuss_cpu6 { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x286>; - }; + cpu_cache { + cache_cpu0 { + qcom,dump-size = <0x2aa000>; + qcom,dump-id = <0x230>; + }; - cpuss_cpu7 { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x287>; - }; + cache_cpu1 { + qcom,dump-size = <0x2aa000>; + qcom,dump-id = <0x231>; + }; - cpuss_cluster0 { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x270>; - }; + cache_cpu2 { + qcom,dump-size = <0x2aa000>; + qcom,dump-id = <0x232>; + }; - cpuss_cluster1 { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x271>; - }; + cache_cpu3 { + qcom,dump-size = <0x2aa000>; + qcom,dump-id = <0x233>; + }; - cpucp { - qcom,dump-size = <0x80000>; - qcom,dump-id = <0xf5>; - }; + cache_cpu4 { + qcom,dump-size = <0x2aa000>; + qcom,dump-id = <0x234>; + }; - scandump_apps { - qcom,dump-size = <0x380000>; - qcom,dump-id = <0x130>; - }; + cache_cpu5 { + qcom,dump-size = <0x2aa000>; + qcom,dump-id = <0x235>; + }; - cache_cpu0 { - qcom,dump-size = <0x2aa000>; - qcom,dump-id = <0x230>; - }; + cache_cpu6 { + qcom,dump-size = <0x2aa000>; + qcom,dump-id = <0x236>; + }; - cache_cpu1 { - qcom,dump-size = <0x2aa000>; - qcom,dump-id = <0x231>; - }; + cache_cpu7 { + qcom,dump-size = <0x2aa000>; + qcom,dump-id = <0x237>; + }; + }; - cache_cpu2 { - qcom,dump-size = <0x2aa000>; - qcom,dump-id = <0x232>; - }; + cluster_cache { + cl_cache0 { + qcom,dump-size = <0x1400000>; + qcom,dump-id = <0x240>; + }; - cache_cpu3 { - qcom,dump-size = <0x2aa000>; - qcom,dump-id = <0x233>; - }; + cl_cache1 { + qcom,dump-size = <0x1400000>; + qcom,dump-id = <0x241>; + }; - cache_cpu4 { - qcom,dump-size = <0x2aa000>; - qcom,dump-id = <0x234>; - }; - - cache_cpu5 { - qcom,dump-size = <0x2aa000>; - qcom,dump-id = <0x235>; - }; - - cache_cpu6 { - qcom,dump-size = <0x2aa000>; - qcom,dump-id = <0x236>; - }; - - cache_cpu7 { - qcom,dump-size = <0x2aa000>; - qcom,dump-id = <0x237>; - }; - - cpuss_reg { - qcom,dump-size = <0xa00000>; - qcom,dump-id = <0xef>; - }; - - spr_cpu0 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f0>; - }; - - spr_cpu1 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f1>; - }; - - spr_cpu2 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f2>; - }; - - spr_cpu3 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f3>; - }; - - spr_cpu4 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f4>; - }; - - spr_cpu5 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f5>; - }; - - spr_cpu6 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f6>; - }; - - spr_cpu7 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f7>; - }; - - cl_cache0 { - qcom,dump-size = <0x1400000>; - qcom,dump-id = <0x240>; - }; - - cl_cache1 { - qcom,dump-size = <0x1400000>; - qcom,dump-id = <0x241>; - }; - - rpmh { - qcom,dump-size = <0x400000>; - qcom,dump-id = <0xec>; - }; - - rpm_sw { - qcom,dump-size = <0x28000>; - qcom,dump-id = <0xea>; - }; - - pmic { - qcom,dump-size = <0x200000>; - qcom,dump-id = <0xe4>; - }; - - fcm { - qcom,dump-size = <0x8400>; - qcom,dump-id = <0xee>; - }; - - etf_swao { - qcom,dump-size = <0x10000>; - qcom,dump-id = <0xf1>; - }; - - etr_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x100>; - }; - - etfswao_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x102>; - }; - - etr1_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x105>; - }; - - misc_data { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0xe8>; - }; - - etf_slpi { - qcom,dump-size = <0x4000>; - qcom,dump-id = <0xf3>; - }; - - etfslpi_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x103>; - }; - - etf_lpass { - qcom,dump-size = <0x4000>; - qcom,dump-id = <0xf4>; - }; - - etflpass_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x104>; - }; - - osm_reg { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x163>; - }; - - pcu_reg { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x164>; - }; - - fsm_data { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x165>; - }; - - scandump_smmu { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x220>; - }; - - scandump_gpu { - qcom,dump-size = <0x300000>; - qcom,dump-id = <0x221>; + }; }; }; }; From 10e5f31ee5ffb3053abb74ae68c8a7d81f3e9d0b Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Mon, 3 Jun 2024 13:58:25 +0800 Subject: [PATCH 43/59] ARM: dts: msm: move spr/cpuss_reg to dynamic dump Move spr/cpuss_reg dump entry to dynamic dump. Change-Id: I9cb30827a86d6d03ed6eb14ecf6cf9b3b059ea7b Signed-off-by: Yuanfang Zhang --- qcom/sun-debug.dtsi | 94 +++++++++++++++++++++++---------------------- 1 file changed, 49 insertions(+), 45 deletions(-) diff --git a/qcom/sun-debug.dtsi b/qcom/sun-debug.dtsi index 5d4d91d3..1c1a8fb2 100644 --- a/qcom/sun-debug.dtsi +++ b/qcom/sun-debug.dtsi @@ -739,56 +739,60 @@ qcom,dump-size = <0x300000>; qcom,dump-id = <0x221>; }; - - spr_cpu0 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f0>; - }; - - spr_cpu1 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f1>; - }; - - spr_cpu2 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f2>; - }; - - spr_cpu3 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f3>; - }; - - spr_cpu4 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f4>; - }; - - spr_cpu5 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f5>; - }; - - spr_cpu6 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f6>; - }; - - spr_cpu7 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f7>; - }; - - cpuss_reg { - qcom,dump-size = <0xa00000>; - qcom,dump-id = <0xef>; - }; }; dynamic_mem_dump { qcom,dynamic-mem-dump; + cpuss_reg { + cpuss_reg { + qcom,dump-size = <0xa00000>; + qcom,dump-id = <0xef>; + }; + }; + + spr { + spr_cpu0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f0>; + }; + + spr_cpu1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f1>; + }; + + spr_cpu2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f2>; + }; + + spr_cpu3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f3>; + }; + + spr_cpu4 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f4>; + }; + + spr_cpu5 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f5>; + }; + + spr_cpu6 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f6>; + }; + + spr_cpu7 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f7>; + }; + }; + cpuss_cpu { cpuss_cpu0 { qcom,dump-size = <0x40000>; From cf4836e995a735258e24fc53403220cdd0aa1606 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Mon, 3 Jun 2024 15:13:25 -0700 Subject: [PATCH 44/59] ARM: dts: msm: Remove SLV_ADDR_SPACE_SIZE register value from dt No need to configure the SLV_ADDR_SPACE_SIZE register value from devicetree node because the PCIe driver is taking care of configure it to the maximum possible size. Change-Id: I925b51a913be06d14c62ce65a954cdb0d96a814f Signed-off-by: Prudhvi Yarlagadda --- qcom/sun-pcie.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/sun-pcie.dtsi b/qcom/sun-pcie.dtsi index 523685eb..e2f83bcc 100644 --- a/qcom/sun-pcie.dtsi +++ b/qcom/sun-pcie.dtsi @@ -84,7 +84,6 @@ qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,l1-2-th-scale = <2>; qcom,l1-2-th-value = <150>; - qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; From e7fc8e39ef555e1dcf02733379134a5368083105 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 21 May 2024 17:07:36 +0800 Subject: [PATCH 45/59] ARM: dts: msm: add version property for Trace Noc add qcom,interconnect-trace-noc/qcom,trace-noc-v2 property for Trace Noc on Sun. Change-Id: I8b990102722565cd9c3ccf4590dd66faa6e3d086 Signed-off-by: Yuanfang Zhang --- qcom/sun-coresight.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sun-coresight.dtsi b/qcom/sun-coresight.dtsi index 1f7e0056..b2f8f0c5 100644 --- a/qcom/sun-coresight.dtsi +++ b/qcom/sun-coresight.dtsi @@ -613,6 +613,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + qcom,interconnect-trace-noc; in-ports { #address-cells = <1>; @@ -1480,6 +1481,7 @@ status = "disabled"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + qcom,trace-noc-v2; in-ports { #address-cells = <1>; @@ -3711,6 +3713,7 @@ reg-names = "traceNoc-base"; coresight-name = "coresight-tracenoc-ddr"; + qcom,interconnect-trace-noc; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3945,6 +3948,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + qcom,interconnect-trace-noc; in-ports { #address-cells = <1>; @@ -3973,6 +3977,7 @@ compatible = "arm,coresight-dummy-source"; coresight-name = "coresight-lpass-stm"; trace-name = "lpass-stm"; + atid = <25>; out-ports { port@0 { @@ -4481,6 +4486,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + qcom,trace-noc-v2; in-ports { #address-cells = <1>; From 5c5c310e87f35cca1008a47c145131cba796aab3 Mon Sep 17 00:00:00 2001 From: kamasali Satyanarayan Date: Tue, 28 May 2024 16:58:41 +0530 Subject: [PATCH 46/59] ARM: dts: msm: Add max-cpu for parrot Add "qcom,max-cpus" DT to specify the maximum number of CPUs the SoC supports. Change-Id: If7289eeac6732f354c31abd69b4e4fabd549c834 Signed-off-by: kamasali Satyanarayan --- qcom/parrot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 72be3bec..4b955056 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -1965,6 +1965,7 @@ qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,max-cpus = <8>; status = "disabled"; qos0 { From e66ef39276277224e6f47df3654deaee276250cd Mon Sep 17 00:00:00 2001 From: quic_swarbu Date: Tue, 4 Jun 2024 18:05:26 +0530 Subject: [PATCH 47/59] dt-bindings: Add novatek touch vendor name Add novatek vendor name in vendor prefix list. Change-Id: I6bf7b154f7d834fdfce1deac80f43ac7184da296 Signed-off-by: quic_swarbu --- bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/vendor-prefixes.yaml b/bindings/vendor-prefixes.yaml index cbe12da6..80e86fea 100644 --- a/bindings/vendor-prefixes.yaml +++ b/bindings/vendor-prefixes.yaml @@ -464,6 +464,8 @@ patternProperties: description: Firefly "^focaltech,.*": description: FocalTech Systems Co.,Ltd + "^novatek,.*": + description: NOVATEK Microelectronics Corporation "^forlinx,.*": description: Baoding Forlinx Embedded Technology Co., Ltd. "^frida,.*": From 3818b3ed8ba2b088277c14d13c42e17255da0133 Mon Sep 17 00:00:00 2001 From: Amirreza Zarrabi Date: Tue, 9 Apr 2024 18:09:54 -0700 Subject: [PATCH 48/59] ARM: dts: msm: enable memory object extension for Sun TUIVM Add DT entry to enable the memory onject support for si-core. Change-Id: Ie2551143a14773ac5cdd9196c39832f8579abd5d Signed-off-by: Amirreza Zarrabi --- qcom/sun-vm.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index 4518418d..95f431f5 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -651,6 +651,10 @@ compatible = "qcom,smcinvoke"; }; + qcom_mem_object { + compatible = "qcom,mem-object"; + }; + qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; qcom,custom-bridge-size = <64>; From 2b0ebab88940ada64d35ba4272852db79e3a5413 Mon Sep 17 00:00:00 2001 From: Jagadeesh Ponduru Date: Wed, 5 Jun 2024 10:08:21 +0530 Subject: [PATCH 49/59] ARM: dts: msm: Add smp2p ipa nodes for volcano Add the smp2p ipa device nodes to enable smp2p communication with remote processors. Change-Id: Ifc5232c05ff77d977b9af1dcd8ab1b4d17b4eb8c Signed-off-by: Pavan Kumar M Signed-off-by: Jagadeesh Ponduru --- qcom/parrot.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 165fbd8b..3b86b6d1 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -713,6 +713,17 @@ #interrupt-cells = <2>; }; + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; qcom,smp2p-adsp { From c4c533f4bd343185d3d2c80152d005b0b41cb650 Mon Sep 17 00:00:00 2001 From: Sarannya S Date: Thu, 18 Jan 2024 17:34:21 +0530 Subject: [PATCH 50/59] ARM: dts: msm: Remove master property from VM entry Remove the 'master' property from the VM devicetree entry. This property is not used anymore so as to handle any bootup order. Change-Id: I261f85a61b522f5b07a2e67d4669deccd3a2872d Signed-off-by: Sarannya S --- qcom/sun-vm.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index 95f431f5..b30e6da0 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -480,7 +480,6 @@ qmsgq-gunyah { compatible = "qcom,qmsgq-gh"; - qcom,master; msgq-label = <3>; }; From ecaad8e10a17de54a6ff40bcaa4b20c1ab9c2f73 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 5 Apr 2024 17:35:15 +0530 Subject: [PATCH 51/59] ARM: dts: msm: Update entry, exit latency and min residency for sun Update cluster low power mode entry, exit and minimum residency numbers. Change-Id: I059c9fdb3e646bd5e1acdb4153e5443be0d354a4 Signed-off-by: Maulik Shah --- qcom/sun.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 18647e7a..51449f47 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -244,18 +244,18 @@ MEDIUM_CLUSTER_PWR_DN: medium-cluster-cl5 { /* CL5 */ compatible = "domain-idle-state"; idle-state-name = "ret-pll-off"; - entry-latency-us = <1964>; - exit-latency-us = <1901>; - min-residency-us = <24511>; + entry-latency-us = <2150>; + exit-latency-us = <1983>; + min-residency-us = <9144>; arm,psci-suspend-param = <0x01000054>; }; LARGE_CLUSTER_PWR_DN: large-cluster-cl5 { /* CL5 */ compatible = "domain-idle-state"; idle-state-name = "ret-pll-off"; - entry-latency-us = <2124>; - exit-latency-us = <1967>; - min-residency-us = <36712>; + entry-latency-us = <2150>; + exit-latency-us = <1983>; + min-residency-us = <9144>; arm,psci-suspend-param = <0x01000054>; }; @@ -264,7 +264,7 @@ idle-state-name = "apps-pc"; entry-latency-us = <2800>; exit-latency-us = <4400>; - min-residency-us = <40000>; + min-residency-us = <10150>; arm,psci-suspend-param = <0x0200C354>; }; }; From 1dcffc73d8d278b2f5b2a486b9920668c1961cc7 Mon Sep 17 00:00:00 2001 From: Lynus Vaz Date: Mon, 3 Jun 2024 10:18:46 -0700 Subject: [PATCH 52/59] ARM: dts: msm: Add the gpu_speed_bin fuse entry on sun Add the gpu_speed_bin fuse entry on sun devices. Change-Id: I790d3456e7d7108a6ae5ec90fc791fde6b1eeab8 Signed-off-by: Lynus Vaz --- qcom/sun.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 18647e7a..fdbaa8ca 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3504,6 +3504,11 @@ read-only; ranges; + gpu_speed_bin: gpu_speed_bin@138 { + reg = <0x138 0x2>; + bits = <0 9>; + }; + ssip_config: ssip_config@13e { reg = <0x13e 0x2>; bits = <7 2>; From ac218ced9832b0f166d7e392d310425e6f314445 Mon Sep 17 00:00:00 2001 From: Ke Du Date: Thu, 30 May 2024 17:46:26 +0800 Subject: [PATCH 53/59] ARM: dts: msm: Add dependency of iommu node on USB driver Currently, wait_for_device_probe api added before dwc3_probe is called in core_init which is suppose to ensure that in case the child is getting teared down, the userspace doesn't get to write UDC and do gadget_start. However, wait_for_device_probe api makes sure that the driver wait until all probes are completed. Ideally, it wouldn't be a problem but in cases of other driver's probe fails, usb would be affected here even though usb isn't at fault. Fix this by making a dummy-dependency on smmu node since the original intention of the patch was to make sure if smmu driver was probed successfully, then only proceed for child driver's probe. Change-Id: Id05797f8dcd26783e3c0eab4facf4f4672790fe6 Signed-off-by: Udipto Goswami Signed-off-by: Ke Du --- qcom/monaco-usb.dtsi | 6 ++++++ qcom/parrot-usb.dtsi | 6 ++++++ qcom/pineapple-usb.dtsi | 8 +++++++- qcom/sun-usb.dtsi | 6 ++++++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/qcom/monaco-usb.dtsi b/qcom/monaco-usb.dtsi index 768028e8..b4f90a77 100644 --- a/qcom/monaco-usb.dtsi +++ b/qcom/monaco-usb.dtsi @@ -55,6 +55,12 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ + /* + * Establish dependency on smmu driver so that depopulate path of + * deferred probe doesn't run into existing bug in smmu driver. + */ + dummy-supply = <&apps_smmu>; + dwc3@4e00000 { compatible = "snps,dwc3"; reg = <0x4e00000 0xcd00>; diff --git a/qcom/parrot-usb.dtsi b/qcom/parrot-usb.dtsi index 3c70d4a7..93856c1f 100644 --- a/qcom/parrot-usb.dtsi +++ b/qcom/parrot-usb.dtsi @@ -53,6 +53,12 @@ <&aggre1_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>, <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>; + /* + * Establish dependency on smmu driver so that depopulate path of + * deferred probe doesn't run into existing bug in smmu driver. + */ + dummy-supply = <&apps_smmu>; + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0 0xa600000 0x0 0xd800>; diff --git a/qcom/pineapple-usb.dtsi b/qcom/pineapple-usb.dtsi index db18a668..5ce462a1 100644 --- a/qcom/pineapple-usb.dtsi +++ b/qcom/pineapple-usb.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -58,6 +58,12 @@ <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + /* + * Establish dependency on smmu driver so that depopulate path of + * deferred probe doesn't run into existing bug in smmu driver. + */ + dummy-supply = <&apps_smmu>; + dwc3@a600000 { compatible = "snps,dwc3"; reg = <0xa600000 0xd93c>; diff --git a/qcom/sun-usb.dtsi b/qcom/sun-usb.dtsi index 72b71966..2e4c642a 100644 --- a/qcom/sun-usb.dtsi +++ b/qcom/sun-usb.dtsi @@ -59,6 +59,12 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ + /* + * Establish dependency on smmu driver so that depopulate path of + * deferred probe doesn't run into existing bug in smmu driver. + */ + dummy-supply = <&apps_smmu>; + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0 0xa600000 0x0 0xd93c>; From c5abe4175556484c948fbfac54d0f6057899f5f3 Mon Sep 17 00:00:00 2001 From: Nageswara reddy Karnati Date: Thu, 6 Jun 2024 10:30:40 -0700 Subject: [PATCH 54/59] dt-bindings: Add dt binding for qrng Addition of dt binding compatible string for qring node. Change-Id: I875d10955ed7563b07ecc9b9d1980f8bbf0fe3c8 Signed-off-by: Nageswara reddy Karnati --- bindings/crypto/qcom,prng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/crypto/qcom,prng.yaml b/bindings/crypto/qcom,prng.yaml index 04ddcc0f..52b05c3f 100644 --- a/bindings/crypto/qcom,prng.yaml +++ b/bindings/crypto/qcom,prng.yaml @@ -15,6 +15,7 @@ properties: - enum: - qcom,prng # 8916 etc. - qcom,prng-ee # 8996 and later using EE + - qcom,msm-rng # parrot - items: - enum: - qcom,sm8450-trng From 0b093bd58219afad376225160ebb9e58deef2090 Mon Sep 17 00:00:00 2001 From: Piyush Pradeep Jain Date: Sat, 8 Jun 2024 16:12:49 +0530 Subject: [PATCH 55/59] ARM: dts: msm: Add entry for KMHal and DeviceID UID Add entry for KMHal and DeviceID UID in vm config consumed by RM to communicate with qtee service. Change-Id: I1fecedaa960c764d45e154d217c58abf71752125 Signed-off-by: Piyush Pradeep Jain --- qcom/sun-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index 4518418d..f9b9e906 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -95,7 +95,7 @@ vendor = "QTI"; image-name = "qcom,trustedvm"; qcom,pasid = <0x0 0x1c>; - qcom,qtee-config-info = "p=3,9,39,77,78,7C,8F,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;"; + qcom,qtee-config-info = "p=3,9,C,39,77,78,7C,8F,96,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;"; qcom,secdomain-ids = <45>; qcom,primary-vm-index = <0>; vm-uri = "vmuid/trusted-ui"; From 49b995da14ad65fdec85f9b81631905121c372e0 Mon Sep 17 00:00:00 2001 From: Nageswara reddy Karnati Date: Mon, 3 Jun 2024 04:34:00 -0700 Subject: [PATCH 56/59] ARM: dts: msm: parrot: Add qrng device node Add dt support for qrng for Parrot SOC. :compile and tested the code on target using test binary. Change-Id: I4ea707cc9e2d8d58aa16530a2c6a2e47670e58c5 Signed-off-by: Nageswara reddy Karnati --- qcom/parrot.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index abaa1cb3..24fa87dd 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -1845,6 +1845,13 @@ }; }; + qcom_rng: qrng@10c3000 { + compatible = "qcom,msm-rng"; + reg = <0x10c3000 0x1000>; + qcom,no-qrng-config; + qcom,no-clock-support; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe10>; reg-names = "phy_mem"; From 1b78f8027a4fee53f515191b1177871019e9c19c Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Mon, 4 Mar 2024 13:52:23 +0530 Subject: [PATCH 57/59] ARM: dts: msm: Add initial device tree for ravelin Add initial device tree support for ravelin target. This is a snapshot of dtsi files as of KP.1.0 'commit <370d8eab7cc6> ("Merge "ARM: dts: qcom: Disable cnss-kiwi SOL on anorak platform"")'. Modified as per compilation and bootup. Change-Id: Icb9a6e67879c68dbf894d1713fa2837882b9f00c Signed-off-by: Swetha Chikkaboraiah --- qcom/Makefile | 20 + qcom/ipcc-test-ravelin.dtsi | 10 + qcom/msm-arm-smmu-ravelin.dtsi | 379 ++ qcom/platform_map.bzl | 11 + qcom/pmi632.dtsi | 532 +++ qcom/ravelin-4gb.dts | 14 + qcom/ravelin-4gb.dtsi | 16 + qcom/ravelin-atp-overlay.dts | 16 + qcom/ravelin-atp.dts | 15 + qcom/ravelin-atp.dtsi | 144 + qcom/ravelin-coresight.dtsi | 3727 +++++++++++++++++ qcom/ravelin-debug.dtsi | 1584 +++++++ qcom/ravelin-dma-heaps.dtsi | 43 + qcom/ravelin-idp-overlay.dts | 16 + ...ravelin-idp-wcn3950-amoled-rcm-overlay.dts | 16 + qcom/ravelin-idp-wcn3950-amoled-rcm.dts | 15 + qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi | 47 + qcom/ravelin-idp-wcn3988-4gb-overlay.dts | 16 + qcom/ravelin-idp-wcn3988-4gb.dts | 15 + qcom/ravelin-idp-wcn3988-4gb.dtsi | 6 + qcom/ravelin-idp.dts | 15 + qcom/ravelin-idp.dtsi | 193 + qcom/ravelin-low-memory.dtsi | 42 + qcom/ravelin-msm-rdbg.dtsi | 19 + qcom/ravelin-pcie.dtsi | 277 ++ qcom/ravelin-pinctrl.dtsi | 1403 +++++++ qcom/ravelin-pm7250b.dtsi | 355 ++ qcom/ravelin-pmi632.dtsi | 326 ++ qcom/ravelin-pmic-overlay.dtsi | 663 +++ qcom/ravelin-qcx6438.dtsi | 62 + qcom/ravelin-qrd-4gb-overlay.dts | 16 + qcom/ravelin-qrd-4gb.dts | 15 + qcom/ravelin-qrd-4gb.dtsi | 6 + qcom/ravelin-qrd-overlay.dts | 17 + qcom/ravelin-qrd.dts | 16 + qcom/ravelin-qrd.dtsi | 164 + qcom/ravelin-qupv3.dtsi | 528 +++ qcom/ravelin-regulators.dtsi | 814 ++++ qcom/ravelin-reserved-memory.dtsi | 174 + qcom/ravelin-rumi-overlay.dts | 17 + qcom/ravelin-rumi.dts | 17 + qcom/ravelin-rumi.dtsi | 243 ++ qcom/ravelin-stub-regulator.dtsi | 429 ++ qcom/ravelin-thermal-modem.dtsi | 404 ++ qcom/ravelin-thermal-overlay.dtsi | 62 + qcom/ravelin-thermal.dtsi | 951 +++++ qcom/ravelin-usb.dtsi | 325 ++ qcom/ravelin-wcn6750.dtsi | 117 + qcom/ravelin.dts | 15 + qcom/ravelin.dtsi | 2569 ++++++++++++ qcom/ravelinp-4gb.dts | 14 + qcom/ravelinp-4gb.dtsi | 12 + qcom/ravelinp-atp.dts | 15 + qcom/ravelinp-atp.dtsi | 6 + qcom/ravelinp-idp-wcn3950-amoled-rcm.dts | 15 + qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi | 6 + qcom/ravelinp-idp-wcn3988-4gb.dts | 15 + qcom/ravelinp-idp-wcn3988-4gb.dtsi | 7 + qcom/ravelinp-idp.dts | 15 + qcom/ravelinp-idp.dtsi | 6 + qcom/ravelinp-qrd-4gb.dts | 15 + qcom/ravelinp-qrd-4gb.dtsi | 6 + qcom/ravelinp-qrd.dts | 16 + qcom/ravelinp-qrd.dtsi | 6 + qcom/ravelinp.dts | 15 + qcom/ravelinp.dtsi | 11 + 66 files changed, 17076 insertions(+) create mode 100644 qcom/ipcc-test-ravelin.dtsi create mode 100644 qcom/msm-arm-smmu-ravelin.dtsi create mode 100644 qcom/pmi632.dtsi create mode 100644 qcom/ravelin-4gb.dts create mode 100644 qcom/ravelin-4gb.dtsi create mode 100644 qcom/ravelin-atp-overlay.dts create mode 100644 qcom/ravelin-atp.dts create mode 100644 qcom/ravelin-atp.dtsi create mode 100644 qcom/ravelin-coresight.dtsi create mode 100644 qcom/ravelin-debug.dtsi create mode 100644 qcom/ravelin-dma-heaps.dtsi create mode 100644 qcom/ravelin-idp-overlay.dts create mode 100644 qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts create mode 100644 qcom/ravelin-idp-wcn3950-amoled-rcm.dts create mode 100644 qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi create mode 100644 qcom/ravelin-idp-wcn3988-4gb-overlay.dts create mode 100644 qcom/ravelin-idp-wcn3988-4gb.dts create mode 100644 qcom/ravelin-idp-wcn3988-4gb.dtsi create mode 100644 qcom/ravelin-idp.dts create mode 100644 qcom/ravelin-idp.dtsi create mode 100644 qcom/ravelin-low-memory.dtsi create mode 100644 qcom/ravelin-msm-rdbg.dtsi create mode 100644 qcom/ravelin-pcie.dtsi create mode 100644 qcom/ravelin-pinctrl.dtsi create mode 100644 qcom/ravelin-pm7250b.dtsi create mode 100644 qcom/ravelin-pmi632.dtsi create mode 100644 qcom/ravelin-pmic-overlay.dtsi create mode 100644 qcom/ravelin-qcx6438.dtsi create mode 100644 qcom/ravelin-qrd-4gb-overlay.dts create mode 100644 qcom/ravelin-qrd-4gb.dts create mode 100644 qcom/ravelin-qrd-4gb.dtsi create mode 100644 qcom/ravelin-qrd-overlay.dts create mode 100644 qcom/ravelin-qrd.dts create mode 100644 qcom/ravelin-qrd.dtsi create mode 100644 qcom/ravelin-qupv3.dtsi create mode 100644 qcom/ravelin-regulators.dtsi create mode 100644 qcom/ravelin-reserved-memory.dtsi create mode 100644 qcom/ravelin-rumi-overlay.dts create mode 100644 qcom/ravelin-rumi.dts create mode 100644 qcom/ravelin-rumi.dtsi create mode 100644 qcom/ravelin-stub-regulator.dtsi create mode 100644 qcom/ravelin-thermal-modem.dtsi create mode 100644 qcom/ravelin-thermal-overlay.dtsi create mode 100644 qcom/ravelin-thermal.dtsi create mode 100644 qcom/ravelin-usb.dtsi create mode 100644 qcom/ravelin-wcn6750.dtsi create mode 100644 qcom/ravelin.dts create mode 100644 qcom/ravelin.dtsi create mode 100644 qcom/ravelinp-4gb.dts create mode 100644 qcom/ravelinp-4gb.dtsi create mode 100644 qcom/ravelinp-atp.dts create mode 100644 qcom/ravelinp-atp.dtsi create mode 100644 qcom/ravelinp-idp-wcn3950-amoled-rcm.dts create mode 100644 qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi create mode 100644 qcom/ravelinp-idp-wcn3988-4gb.dts create mode 100644 qcom/ravelinp-idp-wcn3988-4gb.dtsi create mode 100644 qcom/ravelinp-idp.dts create mode 100644 qcom/ravelinp-idp.dtsi create mode 100644 qcom/ravelinp-qrd-4gb.dts create mode 100644 qcom/ravelinp-qrd-4gb.dtsi create mode 100644 qcom/ravelinp-qrd.dts create mode 100644 qcom/ravelinp-qrd.dtsi create mode 100644 qcom/ravelinp.dts create mode 100644 qcom/ravelinp.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 242401a7..ebe62f22 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -125,6 +125,26 @@ parrot-dtb-$(CONFIG_ARCH_PARROT) += \ parrot-overlays-dtb-$(CONFIG_ARCH_PARROT) += $(PARROT_BOARDS) $(PARROT_BASE_DTB) $(PARROT_4GB_BOARDS) $(PARROT_4GB_BASE_DTB) dtb-y += $(parrot-dtb-y) +RAVELIN_BASE_DTB += ravelin.dtb ravelinp.dtb +RAVELIN_4GB_BASE_DTB += ravelin-4gb.dtb ravelinp-4gb.dtb + +RAVELIN_BOARDS += \ + ravelin-rumi-overlay.dtbo \ + ravelin-atp-overlay.dtbo \ + ravelin-idp-overlay.dtbo \ + ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo \ + ravelin-qrd-overlay.dtbo \ + +RAVELIN_4GB_BOARDS += \ + ravelin-idp-wcn3988-4gb-overlay.dtbo \ + ravelin-qrd-4gb-overlay.dtbo \ + +parrot-dtb-$(CONFIG_ARCH_RAVELIN) += \ + $(call add-overlays, $(RAVELIN_BOARDS),$(RAVELIN_BASE_DTB)) \ + $(call add-overlays, $(RAVELIN_4GB_BOARDS),$(RAVELIN_4GB_BASE_DTB)) +parrot-overlays-dtb-$(CONFIG_ARCH_RAVELIN) += $(RAVELIN_BOARDS) $(RAVELIN_BASE_DTB) $(RAVELIN_4GB_BOARDS) $(RAVELIN_4GB_BASE_DTB) +dtb-y += $(parrot-dtb-y) + endif ifeq ($(CONFIG_ARCH_PINEAPPLE), y) diff --git a/qcom/ipcc-test-ravelin.dtsi b/qcom/ipcc-test-ravelin.dtsi new file mode 100644 index 00000000..bf439c38 --- /dev/null +++ b/qcom/ipcc-test-ravelin.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipcc-test.dtsi" + +&soc { + /delete-node/ ipcc-self-ping-slpi; +}; diff --git a/qcom/msm-arm-smmu-ravelin.dtsi b/qcom/msm-arm-smmu-ravelin.dtsi new file mode 100644 index 00000000..6ebf4e64 --- /dev/null +++ b/qcom/msm-arm-smmu-ravelin.dtsi @@ -0,0 +1,379 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x10000>, + <0x3dc2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + qcom,num-context-banks-override = <0x5>; + qcom,num-smr-override = <0x7>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x1FFF 0x32B>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = + "gpu_cc_cx_gmu", + "gpu_cc_hub_cx_int", + "gpu_cc_hlos1_vote_gpu_smmu", + "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@3dc5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3dc5000 0x1000>, + <0x3dc2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@3dc9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3dc9000 0x1000>, + <0x3dc2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x151e2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + qcom,num-context-banks-override = <0x52>; + qcom,num-smr-override = <0x85>; + qcom,handoff-smrs = <0x800 0x402>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + qcom,actlr = + /* For video clients, +3 PF */ + <0x1980 0x3F 0x103>, + /* Display and camera clients, +0 PF */ + <0x1900 0x3F 0x1>, + <0x1800 0xFF 0x1>, + <0x800 0x7FF 0x1>; + + clocks = <&gcc GCC_HLOS1_VOTE_MMU_TCU_CLK>; + clock-names = + "gcc_hlos1_vote_mmu_tcu_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_TCU>; + qcom,active-only; + + anoc_1_tbu: anoc_1_tbu@151e5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e5000 0x1000>, + <0x151e2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK>; + clock-names = + "gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_IMEM>; + qcom,active-only; + }; + + anoc_2_tbu: anoc_2_tbu@151e9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e9000 0x1000>, + <0x151e2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK>; + clock-names = + "gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &cnoc3 SLAVE_IMEM>; + qcom,active-only; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@151ed000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151ed000 0x1000>, + <0x151e2210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <32>; + qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK>; + clock-names = + "gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk"; + interconnects = <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@151f1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f1000 0x1000>, + <0x151e2218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <32>; + qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK>; + clock-names = + "gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk"; + interconnects = <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + lpass_tbu: lpass_tbu@151f5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f5000 0x1000>, + <0x151e2220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + qcom,iova-width = <32>; + qcom,micro-idle; + clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK>; + clock-names = + "gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk"; + interconnects = <&lpass_ag_noc MASTER_LPASS_PROC + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + pcie_tbu: pcie_tbu@151f9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f9000 0x1000>, + <0x151e2228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + qcom,iova-width = <36>; + qcom,micro-idle; + clocks = <&gcc GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK>; + clock-names = + "gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk"; + interconnects = <&pcie_anoc MASTER_PCIE_0 + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + + sf_0_tbu: sf_0_tbu@151fd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151fd000 0x1000>, + <0x151e2230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <32>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>; + qcom,micro-idle; + clocks = <&gcc GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK>; + clock-names = + "gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk"; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + qcom,active-only; + }; + }; + + dma_dev@0x0 { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + iommu_test_device { + compatible = "qcom,iommu-debug-test"; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "atomic"; + }; + + usecase4_apps_coherent { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e1 0>; + dma-coherent; + }; + + usecase5_kgsl_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x400>; + }; + + usecase6_kgsl_coherent { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x407 0x400>; + dma-coherent; + }; + + usecase7_apps_secure { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x7e0 0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + }; + }; +}; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 77dfc563..f70d7b36 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -191,6 +191,10 @@ _platform_map = { {"name": "parrot-sg.dtb"}, {"name": "parrotp-sg.dtb"}, {"name": "parrot-4gb.dtb"}, + {"name": "ravelin.dtb"}, + {"name": "ravelinp.dtb"}, + {"name": "ravelin-4gb.dtb"}, + {"name": "ravelinp-4gb.dtb"}, ], "dtbo_list": [ # keep sorted @@ -214,6 +218,13 @@ _platform_map = { {"name": "parrot-idp-wcn6750-amoled-4gb-overlay.dtbo"}, {"name": "parrot-qrd-4gb-overlay.dtbo"}, {"name": "parrot-qrd-wcn6750-4gb-overlay.dtbo"}, + {"name": "ravelin-rumi-overlay.dtbo"}, + {"name": "ravelin-atp-overlay.dtbo"}, + {"name": "ravelin-idp-overlay.dtbo"}, + {"name": "ravelin-idp-wcn3950-amoled-rcm-overlay.dtbo"}, + {"name": "ravelin-qrd-overlay.dtbo"}, + {"name": "ravelin-idp-wcn3988-4gb-overlay.dtbo"}, + {"name": "ravelin-qrd-4gb-overlay.dtbo"}, ], }, } diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi new file mode 100644 index 00000000..625aedac --- /dev/null +++ b/qcom/pmi632.dtsi @@ -0,0 +1,532 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pmi632_2: qcom,pmi632@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi632_pon: qcom,power-on@800 { + reg = <0x800>; + }; + + pmi632_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5-lite"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + chg_temp { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k { + reg = ; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k { + reg = ; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_id { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + i_parallel { + reg = ; + label = "i_parallel"; + qcom,pre-scaling = <1 1>; + }; + }; + + pmi632_adc_tm: adc_tm@3500 { + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "threshold"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pmi632_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmi632_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + qcom,schgm-flash@a600 { + reg = <0xa600>; + interrupts = <0x2 0xa6 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0xa6 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "flash-state-change", + "ilim2-s2"; + qcom,flash-disable-soc = <10>; + }; + + pmi632_gpios: pinctrl@c000 { + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmi632_pbs_client3: qcom,pbs@7400 { + compatible = "qcom,qpnp-pbs"; + reg = <0x7400>; + }; + + pmi632_sdam7: qcom,sdam@b600 { + compatible = "qcom,spmi-sdam"; + reg = <0xb600>; + }; + + pmi632_bcl: bcl@3d00 { + compatible = "qcom,bcl-v5"; + reg = <0x3d00>; + interrupts = <0x2 0x3d 0x0 IRQ_TYPE_NONE>, + <0x2 0x3d 0x1 IRQ_TYPE_NONE>, + <0x2 0x3d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,ibat-use-qg-adc-5a; + #thermal-sensor-cells = <1>; + }; + + bcl_soc: bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + }; + + pmi632_3: qcom,pmi632@3 { + compatible ="qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi632_vib: qcom,vibrator@5700 { + reg = <0x5700>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + + pmi632_pwm: qcom,pwms@b300 { + reg = <0xb300>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <5>; + nvmem-names = "ppg_sdam"; + nvmem = <&pmi632_sdam7>; + qcom,pbs-client = <&pmi632_pbs_client3>; + qcom,lut-sdam-base = <0x80>; + qcom,lut-patterns = <0 0 0 14 28 42 56 70 84 100 + 100 84 70 56 42 28 14 0 0 0>; + lpg@1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x48>; + }; + + lpg@2 { + qcom,lpg-chan-id = <2>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x56>; + }; + + lpg@3 { + qcom,lpg-chan-id = <3>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x64>; + }; + }; + + pmi632_rgb: qcom,leds@d000 { + reg = <0xd000>; + red { + label = "red"; + pwms = <&pmi632_pwm 0 1000000>; + led-sources = <0>; + linux,default-trigger = "timer"; + }; + + green { + label = "green"; + pwms = <&pmi632_pwm 1 1000000>; + led-sources = <1>; + linux,default-trigger = "timer"; + }; + + blue { + label = "blue"; + pwms = <&pmi632_pwm 2 1000000>; + led-sources = <2>; + linux,default-trigger = "timer"; + }; + }; + + pmi632_lcdb: qpnp-lcdb@ec00 { + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xec00>; + interrupts = <0x3 0xec 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq"; + + qcom,voltage-step-ramp; + + lcdb_ldo_vreg: ldo { + label = "ldo"; + regulator-name = "lcdb_ldo"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_ncp_vreg: ncp { + label = "ncp"; + regulator-name = "lcdb_ncp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_bst_vreg: bst { + label = "bst"; + regulator-name = "lcdb_bst"; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <6275000>; + }; + }; + + flash_led: qcom,leds@d300 { + reg = <0xd300>; + label = "flash"; + interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + + pmi632_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pmi632_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <2>; + qcom,default-led-trigger = "switch1_trigger"; + }; + + }; + + }; +}; + +&thermal_zones { + pmi632-tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmi632_tz>; + + trips { + pmi632_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmi632_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pmi632-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_bcl 0>; + + trips { + ibat_lvl0: ibat-lvl0 { + temperature = <4000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmi632-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_bcl 1>; + + trips { + ibat_lvl1: ibat-lvl1 { + temperature = <5000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmi632-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmi632_bcl 5>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pmi632-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmi632_bcl 6>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pmi632-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmi632_bcl 7>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&bcl_soc>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + socd_trip:socd-trip { + temperature = <90>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/ravelin-4gb.dts b/qcom/ravelin-4gb.dts new file mode 100644 index 00000000..73105488 --- /dev/null +++ b/qcom/ravelin-4gb.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin 4Gb SoC"; + compatible = "qcom,ravelin"; + qcom,board-id = <0 0x600>; +}; diff --git a/qcom/ravelin-4gb.dtsi b/qcom/ravelin-4gb.dtsi new file mode 100644 index 00000000..778de904 --- /dev/null +++ b/qcom/ravelin-4gb.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin.dtsi" +#include "ravelin-low-memory.dtsi" +/ { +}; + +&mem_client_3_size { + qcom,peripheral-size = <0x200000>; +}; + +&soc { +}; diff --git a/qcom/ravelin-atp-overlay.dts b/qcom/ravelin-atp-overlay.dts new file mode 100644 index 00000000..7ea7d64b --- /dev/null +++ b/qcom/ravelin-atp-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin ATP"; + compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; + qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/qcom/ravelin-atp.dts b/qcom/ravelin-atp.dts new file mode 100644 index 00000000..78d603ee --- /dev/null +++ b/qcom/ravelin-atp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin.dtsi" +#include "ravelin-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin ATP"; + compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/ravelin-atp.dtsi b/qcom/ravelin-atp.dtsi new file mode 100644 index 00000000..f1aa4a4f --- /dev/null +++ b/qcom/ravelin-atp.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-pmic-overlay.dtsi" +#include "ravelin-pm7250b.dtsi" +#include "ravelin-thermal-overlay.dtsi" + +&soc { +}; + +&qupv3_se1_spi { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + qcom,spi-touch-active = "focaltech,fts_ts"; + + focaltech@0 { + reg = <0x0>; + spi-max-frequency = <6000000>; + interrupt-parent = <&tlmm>; + interrupts = <91 0x2008>; + focaltech,reset-gpio = <&tlmm 90 0x00>; + focaltech,irq-gpio = <&tlmm 91 0x2008>; + focaltech,display-coords = <0 0 1080 2340>; + focaltech,max-touch-number = <5>; + focaltech,ic-type = <0x3658D488>; + focaltech,touch-type = "primary"; + + vdd-supply = <&L4E>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_spi_active>; + pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; + pinctrl-2 = <&ts_spi_release>; + }; +}; + +&sdhc_1 { + status = "ok"; + vdd-supply = <&L5E>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&L24B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + /* + * min/max voltages are voted on L24B/L28B and L24B/L28B_PBS + * regulators will only be voted for enabling/disabling conditions + * to support FR84471 for chipsets where PMIC doesn't support + * PBS ram sequence to turn OFF regulators automatically on + * multicard tray removal and these new regulator resources are + * exposed by PMIC team as part of this FR. + */ + vdd-en-dis-supply = <&L24B_PBS>; + + vdd-io-supply = <&L28B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + vdd-io-en-dis-supply = <&L28B_PBS>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + /* + * Here parrot phy is used for ravelin as it + * do not have its own list for module load and + * hence compatible is using parrot. + * We have plan to improve this by making phy binary + * target independent. + */ + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <88530>; + vdda-pll-max-microamp = <18310>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L5E>; + vcc-max-microamp = <1056000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <750000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + /* + * ufs-dev-types and nvmem entries are for ufs device + * identification using nvmem interface. Use number of + * ufs devices supported for ufs-dev-types, and nvmem handle + * added by pmic for sdam register. + * + * Default value taken by driver is bit[0] = 0 for 3.x and + * bit[0] = 1 for 2.x driver code takes this as default case. + * + * But Bit value to identify ufs device is not consistent + * across the targets it could be bit[0] = 0/1 for UFS2.x/3x + * and vice versa. If the bit[0] value is not same as default + * value used in driver and if its reverted then use flag + * qcom,ufs-dev-revert to identify ufs device. + */ + ufs-dev-types = <2>; + qcom,ufs-dev-revert; + nvmem-cells = <&ufs_dev>, <&boot_config>; + nvmem-cell-names = "ufs_dev", "boot_conf"; + + status = "ok"; +}; + +&battery_charger { + qcom,thermal-mitigation-step = <500000>; + qcom,wireless-charging-not-supported; +}; diff --git a/qcom/ravelin-coresight.dtsi b/qcom/ravelin-coresight.dtsi new file mode 100644 index 00000000..586fac35 --- /dev/null +++ b/qcom/ravelin-coresight.dtsi @@ -0,0 +1,3727 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + atid = <40>; + + out-ports { + port { + audio_etm0_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_audio_etm0>; + }; + }; + }; + }; + + tpdm_lpass_lpi: tpdm_lpass_lpi { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-tpdm-lpass-lpi"; + qcom,dummy-source; + + atid = <26>; + + out-ports { + port { + tpdm_lpass_lpi_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_tpdm_lpass_lpi>; + }; + }; + }; + }; + + tpdm_lpass: tpdm@10844000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10844000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <74>; + out-ports { + port { + tpdm_lpass_out_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_in_tpdm_lpass>; + }; + }; + }; + }; + + tpdm_dl_lpass: tpdm@10c38000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c38000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <74>; + out-ports { + port { + tpdm_dl_lpass_out_tpda_dl_lpass_10: endpoint { + remote-endpoint = + <&tpda_dl_lpass_10_in_tpdm_dl_lpass>; + }; + }; + }; + }; + + lpass_stm: lpass_stm { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-lpass-stm"; + qcom,dummy-source; + + atid = <25>; + + out-ports { + port { + lpass_stm_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_lpass_stm>; + }; + }; + }; + }; + + tpdm_swao_prio_0: tpdm@10b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b09000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_0_out_tpda_aoss_0: endpoint { + remote-endpoint = + <&tpda_aoss_0_in_tpdm_swao_prio_0>; + }; + }; + }; + }; + + tpdm_swao_prio_1: tpdm@10b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0a000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_1_out_tpda_aoss_1: endpoint { + remote-endpoint = + <&tpda_aoss_1_in_tpdm_swao_prio_1>; + }; + }; + }; + }; + + tpdm_swao_prio_2: tpdm@10b0b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0b000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_2_out_tpda_aoss_2: endpoint { + remote-endpoint = + <&tpda_aoss_2_in_tpdm_swao_prio_2>; + }; + }; + }; + }; + + tpdm_swao_prio_3: tpdm@10b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0c000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-prio-3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_prio_3_out_tpda_aoss_3: endpoint { + remote-endpoint = + <&tpda_aoss_3_in_tpdm_swao_prio_3>; + }; + }; + }; + }; + + tpdm_swao_1: tpdm@10b0d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0d000 0x1000>; + reg-names = "tpdm-base"; + + atid = <71>; + coresight-name = "coresight-tpdm-swao-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_swao_out_tpda_aoss_4: endpoint { + remote-endpoint = + <&tpda_aoss_4_in_tpdm_swao>; + }; + }; + }; + }; + + tpdm_ddr_ch01: tpdm@10d20000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d20000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-ch01"; + + atid = <78>; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_ch01_out_funnel_ddr_ch01: endpoint { + remote-endpoint = + <&funnel_ddr_ch01_in_tpdm_ddr_ch01>; + }; + }; + }; + }; + + tpdm_ddr: tpdm@10d00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d00000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-ddr"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ddr_dl0_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_tpdm_ddr_dl0>; + }; + }; + }; + }; + + tpdm_shrm: tpdm@10d01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d01000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-shrm"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + out-ports { + port { + tpdm_shrm_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_tpdm_shrm>; + }; + }; + }; + }; + + tpdm_gpu: tpdm@10900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10900000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + + atid = <79>; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_gpu_out_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_in_tpdm_gpu>; + }; + }; + }; + }; + + tpdm_prng: tpdm@10841000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10841000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + atid = <78>; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_dl_center_19: endpoint { + remote-endpoint = + <&tpda_dl_center_19_in_tpdm_prng>; + }; + }; + }; + }; + + tpdm_qm: tpdm@109d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109d0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-qm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_qm_out_tpda_dl_center_20: endpoint { + remote-endpoint = + <&tpda_dl_center_20_in_tpdm_qm>; + }; + }; + }; + }; + + tpdm_gcc: tpdm@1082c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x1082c000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-gcc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_gcc_out_tpda_dl_center_21: endpoint { + remote-endpoint = + <&tpda_dl_center_21_in_tpdm_gcc>; + }; + }; + }; + }; + + tpdm_vsense: tpdm@10840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10840000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-vsense"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_vsense_out_tpda_dl_center_22: endpoint { + remote-endpoint = + <&tpda_dl_center_22_in_tpdm_vsense>; + }; + }; + }; + }; + + tpdm_emmc: tpdm@10c23000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c23000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-emmc"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_sdcc_out_tpda_dl_lpass_0: endpoint { + remote-endpoint = + <&tpda_dl_lpass_0_in_tpdm_sdcc>; + }; + }; + }; + }; + + tpdm_sdcc: tpdm@10c20000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c20000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-sdcc"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_sdcc2_out_tpda_dl_west: endpoint { + remote-endpoint = + <&tpda_dl_west_in_tpdm_sdcc2>; + }; + }; + }; + }; + + tpdm_ipa: tpdm@10c22000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c22000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-ipa"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_ipa_out_tpda_dl_center_24: endpoint { + remote-endpoint = + <&tpda_dl_center_24_in_tpdm_ipa>; + }; + }; + }; + }; + + tpdm_pimem: tpdm@10850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10850000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_pimem_out_tpda_dl_center_25: endpoint { + remote-endpoint = + <&tpda_dl_center_25_in_tpdm_pimem>; + }; + }; + }; + }; + + tpdm_dlct: tpdm@10c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c28000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-dlct"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dlct_out_tpda_dl_center_26: endpoint { + remote-endpoint = + <&tpda_dl_center_26_in_tpdm_dlct>; + }; + }; + }; + }; + + tpdm_ipcc: tpdm@10c29000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c29000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-ipcc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_out_tpda_dl_center_27: endpoint { + remote-endpoint = + <&tpda_dl_center_27_in_tpdm_ipcc>; + }; + }; + }; + }; + + tpdm_dl_west: tpdm@10C48000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10C48000 0x1000>; + reg-names = "tpdm-base"; + + atid = <101>; + coresight-name = "coresight-tpdm-dl-west"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dl_west_out_tpda_dl_west: endpoint { + remote-endpoint = + <&tpda_dl_west_in_tpdm_dl_west>; + }; + }; + }; + }; + + snoc: snoc { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-snoc"; + qcom,dummy-source; + + atid = <125>; + out-ports { + port { + snoc_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_snoc>; + }; + }; + }; + }; + + tpdm_spdm: tpdm@1000f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x1000f000 0x1000>; + reg-names = "tpdm-base"; + + atid = <65>; + coresight-name = "coresight-tpdm-spdm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_spdm_out_tpda_qdss_1: endpoint { + remote-endpoint = + <&tpda_qdss_1_in_tpdm_spdm>; + }; + }; + }; + }; + + stm: stm@10002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + reg = <0x10002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + atid = <16>; + coresight-name = "coresight-stm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_stm>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@10003000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10003000 0x1000>; + reg-names = "tpdm-base"; + + atid = <65>; + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dcc_out_tpda_qdss_0: endpoint { + remote-endpoint = + <&tpda_qdss_0_in_tpdm_dcc>; + }; + }; + }; + }; + + tpdm_dl_center2_dsb: tpdm@10ac0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10ac0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dlct2-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dlct0_out_tpda_dl_center2_26: endpoint { + remote-endpoint = + <&tpda_dl_center2_26_in_tpdm_dlct0>; + }; + }; + }; + }; + + tpdm_dl_center2_cmb: tpdm@10ac1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10ac1000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dlct2-cmb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + status = "disabled"; + out-ports { + port { + tpdm_dlct1_out_tpda_dl_center2_27: endpoint { + remote-endpoint = + <&tpda_dl_center2_27_in_tpdm_dlct1>; + }; + }; + }; + }; + + tpdm_dl_south0: tpdm@109c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109c0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dl-south-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_dl_south0_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_dl_south0>; + }; + }; + }; + }; + + tpdm_dl_south1: tpdm@109c1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109c1000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-dl-south-cmb"; + + clocks = <&aoss_qmp>; + status = "disabled"; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_dl_south1_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_dl_south1>; + }; + }; + }; + }; + + tpdm_rdpm: tpdm@10c00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c00000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-rdpm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + status = "disabled"; + + out-ports { + port { + tpdm_rdpm_out_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_in_tpdm_rdpm>; + }; + }; + }; + }; + + tpdm_rdpm_mx: tpdm@10c01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c01000 0x1000>; + reg-names = "tpdm-base"; + + atid = <79>; + coresight-name = "coresight-tpdm-rdpm-mx"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + status = "disabled"; + + out-ports { + port { + tpdm_rdpm_mx_out_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_in_tpdm_rdpm_mx>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@128a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x128a0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <66>; + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_llm_silver_out_tpda_apss_0: endpoint { + remote-endpoint = + <&tpda_apss_0_in_tpdm_llm_silver>; + }; + }; + }; + }; + + tpdm_actpm: tpdm@12860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x12860000 0x1000>; + reg-names = "tpdm-base"; + + atid = <66>; + coresight-name = "coresight-tpdm-actpm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_apss0_out_tpda_apss_3: endpoint { + remote-endpoint = + <&tpda_apss_3_in_tpdm_apss0>; + }; + }; + }; + }; + + tpdm_apss: tpdm@12861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x12861000 0x1000>; + reg-names = "tpdm-base"; + + atid = <66>; + coresight-name = "coresight-tpdm-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_apps1_out_tpda_apss_4: endpoint { + remote-endpoint = + <&tpda_apss_4_in_tpdm_apps1>; + }; + }; + }; + }; + + tpdm_modem_0: tpdm@10800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10800000 0x1000>; + reg-names = "tpdm-base"; + + atid = <67>; + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_modem_0_out_tpda_modem_0: endpoint { + remote-endpoint = + <&tpda_modem_0_in_tpdm_modem_0>; + }; + }; + }; + }; + + tpdm_modem_1: tpdm@10801000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10801000 0x1000>; + reg-names = "tpdm-base"; + + atid = <67>; + coresight-name = "coresight-tpdm-modem-1"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-msr-skip; + + out-ports { + port { + tpdm_modem_1_out_tpda_modem_1: endpoint { + remote-endpoint = + <&tpda_modem_1_in_tpdm_modem_1>; + }; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + atid = <36 37>; + out-ports { + port { + modem_etm0_out_funnel_modem_q6_dup: endpoint { + remote-endpoint = + <&funnel_modem_q6_dup_in_modem_etm0>; + }; + }; + }; + }; + + modem2_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem2-etm0"; + qcom,inst-id = <11>; + + atid = <39>; + out-ports { + port { + modem2_etm0_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_modem2_etm0>; + }; + }; + }; + }; + + modem_diag: modem_diag { + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-modem-diag"; + qcom,dummy-source; + + atid = <50>; + out-ports { + port { + modem_diag_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_modem_diag>; + }; + }; + }; + }; + + tpdm_wcss: tpdm@109A4000 { + compatible = "arm,coresight-dummy-source"; + qcom,dummy-source; + + atid = <24>; + coresight-name = "coresight-tpdm-wcss"; + + out-ports { + port { + tpdm_wcss_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_wcss>; + }; + }; + }; + }; + + tpdm_tmess_prng: tpdm@10cc9000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc9000 0x1000>; + reg-names = "tpdm-base"; + + atid = <85>; + coresight-name = "coresight-tpdm-tmess-prng"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_tmess_prng_out_tpda_tmess_0: endpoint { + remote-endpoint = + <&tpda_tmess_0_in_tpdm_tmess_prng>; + }; + }; + }; + }; + + tpdm_tmess_0: tpdm@10cc0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc0000 0x1000>; + reg-names = "tpdm-base"; + + atid = <85>; + coresight-name = "coresight-tpdm-tmess-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_tmess_0_out_tpda_tmess_1: endpoint { + remote-endpoint = + <&tpda_tmess_1_in_tpdm_tmess_0>; + }; + }; + }; + }; + + tpdm_tmess_1: tpdm@10cc1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc1000 0x1000>; + reg-names = "tpdm-base"; + + atid = <85>; + coresight-name = "coresight-tpdm-tmess-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + tpdm_tmess_1_out_tpda_tmess_2: endpoint { + remote-endpoint = + <&tpda_tmess_2_in_tpdm_tmess_1>; + }; + }; + }; + }; + + tpdm_wpss: tpdm@10c70000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c70000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-wpss-dsb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_wpss_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_tpdm_wpss>; + }; + }; + }; + }; + + tpdm_wpss1: tpdm@10c71000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c71000 0x1000>; + reg-names = "tpdm-base"; + + atid = <78>; + coresight-name = "coresight-tpdm-wpss-cmb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_wpss_1_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_tpdm_wpss_1>; + }; + }; + }; + }; + + wpss_etm: wpss_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-wpss-etm0"; + qcom,inst-id = <3>; + atid = <44>; + + out-ports { + port { + wpss_etm0_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_wpss_etm0>; + }; + }; + }; + }; + + funnel_wpss: funnel@10c73000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c73000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-wpss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_wpss_in_tpdm_wpss: endpoint { + remote-endpoint = + <&tpdm_wpss_out_funnel_wpss>; + }; + }; + + port@1 { + reg = <1>; + funnel_wpss_in_tpdm_wpss_1: endpoint { + remote-endpoint = + <&tpdm_wpss_1_out_funnel_wpss>; + }; + }; + + port@2 { + reg = <2>; + funnel_wpss_in_wpss_etm0: endpoint { + remote-endpoint = + <&wpss_etm0_out_funnel_wpss>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_wpss_out_tpda_dl_center_5: endpoint { + remote-endpoint = + <&tpda_dl_center_5_in_funnel_wpss>; + source = <&tpdm_wpss>; + }; + }; + + port@1 { + reg = <1>; + funnel_wpss_out_tpda_dl_center_6: endpoint { + remote-endpoint = + <&tpda_dl_center_6_in_funnel_wpss>; + source = <&tpdm_wpss1>; + }; + }; + + port@2 { + reg = <2>; + funnel_wpss_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_wpss>; + source = <&wpss_etm>; + }; + }; + + }; + }; + + funnel_lpass_lpi: funnel@10b44000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-lpass_lpi"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_lpi_in_audio_etm0: endpoint { + remote-endpoint = + <&audio_etm0_out_funnel_lpass_lpi>; + }; + }; + + port@1 { + reg = <1>; + funnel_lpass_lpi_in_lpass_stm: endpoint { + remote-endpoint = + <&lpass_stm_out_funnel_lpass_lpi>; + }; + }; + + port@5 { + reg = <5>; + funnel_lpass_lpi_in_tpdm_lpass_lpi: endpoint { + remote-endpoint = + <&tpdm_lpass_lpi_out_funnel_lpass_lpi>; + }; + }; + + }; + + out-ports { + port { + funnel_lpass_lpi_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_lpass_lpi>; + }; + }; + + }; + }; + + funnel_gfx_dl: funnel@10902000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10902000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gfx_dl"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_gfx_dl_in_tpdm_gpu: endpoint { + remote-endpoint = + <&tpdm_gpu_out_funnel_gfx_dl>; + }; + }; + + }; + + out-ports { + port { + funnel_gfx_out_tpda_dl_center2_17: endpoint { + remote-endpoint = + <&tpda_dl_center2_17_in_funnel_gfx>; + }; + }; + + }; + }; + + + funnel_lpass: funnel@10846000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10846000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_lpass_in_tpdm_lpass: endpoint { + remote-endpoint = + <&tpdm_lpass_out_funnel_lpass>; + }; + }; + + }; + + out-ports { + port { + funnel_lpass_out_tpda_dl_lpass_2: endpoint { + remote-endpoint = + <&tpda_dl_lpass_2_in_funnel_lpass>; + }; + }; + + }; + }; + + funnel_ddr_ch01: funnel@10d22000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10d22000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_ch01"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_ddr_ch01_in_tpdm_ddr_ch01: endpoint { + remote-endpoint = + <&tpdm_ddr_ch01_out_funnel_ddr_ch01>; + }; + }; + + }; + + out-ports { + port { + funnel_ddr_ch01_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_funnel_ddr_ch01>; + }; + }; + + }; + }; + + funnel_ddr_dl0: funnel@10d03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10d03000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_dl0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_dl0_in_funnel_ddr_ch01: endpoint { + remote-endpoint = + <&funnel_ddr_ch01_out_funnel_ddr_dl0>; + }; + }; + + port@2 { + reg = <2>; + funnel_ddr_dl0_in_tpdm_ddr_dl0: endpoint { + remote-endpoint = + <&tpdm_ddr_dl0_out_funnel_ddr_dl0>; + }; + }; + + port@3 { + reg = <3>; + funnel_ddr_dl0_in_tpdm_shrm: endpoint { + remote-endpoint = + <&tpdm_shrm_out_funnel_ddr_dl0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_out_tpda_dl_center_9: endpoint { + remote-endpoint = + <&tpda_dl_center_9_in_funnel_ddr>; + source = <&tpdm_ddr_ch01>; + }; + }; + + port@1 { + reg = <1>; + funnel_ddr_out_tpda_dl_center_11: endpoint { + remote-endpoint = + <&tpda_dl_center_11_in_funnel_ddr>; + source = <&tpdm_ddr>; + }; + }; + + port@2 { + reg = <2>; + funnel_ddr_out_tpda_dl_center_12: endpoint { + remote-endpoint = + <&tpda_dl_center_12_in_funnel_ddr>; + source = <&tpdm_shrm>; + }; + }; + + }; + }; + + funnel_dlct_1: funnel@10c02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c02000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_dl_center_1_in_tpdm_rdpm: endpoint { + remote-endpoint = + <&tpdm_rdpm_out_funnel_dl_center_1>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl_center_1_in_tpdm_rdpm_mx: endpoint { + remote-endpoint = + <&tpdm_rdpm_mx_out_funnel_dl_center_1>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dl_center_1_out_tpda_dl_center_10: endpoint { + remote-endpoint = + <&tpda_dl_center_10_in_funnel_dl_center_1>; + source = <&tpdm_rdpm>; + }; + }; + + port@1 { + reg = <1>; + funnel_dl_center_1_out_tpda_dl_center_11: endpoint { + remote-endpoint = + <&tpda_dl_center_11_in_funnel_dl_center_1>; + source = <&tpdm_rdpm_mx>; + }; + }; + }; + }; + + tpda_tmess: tpda@10cc4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10cc4000 0x1000>; + reg-names = "tpda-base"; + + qcom,cmb-elem-size = <0 64>, + <1 64>, + <2 32>; + qcom,dsb-elem-size = <1 32>; + + qcom,tpda-atid = <85>; + coresight-name = "coresight-tpda-tmess"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_tmess_0_in_tpdm_tmess_prng: endpoint { + remote-endpoint = + <&tpdm_tmess_prng_out_tpda_tmess_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_tmess_1_in_tpdm_tmess_0: endpoint { + remote-endpoint = + <&tpdm_tmess_0_out_tpda_tmess_1>; + }; + }; + + port@2 { + reg = <2>; + tpda_tmess_2_in_tpdm_tmess_1: endpoint { + remote-endpoint = + <&tpdm_tmess_1_out_tpda_tmess_2>; + }; + }; + + }; + + out-ports { + + port { + tpda_tmess_out_funnel_tmess: endpoint { + remote-endpoint = + <&funnel_tmess_in_tpda_tmess>; + }; + }; + + }; + }; + + funnel_tmess: funnel@10cc5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10cc5000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-tmess"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_tmess_in_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_out_funnel_tmess>; + }; + }; + + }; + + out-ports { + port { + funnel_tmess_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_tmess>; + }; + }; + + }; + }; + + tpda_modem: tpda@10803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10803000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + coresight-name = "coresight-tpda-modem"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_modem_0_in_tpdm_modem_0: endpoint { + remote-endpoint = + <&tpdm_modem_0_out_tpda_modem_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_modem_1_in_tpdm_modem_1: endpoint { + remote-endpoint = + <&tpdm_modem_1_out_tpda_modem_1>; + }; + }; + + }; + + out-ports { + + port { + tpda_modem_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem>; + }; + }; + + }; + }; + + funnel_modem_q6_dup: funnel@1080d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x1080d000 0x1000>, + <0x1080c000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-modem_q6_dup"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_q6_dup_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_funnel_modem_q6_dup>; + }; + }; + + }; + + out-ports { + port { + funnel_modem_q6_dup_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_funnel_modem_q6_dup>; + }; + }; + + }; + }; + + funnel_modem_q6: funnel@1080c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x1080c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem_q6"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_modem_q6_in_funnel_modem_q6_dup: endpoint { + remote-endpoint = + <&funnel_modem_q6_dup_out_funnel_modem_q6>; + }; + }; + + port@2 { + reg = <2>; + funnel_modem_q6_in_modem_diag: endpoint { + remote-endpoint = + <&modem_diag_out_funnel_modem_q6>; + }; + }; + + }; + + out-ports { + port { + funnel_modem_q6_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_funnel_modem_q6>; + }; + }; + + }; + }; + + funnel_modem: funnel@10804000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10804000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_modem_in_modem2_etm0: endpoint { + remote-endpoint = + <&modem2_etm0_out_funnel_modem>; + }; + }; + + port@0 { + reg = <0>; + funnel_modem_in_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_out_funnel_modem>; + }; + }; + + port@3 { + reg = <3>; + funnel_modem_in_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_out_funnel_modem>; + }; + }; + + }; + + out-ports { + port { + funnel_modem_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_modem>; + }; + }; + + }; + }; + + tpda_apss: tpda@12863000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x12863000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <4 32>; + qcom,cmb-elem-size = <0 32>, + <3 64>; + + coresight-name = "coresight-tpda-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_apss_0_in_tpdm_llm_silver: endpoint { + remote-endpoint = + <&tpdm_llm_silver_out_tpda_apss_0>; + }; + }; + + port@3 { + reg = <3>; + tpda_apss_3_in_tpdm_apss0: endpoint { + remote-endpoint = + <&tpdm_apss0_out_tpda_apss_3>; + }; + }; + + port@4 { + reg = <4>; + tpda_apss_4_in_tpdm_apps1: endpoint { + remote-endpoint = + <&tpdm_apps1_out_tpda_apss_4>; + }; + }; + + }; + + out-ports { + port { + tpda_apss_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_tpda_apss>; + }; + }; + + }; + }; + + funnel_apss: funnel@12810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x12810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_in_funnel_ete: endpoint { + remote-endpoint = + <&funnel_ete_out_funnel_apss>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss_in_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_out_funnel_apss>; + }; + }; + + }; + + out-ports { + port { + funnel_apss_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_apss>; + }; + }; + + }; + }; + + tpda_dl_center: tpda@10c2b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10c2b000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <78>; + + qcom,dsb-elem-size = <5 32>, + <9 32>, + <11 32>, + <20 32>, + <21 32>, + <25 32>, + <26 32>; + + qcom,cmb-elem-size = <6 32>, + <11 32>, + <12 64>, + <19 64>, + <22 32>, + <24 64>, + <25 64>, + <27 64>; + + coresight-name = "coresight-tpda-dlct0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + tpda_dl_center_5_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_tpda_dl_center_5>; + }; + }; + + port@6 { + reg = <6>; + tpda_dl_center_6_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_tpda_dl_center_6>; + }; + }; + + port@9 { + reg = <9>; + tpda_dl_center_9_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda_dl_center_9>; + }; + }; + + port@c { + reg = <11>; + tpda_dl_center_11_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda_dl_center_11>; + }; + }; + + port@d { + reg = <12>; + tpda_dl_center_12_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_tpda_dl_center_12>; + }; + }; + + port@13 { + reg = <19>; + tpda_dl_center_19_in_tpdm_prng: endpoint { + remote-endpoint = + <&tpdm_prng_out_tpda_dl_center_19>; + }; + }; + + port@14 { + reg = <20>; + tpda_dl_center_20_in_tpdm_qm: endpoint { + remote-endpoint = + <&tpdm_qm_out_tpda_dl_center_20>; + }; + }; + + port@15 { + reg = <21>; + tpda_dl_center_21_in_tpdm_gcc: endpoint { + remote-endpoint = + <&tpdm_gcc_out_tpda_dl_center_21>; + }; + }; + + port@16 { + reg = <22>; + tpda_dl_center_22_in_tpdm_vsense: endpoint { + remote-endpoint = + <&tpdm_vsense_out_tpda_dl_center_22>; + }; + }; + + port@18 { + reg = <24>; + tpda_dl_center_24_in_tpdm_ipa: endpoint { + remote-endpoint = + <&tpdm_ipa_out_tpda_dl_center_24>; + }; + }; + + port@19 { + reg = <25>; + tpda_dl_center_25_in_tpdm_pimem: endpoint { + remote-endpoint = + <&tpdm_pimem_out_tpda_dl_center_25>; + }; + }; + + port@1a { + reg = <26>; + tpda_dl_center_26_in_tpdm_dlct: endpoint { + remote-endpoint = + <&tpdm_dlct_out_tpda_dl_center_26>; + }; + }; + + port@1b { + reg = <27>; + tpda_dl_center_27_in_tpdm_ipcc: endpoint { + remote-endpoint = + <&tpdm_ipcc_out_tpda_dl_center_27>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_center_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_tpda_dl_center>; + }; + }; + + }; + }; + + funnel_dlct0: funnel@10c2c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c2c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_center_in_tpda_dl_center: endpoint { + remote-endpoint = + <&tpda_dl_center_out_funnel_dl_center>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl_center_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_funnel_dl_center>; + }; + }; + + port@7 { + reg = <7>; + funnel_dl_center_in_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_out_funnel_dl_center>; + }; + }; + }; + + out-ports { + port { + funnel_dl_center_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_center>; + }; + }; + + }; + }; + + funnel_dl_south: funnel@109c3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x109c3000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl_south"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + funnel_dl_south_in_tpdm_dl_south0: endpoint { + remote-endpoint = + <&tpdm_dl_south0_out_funnel_dl_south>; + }; + }; + + port@3 { + reg = <3>; + funnel_dl_south_in_tpdm_dl_south1: endpoint { + remote-endpoint = + <&tpdm_dl_south1_out_funnel_dl_south>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl_south_in_tpdm_wcss: endpoint { + remote-endpoint = + <&tpdm_wcss_out_funnel_dl_south>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_south_out_tpda_dl_center2_7: endpoint { + remote-endpoint = + <&tpda_dl_center2_7_in_funnel_dl_south>; + source = <&tpdm_dl_south0>; + }; + }; + + port@1 { + reg = <1>; + funnel_dl_south_out_tpda_dl_center2_8: endpoint { + remote-endpoint = + <&tpda_dl_center2_8_in_funnel_dl_south>; + source = <&tpdm_dl_south1>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl_south_out_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_in_funnel_dl_south>; + }; + }; + }; + }; + + tpda_dl_center2: tpda@10ac3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10ac3000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <79>; + + qcom,dsb-elem-size = <7 32>, + <17 32>, + <26 32>; + + qcom,cmb-elem-size = <8 64>, + <13 64>, + <14 64>, + <27 64>; + + coresight-name = "coresight-tpda-dlct2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + tpda_dl_center2_7_in_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_out_tpda_dl_center2_7>; + }; + }; + + port@8 { + reg = <8>; + tpda_dl_center2_8_in_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_out_tpda_dl_center2_8>; + }; + }; + + + port@d { + reg = <13>; + tpda_dl_center_10_in_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_out_tpda_dl_center_10>; + }; + }; + + port@e { + reg = <14>; + tpda_dl_center_11_in_funnel_dl_center_1: endpoint { + remote-endpoint = + <&funnel_dl_center_1_out_tpda_dl_center_11>; + }; + }; + + port@11 { + reg = <17>; + tpda_dl_center2_17_in_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_out_tpda_dl_center2_17>; + }; + }; + + port@1a { + reg = <26>; + tpda_dl_center2_26_in_tpdm_dlct0: endpoint { + remote-endpoint = + <&tpdm_dlct0_out_tpda_dl_center2_26>; + }; + }; + + port@1b { + reg = <27>; + tpda_dl_center2_27_in_tpdm_dlct1: endpoint { + remote-endpoint = + <&tpdm_dlct1_out_tpda_dl_center2_27>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_center2_out_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_in_tpda_dl_center2>; + }; + }; + + }; + }; + + + funnel_dl_center2: funnel@10ac4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10ac4000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_center2_in_tpda_dl_center2: endpoint { + remote-endpoint = + <&tpda_dl_center2_out_funnel_dl_center2>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl_center2_in_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_out_funnel_dl_center2>; + }; + }; + + port@6 { + reg = <6>; + funnel_dl_center2_in_funnel_dl_lpass: endpoint { + remote-endpoint = + <&funnel_dl_lpass_out_funnel_dl_center2>; + }; + }; + + }; + + out-ports { + port { + funnel_dl_center2_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_center2>; + }; + }; + + }; + }; + + tpda_dl_west: tpda@10c4a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10c4a000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <101>; + coresight-name = "coresight-tpda-dl-west"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-elem-size = <0 32>, + <10 32>; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_dl_west_in_tpdm_sdcc2: endpoint { + remote-endpoint = + <&tpdm_sdcc2_out_tpda_dl_west>; + }; + }; + + port@10 { + reg = <10>; + tpda_dl_west_in_tpdm_dl_west: endpoint { + remote-endpoint = + <&tpdm_dl_west_out_tpda_dl_west>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_west_out_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_in_tpda_dl_west>; + }; + }; + + }; + }; + + funnel_dl_west: funnel@10c4b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c4b000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-west"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + port { + funnel_dl_west_in_tpda_dl_west: endpoint { + remote-endpoint = + <&tpda_dl_west_out_funnel_dl_west>; + }; + }; + + }; + + out-ports { + port { + funnel_dl_west_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_west>; + }; + }; + + }; + }; + + + + tpda_dl_lpass: tpda@10c3a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10c3a000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <74>; + coresight-name = "coresight-tpda-dl-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,cmb-elem-size = <0 32>; + qcom,dsb-elem-size = <2 32>, + <10 32>; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_dl_lpass_0_in_tpdm_sdcc: endpoint { + remote-endpoint = + <&tpdm_sdcc_out_tpda_dl_lpass_0>; + }; + }; + + port@2 { + reg = <2>; + tpda_dl_lpass_2_in_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_out_tpda_dl_lpass_2>; + }; + }; + + port@10 { + reg = <10>; + tpda_dl_lpass_10_in_tpdm_dl_lpass: endpoint { + remote-endpoint = + <&tpdm_dl_lpass_out_tpda_dl_lpass_10>; + }; + }; + + }; + + out-ports { + + port { + tpda_dl_lpass_out_funnel_dl_lpass: endpoint { + remote-endpoint = + <&funnel_dl_lpass_in_tpda_dl_lpass>; + }; + }; + + }; + }; + + funnel_dl_lpass: funnel@10c3b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c3b000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + port { + funnel_dl_lpass_in_tpda_dl_lpass: endpoint { + remote-endpoint = + <&tpda_dl_lpass_out_funnel_dl_lpass>; + }; + }; + + }; + + out-ports { + port { + funnel_dl_lpass_out_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_in_funnel_dl_lpass>; + }; + }; + + }; + }; + + tpda_qdss: tpda@10004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10004000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <65>; + coresight-name = "coresight-tpda-qdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-elem-size = <0 32>, + <1 32>; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_0_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda_qdss_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_qdss_1_in_tpdm_spdm: endpoint { + remote-endpoint = + <&tpdm_spdm_out_tpda_qdss_1>; + }; + }; + + + }; + + out-ports { + + port { + tpda_qdss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpda_qdss>; + }; + }; + + }; + }; + + funnel_in0: funnel@10041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_in_snoc: endpoint { + remote-endpoint = + <&snoc_out_funnel_in0>; + }; + }; + + port@1 { + reg = <1>; + funnel_in0_in_funnel_tmess: endpoint { + remote-endpoint = + <&funnel_tmess_out_funnel_in0>; + }; + }; + + port@6 { + reg = <6>; + funnel_in0_in_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_out_funnel_in0>; + }; + }; + + port@7 { + reg = <7>; + funnel_in0_in_stm: endpoint { + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_in_funnel_in0>; + }; + }; + + }; + }; + + funnel_in1: funnel@10042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel_in1_in_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_out_funnel_in1>; + }; + }; + + port@5 { + reg = <5>; + funnel_in1_in_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_out_funnel_in1>; + }; + }; + + + port@6 { + reg = <6>; + funnel_in1_in_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_out_funnel_in1>; + }; + }; + + port@7 { + reg = <7>; + funnel_in1_in_funnel_dl_center2: endpoint { + remote-endpoint = + <&funnel_dl_center2_out_funnel_in1>; + }; + }; + + }; + + out-ports { + port { + funnel_in1_out_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_in_funnel_in1>; + }; + }; + + }; + }; + + funnel_merg: funnel@10045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_qdss_in_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_out_funnel_qdss>; + }; + }; + + port@0 { + reg = <0>; + funnel_qdss_in_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_out_funnel_qdss>; + }; + }; + + }; + + out-ports { + port { + funnel_qdss_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_qdss>; + }; + }; + + }; + }; + + tpda_aoss: tpda@10b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10b08000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-aoss"; + + qcom,tpda-atid = <71>; + qcom,cmb-elem-size = <0 64>, + <1 64>, + <2 64>, + <3 64>; + + qcom,dsb-elem-size = <4 32>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_aoss_0_in_tpdm_swao_prio_0: endpoint { + remote-endpoint = + <&tpdm_swao_prio_0_out_tpda_aoss_0>; + }; + }; + + port@1 { + reg = <1>; + tpda_aoss_1_in_tpdm_swao_prio_1: endpoint { + remote-endpoint = + <&tpdm_swao_prio_1_out_tpda_aoss_1>; + }; + }; + + port@2 { + reg = <2>; + tpda_aoss_2_in_tpdm_swao_prio_2: endpoint { + remote-endpoint = + <&tpdm_swao_prio_2_out_tpda_aoss_2>; + }; + }; + + port@3 { + reg = <3>; + tpda_aoss_3_in_tpdm_swao_prio_3: endpoint { + remote-endpoint = + <&tpdm_swao_prio_3_out_tpda_aoss_3>; + }; + }; + + port@4 { + reg = <4>; + tpda_aoss_4_in_tpdm_swao: endpoint { + remote-endpoint = + <&tpdm_swao_out_tpda_aoss_4>; + }; + }; + + }; + + out-ports { + + port { + tpda_aoss_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_tpda_aoss>; + }; + }; + + }; + }; + + funnel_aoss: funnel@10b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10b04000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-aoss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + funnel_aoss_in_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_out_funnel_aoss>; + }; + }; + + port@6 { + reg = <6>; + funnel_aoss_in_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_out_funnel_aoss>; + }; + }; + + port@7 { + reg = <7>; + funnel_aoss_in_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_out_funnel_aoss>; + }; + }; + }; + + out-ports { + port { + funnel_aoss_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_aoss>; + }; + }; + + }; + }; + + dummy_eud: dummy_sink { + compatible = "arm,coresight-dummy-sink"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + in-ports { + port { + eud_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + }; + + tmc_etf: tmc@10b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x10b05000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_out_tmc_etf>; + }; + }; + }; + + out-ports { + port { + tmc_etf_out_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_in_tmc_etf>; + }; + }; + }; + }; + + replicator_swao: replicator@10b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + + reg = <0x10b06000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_swao"; + + qcom,replicator-loses-context; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + in-ports { + port { + replicator_swao_in_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_out_replicator_swao>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_swao_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_replicator_swao>; + }; + }; + + port@1 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + }; + }; + + replicator_qdss: replicator@10046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + + reg = <0x10046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_qdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + in-ports { + port { + replicator_qdss_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_replicator_qdss>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_qdss_out_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_in_replicator_qdss>; + }; + }; + }; + }; + + replicator_etr: replicator@1004e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + + reg = <0x1004e000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_etr"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_etr_in_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_out_replicator_etr>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_etr_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator_etr>; + }; + }; + + port@1 { + reg = <1>; + replicator_etr_out_tmc_etr1: endpoint { + remote-endpoint = + <&tmc_etr1_in_replicator_etr>; + }; + }; + }; + }; + + tmc_etr: tmc@10048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x10048000 0x1000>, + <0x10064000 0x16000>; + reg-names = "tmc-base", "bam-base"; + + qcom,iommu-dma = "bypass"; + iommus = <&apps_smmu 0x04e0 0>, + <&apps_smmu 0x0520 0>; + + qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + + qcom,sw-usb; + dma-coherent; + coresight-name = "coresight-tmc-etr"; + + coresight-csr = <&csr>; + csr-atid-offset = <0xf8>; + csr-irqctrl-offset = <0x6c>; + byte-cntr-name = "byte-cntr"; + byte-cntr-class-name = "coresight-tmc-etr-stream"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + arm,scatter-gather; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etr_in_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_out_tmc_etr>; + }; + }; + }; + }; + + tmc_etr1: tmc@1004f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x1004f000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etr1"; + + iommus = <&apps_smmu 0x0500 0>; + qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + dma-coherent; + + coresight-csr = <&csr>; + csr-atid-offset = <0x108>; + csr-irqctrl-offset = <0x70>; + byte-cntr-name = "byte-cntr1"; + byte-cntr-class-name = "coresight-tmc-etr1-stream"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + arm,scatter-gather; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etr1_in_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_out_tmc_etr1>; + }; + }; + }; + }; + + csr: csr@10001000 { + compatible = "qcom,coresight-csr"; + + reg = <0x10001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,perflsheot-set-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + qcom,blk-size = <1>; + }; + + swao_csr: csr@10b11000 { + compatible = "qcom,coresight-csr"; + + reg = <0x10b11000 0x1000>, + <0x10b110f8 0x50>; + reg-names = "csr-base", "msr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + qcom,msr-support; + qcom,blk-size = <1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + qc_cti: cti@10010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10010000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-qc_cti"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cti-gpio-trigout = <16>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_a>; + }; + + cti0: cti@10c2a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c2a000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-cti0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + south_cti: cti@109C2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109C2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-dl_south_cti0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_dl_0_cti_0: cti@10d02000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d02000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_dl_0_cti_0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_dl_1_cti_0: cti@10d0c000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d0c000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_dl_1_cti_0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_ch01_dl_cti_0: cti@10d21000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d21000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_ch01_dl_cti_0"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_dl_cti: cti@10845000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10845000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_dl_cti"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + gpu_isdb_cti: cti@10961000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10961000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-gpu_isdb_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + gpu_cortex_m3: cti@10962000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10962000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-gpu_cortex_m3"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + turing_dl_cti_0: cti@10982000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10982000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-turing_dl_cti_0"; + + status = "disabled"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + turing_q6_cti: cti@1098b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1098b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-turing_q6_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wlan_q6_cti: cti@10C7B000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10C7B000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wlan_q6_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + swao_cti: cti@10b00000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b00000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-swao_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,extended_cti; + }; + + cortex_m3: cti@10b13000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b13000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-cortex_m3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_lpi_cti: cti@10b41000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b41000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_lpi_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_q6_cti: cti@10b4b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b4b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_q6_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti0: cti@128e0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x128e0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti1: cti@128f0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x128f0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti2: cti@12900000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12900000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + riscv_cti: cti@1282b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1282b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-riscv_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + mss_q6_cti: cti@1080b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1080b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss_q6_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + mss_vq6_cti: cti@10813000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10813000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss_vq6_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_0: cti@10cc2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_0"; + + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_1: cti@10cc3000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc3000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_1"; + + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cpu: cti@10cd1000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cd1000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cpu"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_atb_cti: cti@12862000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12862000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_atb_cti"; + + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddrss_shrm2: cti@10d11000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d11000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddrss_shrm2"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + Sierra_A6: cti@10C13000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10C13000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-sierra_a6"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wcss0: cti@109AC000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109AC000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-sierra_a6"; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wcss1: cti@109ad000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109ad000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wcss1"; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + wcss2: cti@109Ae000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x109Ae000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-wcss2"; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ipcb_tgu: tgu@10b0e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b0e000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + spmi_tgu0: tgu@10b0f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b0f000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <9>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-spmi0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + spmi_tgu1: tgu@10b10000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b10000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <9>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-spmi1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + etm0 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12040000 0x1000>; + cpu = <&CPU0>; + + coresight-name = "coresight-etm0"; + qcom,skip-power-up; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <1>; + out-ports { + port { + ete0_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete0>; + }; + }; + }; + }; + + etm1 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12140000 0x1000>; + cpu = <&CPU1>; + + coresight-name = "coresight-etm1"; + qcom,skip-power-up; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <2>; + out-ports { + port { + ete1_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete1>; + }; + }; + }; + }; + + etm2 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12240000 0x1000>; + cpu = <&CPU2>; + + coresight-name = "coresight-etm2"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <3>; + out-ports { + port { + ete2_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete2>; + }; + }; + }; + }; + + etm3 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12340000 0x1000>; + cpu = <&CPU3>; + + coresight-name = "coresight-etm3"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <4>; + out-ports { + port { + ete3_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete3>; + }; + }; + }; + }; + + etm4 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12440000 0x1000>; + cpu = <&CPU4>; + + coresight-name = "coresight-etm4"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <5>; + out-ports { + port { + ete4_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete4>; + }; + }; + }; + }; + + etm5 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12540000 0x1000>; + cpu = <&CPU5>; + + coresight-name = "coresight-etm5"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <6>; + out-ports { + port { + ete5_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete5>; + }; + }; + }; + }; + + etm6 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12640000 0x1000>; + cpu = <&CPU6>; + + coresight-name = "coresight-etm6"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <7>; + out-ports { + port { + ete6_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete6>; + }; + }; + }; + }; + + etm7 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x12740000 0x1000>; + cpu = <&CPU7>; + + coresight-name = "coresight-etm7"; + qcom,skip-power-up; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <8>; + out-ports { + port { + ete7_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete7>; + }; + }; + }; + }; + + funnel_etm: funnel@12800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x12800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-etm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_ete_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_funnel_ete>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ete_in_ete0: endpoint { + remote-endpoint = + <&ete0_out_funnel_ete>; + }; + }; + + port@1 { + reg = <1>; + funnel_ete_in_ete1: endpoint { + remote-endpoint = + <&ete1_out_funnel_ete>; + }; + }; + + port@2 { + reg = <2>; + funnel_ete_in_ete2: endpoint { + remote-endpoint = + <&ete2_out_funnel_ete>; + }; + }; + + port@3 { + reg = <3>; + funnel_ete_in_ete3: endpoint { + remote-endpoint = + <&ete3_out_funnel_ete>; + }; + }; + + port@4 { + reg = <4>; + funnel_ete_in_ete4: endpoint { + remote-endpoint = + <&ete4_out_funnel_ete>; + }; + }; + + port@5 { + reg = <5>; + funnel_ete_in_ete5: endpoint { + remote-endpoint = + <&ete5_out_funnel_ete>; + }; + }; + + port@6 { + reg = <6>; + funnel_ete_in_ete6: endpoint { + remote-endpoint = + <&ete6_out_funnel_ete>; + }; + }; + + port@7 { + reg = <7>; + funnel_ete_in_ete7: endpoint { + remote-endpoint = + <&ete7_out_funnel_ete>; + }; + }; + }; + }; +}; diff --git a/qcom/ravelin-debug.dtsi b/qcom/ravelin-debug.dtsi new file mode 100644 index 00000000..c0b1e3eb --- /dev/null +++ b/qcom/ravelin-debug.dtsi @@ -0,0 +1,1584 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xc00000>; + }; +}; + +&soc { + dcc: dcc_v2@100ff000 { + compatible = "qcom,dcc-v2"; + reg = <0x100ff000 0x1000>, + <0x10080000 0x18000>; + + qcom,transaction_timeout = <0>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0>; + + link_list_0 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list_1 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + cpuss_reg { + qcom,dump-size = <0x30000>; + qcom,dump-id = <0xef>; + }; + + l1_icache0 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x87>; + }; + + l1_itlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb700 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb700 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x47>; + }; + + l2_cache600 { + qcom,dump-size = <0x48100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x48100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x121>; + }; + + l2_tlb200 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x122>; + }; + + l2_tlb300 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x123>; + }; + + l2_tlb400 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x124>; + }; + + l2_tlb500 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x125>; + }; + + l2_tlb600 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x126>; + }; + + l2_tlb700 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x127>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + }; +}; diff --git a/qcom/ravelin-dma-heaps.dtsi b/qcom/ravelin-dma-heaps.dtsi new file mode 100644 index 00000000..004a2ef0 --- /dev/null +++ b/qcom/ravelin-dma-heaps.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + qcom,user_contig { + qcom,dma-heap-name = "qcom,user-contig"; + qcom,dma-heap-type = ; + memory-region = <&user_contig_mem>; + }; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; + + qcom,audio_ml { + qcom,dma-heap-name = "qcom,audio-ml"; + qcom,dma-heap-type = ; + memory-region = <&audio_cma_mem>; + }; + + non_secure_display_dma_buf: qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = ; + qcom,max-align = <9>; + memory-region = <&non_secure_display_memory>; + }; + }; +}; + diff --git a/qcom/ravelin-idp-overlay.dts b/qcom/ravelin-idp-overlay.dts new file mode 100644 index 00000000..e46b8a1e --- /dev/null +++ b/qcom/ravelin-idp-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin IDP"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts b/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts new file mode 100644 index 00000000..8f917453 --- /dev/null +++ b/qcom/ravelin-idp-wcn3950-amoled-rcm-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelin-idp-wcn3950-amoled-rcm.dts b/qcom/ravelin-idp-wcn3950-amoled-rcm.dts new file mode 100644 index 00000000..49f04598 --- /dev/null +++ b/qcom/ravelin-idp-wcn3950-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin.dtsi" +#include "ravelin-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin WCN3950 IDP + AMOLED + RCM"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi new file mode 100644 index 00000000..fec6cbb4 --- /dev/null +++ b/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp.dtsi" + +&soc { +}; + +&qupv3_se1_i2c { + status = "disabled"; +}; + +&qupv3_se1_spi { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + + goodix-berlin@0 { + reg = <0>; + spi-max-frequency = <1000000>; + + goodix,avdd-name = "avdd"; + avdd-supply = <&L4E>; + + interrupt-parent = <&tlmm>; + interrupts = <91 0x2008>; + goodix,reset-gpio = <&tlmm 90 0x00>; + goodix,irq-gpio = <&tlmm 91 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_spi_active>; + pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; + pinctrl-2 = <&ts_spi_release>; + + qcom,touch-environment = "pvm"; + }; +}; diff --git a/qcom/ravelin-idp-wcn3988-4gb-overlay.dts b/qcom/ravelin-idp-wcn3988-4gb-overlay.dts new file mode 100644 index 00000000..cc8bf2e9 --- /dev/null +++ b/qcom/ravelin-idp-wcn3988-4gb-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-idp-wcn3988-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR + WCN3988"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/ravelin-idp-wcn3988-4gb.dts b/qcom/ravelin-idp-wcn3988-4gb.dts new file mode 100644 index 00000000..c186a13d --- /dev/null +++ b/qcom/ravelin-idp-wcn3988-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-4gb.dtsi" +#include "ravelin-idp-wcn3988-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin IDP 4GB DDR + WCN3988"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/ravelin-idp-wcn3988-4gb.dtsi b/qcom/ravelin-idp-wcn3988-4gb.dtsi new file mode 100644 index 00000000..122b06c7 --- /dev/null +++ b/qcom/ravelin-idp-wcn3988-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp.dtsi" diff --git a/qcom/ravelin-idp.dts b/qcom/ravelin-idp.dts new file mode 100644 index 00000000..451a3e72 --- /dev/null +++ b/qcom/ravelin-idp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin.dtsi" +#include "ravelin-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin IDP"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/ravelin-idp.dtsi b/qcom/ravelin-idp.dtsi new file mode 100644 index 00000000..5de7dd7b --- /dev/null +++ b/qcom/ravelin-idp.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-pmic-overlay.dtsi" +#include "ravelin-pm7250b.dtsi" +#include "ravelin-thermal-overlay.dtsi" + +&soc { +}; + +&qupv3_se8_i2c { + awinic@64 { + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + }; +}; + +&qupv3_se1_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + focaltech,reset-gpio = <&tlmm 12 0x00>; + focaltech,irq-gpio = <&tlmm 13 0x2008>; + focaltech,display-coords = <0 0 1080 2408>; + focaltech,max-touch-number = <10>; + focaltech,ic-type = <0x8726081C>; + focaltech,touch-type = "primary"; + + pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-type = "primary"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0x984000 0x910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x4000>; + focaltech,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0x2008>; + }; +}; + +&sdhc_1 { + status = "ok"; + vdd-supply = <&L5E>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&L24B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + /* + * min/max voltages are voted on L24B/L28B and L24B/L28B_PBS + * regulators will only be voted for enabling/disabling conditions + * to support FR84471 for chipsets where PMIC doesn't support + * PBS ram sequence to turn OFF regulators automatically on + * multicard tray removal and these new regulator resources are + * exposed by PMIC team as part of this FR. + */ + vdd-en-dis-supply = <&L24B_PBS>; + + vdd-io-supply = <&L28B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + vdd-io-en-dis-supply = <&L28B_PBS>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + /* + * Here parrot phy is used for ravelin as it + * do not have its own list for module load and + * hence compatible is using parrot. + * We have plan to improve this by making phy binary + * target independent. + */ + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <88530>; + vdda-pll-max-microamp = <18310>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L5E>; + vcc-max-microamp = <1056000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <750000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + /* + * ufs-dev-types and nvmem entries are for ufs device + * identification using nvmem interface. Use number of + * ufs devices supported for ufs-dev-types, and nvmem handle + * added by pmic for sdam register. + * + * Default value taken by driver is bit[0] = 0 for 3.x and + * bit[0] = 1 for 2.x driver code takes this as default case. + * + * But Bit value to identify ufs device is not consistent + * across the targets it could be bit[0] = 0/1 for UFS2.x/3x + * and vice versa. If the bit[0] value is not same as default + * value used in driver and if its reverted then use flag + * qcom,ufs-dev-revert to identify ufs device. + */ + ufs-dev-types = <2>; + qcom,ufs-dev-revert; + nvmem-cells = <&ufs_dev>, <&boot_config>; + nvmem-cell-names = "ufs_dev", "boot_conf"; + + status = "ok"; +}; + +&battery_charger { + qcom,thermal-mitigation-step = <500000>; + qcom,wireless-charging-not-supported; +}; diff --git a/qcom/ravelin-low-memory.dtsi b/qcom/ravelin-low-memory.dtsi new file mode 100644 index 00000000..201d98f4 --- /dev/null +++ b/qcom/ravelin-low-memory.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&trust_ui_vm_mem { + status = "disabled"; +}; + +&trust_ui_vm_qrtr { + status = "disabled"; +}; + +&trust_ui_vm_vblk0_ring { + status = "disabled"; +}; + +&trust_ui_vm_swiotlb { + status = "disabled"; +}; + +&non_secure_display_dma_buf { + status = "disabled"; +}; + +&non_secure_display_memory { + status = "disabled"; +}; + +&soc { + qcom,guestvm_loader@e0b00000 { + status = "disabled"; + }; + + qrtr-gunyah { + status = "disabled"; + }; + + qcom,virtio_backend@0 { + status = "disabled"; + }; +}; diff --git a/qcom/ravelin-msm-rdbg.dtsi b/qcom/ravelin-msm-rdbg.dtsi new file mode 100644 index 00000000..e15e0053 --- /dev/null +++ b/qcom/ravelin-msm-rdbg.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* smp2p information */ + qcom,smp2p_interrupt_rdbg_2_out { + compatible = "qcom,smp2p-interrupt-rdbg-2-out"; + qcom,smem-states = <&smp2p_rdbg2_out 0>; + qcom,smem-state-names = "rdbg-smp2p-out"; + }; + + qcom,smp2p_interrupt_rdbg_2_in { + compatible = "qcom,smp2p-interrupt-rdbg-2-in"; + interrupts-extended = <&smp2p_rdbg2_in 0 0>; + interrupt-names = "rdbg-smp2p-in"; + }; +}; diff --git a/qcom/ravelin-pcie.dtsi b/qcom/ravelin-pcie.dtsi new file mode 100644 index 00000000..2b751c85 --- /dev/null +++ b/qcom/ravelin-pcie.dtsi @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + + interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie0_msi>; + + perst-gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_perst_default + &pcie0_clkreq_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_perst_default + &pcie0_clkreq_sleep + &pcie0_wake_default>; + + gdsc-vdd-supply = <&gcc_pcie_0_gdsc>; + vreg-1p8-supply = <&L16B>; + vreg-0p9-supply = <&L5B>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MX_LEVEL>; + qcom,vreg-1p8-voltage-level = <1200000 1200000 15070>; + qcom,vreg-0p9-voltage-level = <880000 880000 46890>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>, + <&gcc GCC_QMIP_PCIE_AHB_CLK>, + <&pcie_0_pipe_clk>; + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", + "pcie_ddrss_sf_tbu_clk", + "pcie_aggre_noc_0_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk", + "pcie_pipe_clk_mux", "pcie_0_pipe_div2_clk", + "pcie_qmip_pcie_ahb_clk", "pcie_pipe_clk_ext_src"; + max-clock-frequency-hz = <0>, <0>, <0>, <19200000>, <0>, <0>, + <0>, <0>, <0>, <0>, <0>, <100000000>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + dma-coherent; + qcom,smmu-sid-base = <0x1400>; + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,drv-supported; + qcom,drv-l1ss-timeout-us = <5000>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + qcom,config-recovery; + + qcom,pcie-phy-ver = <107>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xca 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0xa2 0x0 + 0x0050 0x07 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0ee4 0x20 0x0 + 0x0e84 0x75 0x0 + 0x0e90 0x3f 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0xbf 0x0 + 0x1168 0x3f 0x0 + 0x116c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1190 0x34 0x0 + 0x1194 0x38 0x0 + 0x10d8 0x0f 0x0 + 0x0e3c 0x12 0x0 + 0x0e40 0x01 0x0 + 0x10dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1044 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x10cc 0xf0 0x0 + 0x10f4 0x07 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x0694 0x00 0x0 + 0x0654 0x00 0x0 + 0x06a8 0x0f 0x0 + 0x0048 0x90 0x0 + 0x0620 0xc1 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x02dc 0x05 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500 + 0x04D0 0x04D4 0x03C0 0x0630 0x0230 + 0x0000>; + + qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x0204 0x0730 + 0x0734 0x0738 0x073C>; + + qcom,phy-debug-reg = <0x0068 0x0140 0x0144 0x0148 0x014C + 0x0150 0x0160 0x0178 0x0ED0 0x0EDC + 0x0F34 0x0F38 0x0f3C 0x0F40 0x0F44 + 0x0F48 0x0F4C 0x0F50 0x0F54 0x0F58 + 0x11E8 0x0A00 0x0A04 0x0A08 0x0A0C + 0x0A10 0x0A14 0x0A18 0x0C20 0x0214 + 0x0218 0x021C 0x0220 0x0224 0x0228 + 0x022C 0x0230 0x0234 0x0238 0x023C + 0x0600 0x0604 0x1204 0x1210>; + + status = "disabled"; + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@0x17210040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17210040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; +}; diff --git a/qcom/ravelin-pinctrl.dtsi b/qcom/ravelin-pinctrl.dtsi new file mode 100644 index 00000000..fad561c0 --- /dev/null +++ b/qcom/ravelin-pinctrl.dtsi @@ -0,0 +1,1403 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + tlmm: pinctrl@f000000 { + compatible = "qcom,ravelin-tlmm"; + reg = <0xf000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + qcom,gpios-reserved = <0 1 2 3>; + + qupv3_se7_2uart_pins: qupv3_se7_2uart_pins { + qupv3_se7_2uart_tx_active: qupv3_se7_2uart_tx_active { + mux { + pins = "gpio22"; + function = "qup1_se2_l2"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_2uart_rx_active: qupv3_se7_2uart_rx_active { + mux { + pins = "gpio23"; + function = "qup1_se2_l3"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se2_4uart_pins: qupv3_se2_4uart_pins { + qupv3_se2_default_cts: qupv3_se2_default_cts { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se2_default_rts: qupv3_se2_default_rts { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se2_default_tx: qupv3_se2_default_tx { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_default_rx: qupv3_se2_default_rx { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se2_cts: qupv3_se2_cts { + mux { + pins = "gpio14"; + function = "qup0_se2_l0"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_rts: qupv3_se2_rts { + mux { + pins = "gpio15"; + function = "qup0_se2_l1"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se2_tx: qupv3_se2_tx { + mux { + pins = "gpio16"; + function = "qup0_se2_l2"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_rx: qupv3_se2_rx { + mux { + pins = "gpio17"; + function = "qup0_se2_l3"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_2uart_pins: qupv3_se0_2uart_pins { + qupv3_se0_2uart_tx_active: qupv3_se0_2uart_tx_active { + mux { + pins = "gpio34"; + function = "qup0_se0_l2"; + }; + + config { + pins = "gpio34"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_2uart_rx_active: qupv3_se0_2uart_rx_active { + mux { + pins = "gpio35"; + function = "qup0_se0_l3"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_2uart_sleep: qupv3_se0_2uart_sleep { + mux { + pins = "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio34", "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio4"; + function = "qup0_se0_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio5"; + function = "qup0_se0_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { + mux { + pins = "gpio10"; + function = "qup0_se1_l0"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active { + mux { + pins = "gpio11"; + function = "qup0_se1_l1"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active { + mux { + pins = "gpio10"; + function = "qup0_se1_l0"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active { + mux { + pins = "gpio11"; + function = "qup0_se1_l1"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active { + mux { + pins = "gpio12"; + function = "qup0_se1_l2"; + }; + + config { + pins = "gpio12"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active { + mux { + pins = "gpio13"; + function = "qup0_se1_l3"; + }; + + config { + pins = "gpio13"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio10", "gpio11", + "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11", + "gpio12", "gpio13"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { + mux { + pins = "gpio18"; + function = "qup0_se3_l0"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio19"; + function = "qup0_se3_l1"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { + mux { + pins = "gpio18"; + function = "qup0_se3_l0"; + }; + + config { + pins = "gpio18"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { + mux { + pins = "gpio19"; + function = "qup0_se3_l1"; + }; + + config { + pins = "gpio19"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { + mux { + pins = "gpio20"; + function = "qup0_se3_l2"; + }; + + config { + pins = "gpio20"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { + mux { + pins = "gpio21"; + function = "qup0_se3_l3"; + }; + + config { + pins = "gpio21"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio18", "gpio19", + "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19", + "gpio20", "gpio21"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup0_se4_l0_mira"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup0_se4_l1_mira"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup0_se4_l0_mira"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup0_se4_l1_mira"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active { + mux { + pins = "gpio6"; + function = "qup0_se4_l2"; + }; + + config { + pins = "gpio6"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active { + mux { + pins = "gpio7"; + function = "qup0_se4_l3"; + }; + + config { + pins = "gpio7"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { + mux { + pins = "gpio0"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio1"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active { + mux { + pins = "gpio0"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active { + mux { + pins = "gpio1"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active { + mux { + pins = "gpio2"; + function = "qup1_se0_l2"; + }; + + config { + pins = "gpio2"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active { + mux { + pins = "gpio3"; + function = "qup1_se0_l3"; + }; + + config { + pins = "gpio3"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio50"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio51"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio51"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio50", "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio50", "gpio51"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio50"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio50"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio51"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio51"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio26"; + function = "qup1_se1_l2"; + }; + + config { + pins = "gpio26"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio27"; + function = "qup1_se1_l3"; + }; + + config { + pins = "gpio27"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio50", "gpio51", + "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio50", "gpio51", + "gpio26", "gpio27"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active { + mux { + pins = "gpio24"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active { + mux { + pins = "gpio25"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active { + mux { + pins = "gpio24"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio24"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active { + mux { + pins = "gpio25"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active { + mux { + pins = "gpio51"; + function = "qup1_se3_l2"; + }; + + config { + pins = "gpio51"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active { + mux { + pins = "gpio50"; + function = "qup1_se3_l3"; + }; + + config { + pins = "gpio50"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio51", "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio51", "gpio50"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active { + mux { + pins = "gpio91"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active { + mux { + pins = "gpio90"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio91", "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio91", "gpio90"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_miso_active: qupv3_se9_spi_miso_active { + mux { + pins = "gpio91"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio91"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se9_spi_mosi_active: qupv3_se9_spi_mosi_active { + mux { + pins = "gpio90"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio90"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se9_spi_clk_active: qupv3_se9_spi_clk_active { + mux { + pins = "gpio48"; + function = "qup1_se4_l2"; + }; + + config { + pins = "gpio48"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se9_spi_cs_active: qupv3_se9_spi_cs_active { + mux { + pins = "gpio43"; + function = "qup1_se4_l3"; + }; + + config { + pins = "gpio43"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio91", "gpio90", + "gpio48", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio91", "gpio90", + "gpio48", "gpio43"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + /* WCD reset pin */ + wcd_reset_active: wcd_reset_active { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <16>; + output-high; + }; + }; + + wcd_reset_sleep: wcd_reset_sleep { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio101"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio101"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio26"; + function = "qdss_cti"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* touchscreen pins */ + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + ts_spi_active: ts_spi_active { + mux { + pins = "gpio90", "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio90", "gpio91"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ts_spi_reset_suspend: ts_spi_reset_suspend { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ts_spi_int_suspend: ts_spi_int_suspend { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + ts_spi_release: ts_spi_release { + mux { + pins = "gpio90", "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio90", "gpio91"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pcie0 { + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio32"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio107"; + function = "pcie0_clk_req"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + usb_phy_ps: usb_phy_ps { + usb3phy_portselect_default: usb3phy_portselect_default { + mux { + pins = "gpio94"; + function = "usb0_phy_ps"; + }; + + config { + pins = "gpio94"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + }; +}; diff --git a/qcom/ravelin-pm7250b.dtsi b/qcom/ravelin-pm7250b.dtsi new file mode 100644 index 00000000..750724d2 --- /dev/null +++ b/qcom/ravelin-pm7250b.dtsi @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "pm7250b.dtsi" + +&soc { + qcom,pmic_glink { + status = "okay"; + }; + + qcom,pmic_glink_log { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + spmi_glink_debug: qcom,spmi_glink_debug { + compatible = "qcom,spmi-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi0_bus>; + + /* Primary SPMI bus */ + spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm7250b-debug@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + qcom,can-sleep; + }; + }; + }; + }; +}; + +&glink_edge { + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; + }; +}; + +&battery_charger { + status = "okay"; +}; + +&ucsi { + status = "okay"; +}; + +&altmode { + status = "okay"; +}; + +&spmi0_debug_bus { + qcom,pm7250b-debug@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm7250b-debug@9 { + compatible = "qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + +&pm7250b_2 { + /* Slave ID - 8 */ + reg = <8 SPMI_USID>; +}; + +&pm7250b_3 { + /* Slave ID - 9 */ + reg = <9 SPMI_USID>; +}; + +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; +}; + +&pm7250b_vadc { + interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + pm7250b_usb_conn_therm { + reg = ; + label = "pm7250b_usb_conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm7250b_charger_skin_therm { + reg = ; + label = "pm7250b_charger_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm7250b_adc_tm { + interrupts = <0x8 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; + + pm7250b_usb_conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm7250b_charger_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu_6_7 { + trip = <&socd_trip>; + cooling-device = <&cpu_6_7_pause 1 1>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm7250b-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <4000>; + }; + }; + }; + + pm7250b-ibat-lvl1 { + trips { + ibat-lvl1 { + temperature = <5000>; + }; + }; + }; + + pm7250b-bcl-lvl0 { + cooling-maps { + vbat_lte0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + vbat_nr0_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + vbat_nr0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + vbat_cpu_4 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu4_pause 1 1>; + }; + + vbat_cpu_5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_pause 1 1>; + }; + + vbat_cpu_6 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu6_pause 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm7250b-bcl-lvl1 { + cooling-maps { + vbat_lte1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + vbat_nr1_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 255 255>; + }; + + vbat_nr1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + + vbat_cpu_7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_pause 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm7250b-bcl-lvl2 { + cooling-maps { + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>; + }; + }; + }; + + sys-therm-9 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-7 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm7250b_tz { + interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; +}; + +&pm7250b_bcl { + interrupts = <0x8 0x1d 0x0 IRQ_TYPE_EDGE_RISING>, + <0x8 0x1d 0x1 IRQ_TYPE_EDGE_RISING>, + <0x8 0x1d 0x2 IRQ_TYPE_EDGE_RISING>; +}; + +&pm7250b_gpios { + display_panel_supply_ctrl { + display_panel_vddio_default: display_panel_vddio_default { + pins = "gpio11"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + + display_panel_extvdd_default: display_panel_extvdd_default { + pins = "gpio12"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; +}; + +&soc { + display_panel_vddio: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_vddio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm7250b_gpios 11 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_vddio>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_vddio_default>; + }; + + display_panel_extvdd: display_gpio_regulator@2 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_extvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm7250b_gpios 12 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_extvdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_extvdd_default>; + }; +}; diff --git a/qcom/ravelin-pmi632.dtsi b/qcom/ravelin-pmi632.dtsi new file mode 100644 index 00000000..518976db --- /dev/null +++ b/qcom/ravelin-pmi632.dtsi @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "pmi632.dtsi" + +&soc { + qcom,pmic_glink { + status = "okay"; + }; + + qcom,pmic_glink_log { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + spmi_glink_debug: qcom,spmi_glink_debug { + compatible = "qcom,spmi-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi0_bus>; + + /* Primary SPMI bus */ + spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pmi632-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + qcom,can-sleep; + }; + }; + }; + }; +}; + +&glink_edge { + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; + }; +}; + +&battery_charger { + status = "okay"; +}; + +&ucsi { + status = "okay"; +}; + +&altmode { + status = "disabled"; +}; + +&spmi0_debug_bus { + qcom,pmi632-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmi632-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + +&pmi632_gpios { + usb_conn_therm { + usb_conn_therm_default: usb_conn_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + charger_skin_temp { + charger_skin_temp_default: charger_skin_temp_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + + smb_skin_therm { + smb_skin_therm_default: smb_skin_therm_default { + pins = "gpio4"; + bias-high-impedance; + }; + }; +}; + +&pmi632_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&usb_conn_therm_default &charger_skin_temp_default + &smb_skin_therm_default>; + + pmi632_usb_conn_therm { + reg = ; + label = "pmi632_usb_conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmi632_charger_skin_temp { + reg = ; + label = "pmi632_charger_skin_temp"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmi632_smb_skin_therm { + reg = ; + label = "pmi632_smb_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmi632_adc_tm { + io-channels = <&pmi632_vadc ADC5_GPIO1_100K_PU>, + <&pmi632_vadc ADC5_GPIO2_100K_PU>, + <&pmi632_vadc ADC5_GPIO3_100K_PU>; + + pmi632_usb_conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmi632_charger_skin_temp { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmi632_smb_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + +}; + +&thermal_zones { + socd { + cooling-maps { + socd_cpu_6_7 { + trip = <&socd_trip>; + cooling-device = <&cpu_6_7_pause 1 1>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmi632-bcl-lvl0 { + cooling-maps { + vbat_lte0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + vbat_nr0_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + vbat_nr0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + vbat_cpu_4 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu4_pause 1 1>; + }; + + vbat_cpu_5 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu5_pause 1 1>; + }; + + vbat_cpu_6 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu6_pause 1 1>; + }; + + vbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmi632-bcl-lvl1 { + cooling-maps { + vbat_lte1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + vbat_nr1_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 255 255>; + }; + + vbat_nr1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + + vbat_cpu_7 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu7_pause 1 1>; + }; + + vbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pmi632-bcl-lvl2 { + cooling-maps { + vbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>; + }; + }; + }; + + sys-therm-9 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_adc_tm ADC5_GPIO1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-7 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_adc_tm ADC5_GPIO2_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-8 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmi632_adc_tm ADC5_GPIO3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&flash_led { + qcom,use-qti-battery-interface; +}; + +&pmi632_lcdb { + status = "ok"; +}; diff --git a/qcom/ravelin-pmic-overlay.dtsi b/qcom/ravelin-pmic-overlay.dtsi new file mode 100644 index 00000000..d6bc3028 --- /dev/null +++ b/qcom/ravelin-pmic-overlay.dtsi @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pmk8350.dtsi" +#include "pm6450.dtsi" + +&soc { + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; + + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pmk8350_sdam_5>; + nvmem-names = "pon_log"; + }; +}; + +&pmk8350 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1300; + + pon_hlos@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + qcom,log-kpd-event; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&pmk8350_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&quiet_therm_default &wide_rfc_therm_default + &rear_cam_flash_therm_default &pa_therm2_default &pa_therm1_default>; + + /delete-node/ pm8350_ref_gnd; + /delete-node/ pm8350_vref_1p25; + /delete-node/ pm8350_die_temp; + /delete-node/ pm8350_vph_pwr; + + /delete-node/ pm8350b_ref_gnd; + /delete-node/ pm8350b_vref_1p25; + /delete-node/ pm8350b_die_temp; + /delete-node/ pm8350b_vph_pwr; + /delete-node/ pm8350b_vbat_sns; + + /delete-node/ pmr735b_ref_gnd; + /delete-node/ pmr735b_vref_1p25; + /delete-node/ pmr735b_die_temp; + + /delete-node/ pmr735a_ref_gnd; + /delete-node/ pmr735a_vref_1p25; + /delete-node/ pmr735a_die_temp; + + /* PM6450 Channel nodes */ + pm6450_ref_gnd { + reg = ; + label = "pm6450_ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + pm6450_vref_1p25 { + reg = ; + label = "pm6450_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm6450_die_temp { + reg = ; + label = "pm6450_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm6450_quiet_therm { + reg = ; + label = "pm6450_quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmk8350_wide_rfc_therm { + reg = ; + label = "pmk8350_wide_rfc_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm6450_rear_cam_flash_therm { + reg = ; + label = "pm6450_rear_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pm6450_pa_therm2 { + reg = ; + label = "pm6450_pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pmk8350_pa_therm1 { + reg = ; + label = "pmk8350_pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pm8010_e: qcom,pm8010@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010e_tz: pm8010-e-temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; +}; + +&pmk8350_adc_tm { + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>, + <&pmk8350_vadc PM6450_ADC7_AMUX1_GPIO2_100K_PU>, + <&pmk8350_vadc PMK8350_ADC7_AMUX_THM2_100K_PU>, + <&pmk8350_vadc PM6450_ADC7_AMUX4_GPIO5_100K_PU>, + <&pmk8350_vadc PM6450_ADC7_AMUX3_GPIO4_100K_PU>, + <&pmk8350_vadc PMK8350_ADC7_AMUX_THM3_100K_PU>; + + pmk8350_xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm6450_quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmk8350_wide_rfc_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm6450_rear_cam_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm6450_pa2_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pmk8350_pa1_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pmk8350_gpios { + wide_rfc_therm { + wide_rfc_therm_default: wide_rfc_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + pa_therm1 { + pa_therm1_default: pa_therm1_default { + pins = "gpio2"; + bias-high-impedance; + }; + }; +}; + +&pmk8350_sdam_23 { + adc_scaling: scaling@bf { + reg = <0xbf 0x1>; + bits = <0 2>; + }; +}; + +&pmk8350_sdam_1 { + ufs_dev: ufs_dev@94 { + reg = <0x94 0x1>; + bits = <0 0>; + }; +}; + +&pm6450_gpios { + quiet_therm { + quiet_therm_default: quiet_therm_default { + pins = "gpio2"; + bias-high-impedance; + }; + }; + + rear_cam_flash_therm { + rear_cam_flash_therm_default: rear_cam_flash_therm_default { + pins = "gpio5"; + bias-high-impedance; + }; + }; + + pa_therm2 { + pa_therm2_default: pa_therm2_default { + pins = "gpio4"; + bias-high-impedance; + }; + }; + +}; + +&thermal_zones { + pm8010e_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8010e_tz>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + sys-therm-6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM2_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX1_GPIO2_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX4_GPIO5_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-11 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PM6450_ADC7_AMUX3_GPIO4_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&tlmm { + key_vol_up_default: key_vol_up_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + pm8010m_active: pm8010m-active { + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + + pm8010n_active: pm8010n-active { + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +/* + * Each QUP device that's a parent to PMIC must be listed as a critical device + * to GCC + */ +&gcc { + qcom,critical-devices = <&qupv3_se8_i2c>; +}; + +&qupv3_se8_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + pm8010m@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8010m_active>; + + pm8010-chip@900 { + reg = <0x900>; + + PM8010M_EN: qcom,pm8008-chip-en { + regulator-name = "pm8010m-chip-en"; + }; + }; + + qcom,revid@100 { + reg = <0x100>; + }; + }; + + pm8010m@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm8010m-regulator { + #address-cells = <1>; + #size-cells = <0>; + + pm8008_en-supply = <&PM8010M_EN>; + vdd_l1_l2-supply = <&S8B>; + + L1M: pm8010m_l1: regulator@4000 { + reg = <0x4000>; + regulator-name = "pm8010m_l1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + qcom,min-dropout-voltage = <88000>; + qcom,hpm-min-load = <30000>; + }; + + L2M: pm8010m_l2: regulator@4100 { + reg = <0x4100>; + regulator-name = "pm8010m_l2"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <80000>; + qcom,hpm-min-load = <30000>; + }; + + L3M: pm8010m_l3: regulator@4200 { + reg = <0x4200>; + regulator-name = "pm8010m_l3"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + qcom,hpm-min-load = <0>; + }; + + L4M: pm8010m_l4: regulator@4300 { + reg = <0x4300>; + regulator-name = "pm8010m_l4"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,hpm-min-load = <0>; + }; + + L6M: pm8010m_l6: regulator@4500 { + reg = <0x4500>; + regulator-name = "pm8010m_l6"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,hpm-min-load = <0>; + }; + + L7M: pm8010m_l7: regulator@4600 { + reg = <0x4600>; + regulator-name = "pm8010m_l7"; + regulator-min-microvolt = <2650000>; + regulator-max-microvolt = <2950000>; + qcom,hpm-min-load = <0>; + }; + }; + }; + + pm8010n@c { + compatible = "qcom,i2c-pmic"; + reg = <0xc>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8010n_active>; + + pm8010-chip@900 { + reg = <0x900>; + + PM8010N_EN: qcom,pm8008-chip-en { + regulator-name = "pm8010n-chip-en"; + }; + }; + + qcom,revid@100 { + reg = <0x100>; + }; + }; + + pm8010n@d { + compatible = "qcom,i2c-pmic"; + reg = <0xd>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm8010n-regulator { + #address-cells = <1>; + #size-cells = <0>; + + pm8008_en-supply = <&PM8010N_EN>; + vdd_l1_l2-supply = <&S8B>; + vdd_l3_l4-supply = <&S9B>; + + L1N: pm8010n_l1: regulator@4000 { + reg = <0x4000>; + regulator-name = "pm8010n_l1"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,min-dropout-voltage = <72000>; + qcom,hpm-min-load = <30000>; + }; + + L3N: pm8010n_l3: regulator@4200 { + reg = <0x4200>; + regulator-name = "pm8010n_l3"; + regulator-min-microvolt = <1736000>; + regulator-max-microvolt = <3312000>; + qcom,hpm-min-load = <0>; + qcom,min-dropout-voltage = <120000>; + }; + + L4N: pm8010n_l4: regulator@4300 { + reg = <0x4300>; + regulator-name = "pm8010N_l4"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1900000>; + qcom,hpm-min-load = <0>; + qcom,min-dropout-voltage = <152000>; + }; + + L6N: pm8010n_l6: regulator@4500 { + reg = <0x4500>; + regulator-name = "pm8010n_l6"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,hpm-min-load = <0>; + }; + }; + }; +}; + +&pm6450_pwm_1 { + status = "ok"; +}; + +&pm6450_gpios { + lcd_backlight_ctrl { + lcd_backlight_pwm_default: lcd_backlight_pwm_default { + pins = "gpio7"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <2>; + }; + + lcd_backlight_en_default: lcd_backlight_en_default { + pins = "gpio6"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + qcom,drive-strength = <2>; + }; + }; +}; diff --git a/qcom/ravelin-qcx6438.dtsi b/qcom/ravelin-qcx6438.dtsi new file mode 100644 index 00000000..f51eb0ac --- /dev/null +++ b/qcom/ravelin-qcx6438.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + wil6210: qcom,wil6210 { + qcom,pcie-parent = <&pcie0>; + qcom,wigig-en = <&tlmm 91 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wil6210_refclk_en_pin>; + qcom,11ad-bus-bw,name = "wil6210"; + qcom,11ad-bus-bw,num-cases = <3>; + qcom,11ad-bus-bw,num-paths = <1>; + qcom,11ad-bus-bw,vectors-KBps = <100 512 0 0>, + <100 512 600000 800000>, + <100 512 1300000 1300000>; + qcom,use-ext-supply; + vdd-s1c-supply = <&S9B>; + qcom,keep-radio-on-during-sleep; + qcom,use-ap-power-save; + status = "disabled"; + }; +}; + +&pcie0_rp { + #address-cells = <5>; + #size-cells = <0>; + + wil6210_pci: wil6210_pci { + reg = <0 0 0 0 0>; + qcom,iommu-group = <&wil6210_pci_iommu_group>; + + #address-cells = <1>; + #size-cells = <1>; + + wil6210_pci_iommu_group: wil6210_pci_iommu_group { + reg = <0 0>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-pagetable = "coherent"; + }; + }; +}; + +&tlmm { + talyn_pins { + wil6210_refclk_en_pin: wil6210_refclk_en_pin { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + }; +}; diff --git a/qcom/ravelin-qrd-4gb-overlay.dts b/qcom/ravelin-qrd-4gb-overlay.dts new file mode 100644 index 00000000..ea38d8c4 --- /dev/null +++ b/qcom/ravelin-qrd-4gb-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-qrd-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,msm-id = <568 0x10000>, <602 0x10000>; + qcom,board-id = <0x1000B 0x600>; +}; diff --git a/qcom/ravelin-qrd-4gb.dts b/qcom/ravelin-qrd-4gb.dts new file mode 100644 index 00000000..caadec8c --- /dev/null +++ b/qcom/ravelin-qrd-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-4gb.dtsi" +#include "ravelin-qrd-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin QRD 4GB DDR"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,board-id = <0x1000B 0x600>; +}; diff --git a/qcom/ravelin-qrd-4gb.dtsi b/qcom/ravelin-qrd-4gb.dtsi new file mode 100644 index 00000000..c0e0c1bc --- /dev/null +++ b/qcom/ravelin-qrd-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-qrd.dtsi" diff --git a/qcom/ravelin-qrd-overlay.dts b/qcom/ravelin-qrd-overlay.dts new file mode 100644 index 00000000..5de8fb12 --- /dev/null +++ b/qcom/ravelin-qrd-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin QRD"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>; + qcom,board-id = <0x1000B 0>; +}; + diff --git a/qcom/ravelin-qrd.dts b/qcom/ravelin-qrd.dts new file mode 100644 index 00000000..111cf271 --- /dev/null +++ b/qcom/ravelin-qrd.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin.dtsi" +#include "ravelin-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin QRD"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + diff --git a/qcom/ravelin-qrd.dtsi b/qcom/ravelin-qrd.dtsi new file mode 100644 index 00000000..cf9f8ecd --- /dev/null +++ b/qcom/ravelin-qrd.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-pmic-overlay.dtsi" +#include "ravelin-pmi632.dtsi" +#include "ravelin-thermal-overlay.dtsi" + +&soc { +}; + +&qupv3_se1_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,i2c-touch-active = "focaltech,fts_ts"; + + focaltech@38 { + status = "ok"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + focaltech,reset-gpio = <&tlmm 12 0x00>; + focaltech,irq-gpio = <&tlmm 13 0x2008>; + focaltech,display-coords = <0 0 1080 2408>; + focaltech,max-touch-number = <10>; + focaltech,ic-type = <0x8726081C>; + focaltech,touch-type = "primary"; + focaltech,touch-environment = "pvm"; + + pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + }; +}; + +&sdhc_1 { + status = "ok"; + vdd-supply = <&L5E>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&L24B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + /* + * min/max voltages are voted on L24B/L28B and L24B/L28B_PBS + * regulators will only be voted for enabling/disabling conditions + * to support FR84471 for chipsets where PMIC doesn't support + * PBS ram sequence to turn OFF regulators automatically on + * multicard tray removal and these new regulator resources are + * exposed by PMIC team as part of this FR. + */ + vdd-en-dis-supply = <&L24B_PBS>; + + vdd-io-supply = <&L28B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + vdd-io-en-dis-supply = <&L28B_PBS>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + /* + * Here parrot phy is used for ravelin as it + * do not have its own list for module load and + * hence compatible is using parrot. + * We have plan to improve this by making phy binary + * target independent. + */ + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <88530>; + vdda-pll-max-microamp = <18310>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L5E>; + vcc-max-microamp = <1056000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <750000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + /* + * ufs-dev-types and nvmem entries are for ufs device + * identification using nvmem interface. Use number of + * ufs devices supported for ufs-dev-types, and nvmem handle + * added by pmic for sdam register. + * + * Default value taken by driver is bit[0] = 0 for 3.x and + * bit[0] = 1 for 2.x driver code takes this as default case. + * + * But Bit value to identify ufs device is not consistent + * across the targets it could be bit[0] = 0/1 for UFS2.x/3x + * and vice versa. If the bit[0] value is not same as default + * value used in driver and if its reverted then use flag + * qcom,ufs-dev-revert to identify ufs device. + */ + ufs-dev-types = <2>; + qcom,ufs-dev-revert; + nvmem-cells = <&ufs_dev>, <&boot_config>; + nvmem-cell-names = "ufs_dev", "boot_conf"; + + status = "ok"; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x86 0x6c>; +}; + +&battery_charger { + qcom,thermal-mitigation-step = <500000>; + qcom,wireless-charging-not-supported; + qcom,thermal-mitigation = <11500000 11000000 10500000 10000000 9500000 + 9000000 8500000 8000000 7500000 7000000 6500000 + 6000000 5500000 5000000 4500000 4000000 3500000 + 3000000 2500000 2000000 1500000 1000000 500000>; +}; diff --git a/qcom/ravelin-qupv3.dtsi b/qcom/ravelin-qupv3.dtsi new file mode 100644 index 00000000..aeceb616 --- /dev/null +++ b/qcom/ravelin-qupv3.dtsi @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup1 0: SE 5 + * Qup1 1: SE 6 + * Qup1 2: SE 7 + * Qup1 3: SE 8 + * Qup1 4: SE 9 + */ + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x176 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x3e>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + dma-coherent; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x9c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x163 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + status = "ok"; + + /* HS UART Instance */ + qupv3_se2_4uart: qcom,qup_uart@988000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x988000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 17 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>, + <&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>; + pinctrl-1 = <&qupv3_se2_cts>, <&qupv3_se2_rts>, + <&qupv3_se2_tx>, <&qupv3_se2_rx>; + pinctrl-2 = <&qupv3_se2_cts>, <&qupv3_se2_rts>, + <&qupv3_se2_tx>, <&qupv3_se2_default_rx>; + pinctrl-3 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>, + <&qupv3_se2_default_tx>, <&qupv3_se2_default_rx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + /* HST Debug UART Instance */ + qupv3_se0_2uart: qcom,qup_uart@980000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x980000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_2uart_tx_active>, <&qupv3_se0_2uart_rx_active>; + pinctrl-1 = <&qupv3_se0_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma0 0 1 3 64 2>, + <&gpi_dma0 1 1 3 64 2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_spi: spi@984000 { + compatible = "qcom,spi-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, + <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma0 0 1 1 64 2>, + <&gpi_dma0 1 1 1 64 2>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>, + <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se4_spi: spi@990000 { + compatible = "qcom,spi-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>, + <&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x416 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x3f>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + dma-coherent; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x403 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + /* PORed Debug UART Instance */ + qupv3_se7_2uart: qcom,qup_uart@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>; + pinctrl-1 = <&qupv3_se7_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se5_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>, + <&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se8_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + qcom,shared; + status = "disabled"; + }; + + qupv3_se8_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>, + <&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + interconnect-names = "qup-core", "snoc-llcc", "qup-ddr"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>, + <&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + dmas = <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/ravelin-regulators.dtsi b/qcom/ravelin-regulators.dtsi new file mode 100644 index 00000000..3f67cb6f --- /dev/null +++ b/qcom/ravelin-regulators.dtsi @@ -0,0 +1,814 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&apps_rsc_drv2 { + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + VDD_MODEM_LEVEL: + S1B_LEVEL: + pm6450_s1_level: regulator-pm6450-s1-level { + regulator-name = "pm6450_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + VDD_CX_LEVEL: + S5B_LEVEL: + pm6450_s5_level: regulator-pm6450-s5-level { + regulator-name = "pm6450_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_CX_LEVEL_AO: + S5B_LEVEL_AO: + pm6450_s5_level_ao: regulator-pm6450-s5-level-ao { + regulator-name = "pm6450_s5_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "ebi.lvl"; + VDD_EBI_LEVEL: + S6B_LEVEL: + pm6450_s6_level: regulator-pm6450-s6-level { + regulator-name = "pm6450_s6_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpb7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb7"; + S7B: + pm6450_s7: regulator-pm6450-s7 { + regulator-name = "pm6450_s7"; + qcom,set = ; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + qcom,init-voltage = <1120000>; + }; + }; + + rpmh-regulator-smpb8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb8"; + S8B: + pm6450_s8: regulator-pm6450-s8 { + regulator-name = "pm6450_s8"; + qcom,set = ; + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1744000>; + qcom,init-voltage = <1352000>; + }; + }; + + rpmh-regulator-smpb9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb9"; + S9B: + pm6450_s9: regulator-pm6450-s9 { + regulator-name = "pm6450_s9"; + qcom,set = ; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1872000>; + }; + }; + + rpmh-regulator-ldob1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L1B: + pm6450_l1: regulator-pm6450-l1 { + regulator-name = "pm6450_l1"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + VDD_LPI_CX_LEVEL: + L2B_LEVEL: + pm6450_l2_level: regulator-pm6450-l2-level { + regulator-name = "pm6450_l2_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L3B: + pm6450_l3: regulator-pm6450-l3 { + regulator-name = "pm6450_l3"; + qcom,set = ; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + qcom,init-voltage = <904000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L4B: + pm6450_l4: regulator-pm6450-l4 { + regulator-name = "pm6450_l4"; + qcom,set = ; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <860000>; + qcom,init-voltage = <808000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L5B: + pm6450_l5: regulator-pm6450-l5 { + regulator-name = "pm6450_l4"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1052000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L6B: + pm6450_l6: regulator-pm6450-l6 { + regulator-name = "pm6450_l6"; + qcom,set = ; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + qcom,init-voltage = <824000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L7B: + pm6450_l7: regulator-pm6450-l7 { + regulator-name = "pm6450_l7"; + qcom,set = ; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + VDD_LPI_MX_LEVEL: + L8B_LEVEL: + pm6450_l8_level: regulator-pm6450-l8-level { + regulator-name = "pm6450_l8_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L9B: + pm6450_l9: regulator-pm6450-l9 { + regulator-name = "pm6450_l9"; + qcom,set = ; + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <824000>; + qcom,init-voltage = <752000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L10B: + pm6450_l10: regulator-pm6450-l10 { + regulator-name = "pm6450_l10"; + qcom,set = ; + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <901000>; + qcom,init-voltage = <824000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L11B: + pm6450_l11: regulator-pm6450-l11 { + regulator-name = "pm6450_l11"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <752000>; + qcom,init-voltage = <348000>; + }; + }; + + rpmh-regulator-ldob12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L12B: + pm6450_l12: regulator-pm6450-l12 { + regulator-name = "pm6450_l12"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1080000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L13B: + pm6450_l13: regulator-pm6450-l13 { + regulator-name = "pm6450_l13"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L14B: + pm6450_l14: regulator-pm6450-l14 { + regulator-name = "pm6450_l14"; + qcom,set = ; + regulator-min-microvolt = <1245000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1150000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L16B: + pm6450_l16: regulator-pm6450-l16 { + regulator-name = "pm6450_l16"; + qcom,set = ; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = ; + L17B: + pm6450_l17: regulator-pm6450-l17 { + regulator-name = "pm6450_l17"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob18 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L18B: + pm6450_l18: regulator-pm6450-l18 { + regulator-name = "pm6450_l18"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob19 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob19"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L19B: + pm6450_l19: regulator-pm6450-l19 { + regulator-name = "pm6450_l19"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob20 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob20"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L20B: + pm6450_l20: regulator-pm6450-l20 { + regulator-name = "pm6450_l20"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob21 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob21"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L21B: + pm6450_l21: regulator-pm6450-l21 { + regulator-name = "pm6450_l21"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob22 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob22"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L22B: + pm6450_l22: regulator-pm6450-l22 { + regulator-name = "pm6450_l22"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob23 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob23"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L23B: + pm6450_l23: regulator-pm6450-l23 { + regulator-name = "pm6450_l23"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob24 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob24"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L24B: + pm6450_l24: regulator-pm6450-l24 { + regulator-name = "pm6450_l24"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob25 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob25"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L25B: + pm6450_l25: regulator-pm6450-l25 { + regulator-name = "pm6450_l25"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3072000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob26 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob26"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L26B: + pm6450_l26: regulator-pm6450-l26 { + regulator-name = "pm6450_l26"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob27 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob27"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L27B: + pm6450_l27: regulator-pm6450-l27 { + regulator-name = "pm6450_l27"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob28 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob28"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L28B: + pm6450_l28: regulator-pm6450-l28 { + regulator-name = "pm6450_l28"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = ; + L1E: + pm8010l_l1: regulator-pm8010-l1 { + regulator-name = "pm8010_l1"; + qcom,set = ; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <864000>; + qcom,init-voltage = <530000>; + }; + }; + + rpmh-regulator-ldoe3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe3"; + qcom,regulator-type = "pmic5-ldo"; + /* mode voting is not allowed */ + L3E: + pm8010l_l3: regulator-pm8010-l3 { + regulator-name = "pm8010_l3"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2700000>; + }; + }; + + rpmh-regulator-ldoe4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe4"; + qcom,regulator-type = "pmic5-ldo"; + /* mode voting is not allowed */ + L4E: + pm8010_l4: regulator-pm8010-l4 { + regulator-name = "pm8010_l4"; + qcom,set = ; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <2700000>; + }; + }; + + rpmh-regulator-ldoe5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe5"; + qcom,regulator-type = "pmic5-ldo"; + /* mode voting is not allowed */ + L5E: + pm8010_l5: regulator-pm8010-l5 { + regulator-name = "pm8010_l5"; + qcom,set = ; + /* + * Remove min/max voltages for this regulator as initial + * voltage of L5E is set to be 2.4v/2.96v during PON + * depending upon the UFS mode. UFS is the only client + * on this and this regulator will only be voted + * for enabling/disabling conditions. + */ + }; + }; + + rpmh-regulator-ldoe6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe6"; + qcom,regulator-type = "pmic5-ldo"; + /* mode voting is not allowed */ + L6E: + pm8010_l6: regulator-pm8010-l6 { + regulator-name = "pm8010_l6"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + }; + }; + + rpmh-regulator-ldoe7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe7"; + qcom,regulator-type = "pmic5-ldo"; + /* mode voting is not allowed */ + L7E: + pm8010_l7: regulator-pm8010-l7 { + regulator-name = "pm8010_l7"; + qcom,set = ; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3000000>; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MX_LEVEL>; + + VDD_MX_LEVEL: + S1G_LEVEL: + pmg1110_s1_level: regulator-pmg1110-s1-level { + regulator-name = "pmg1110_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + + }; + }; + + rpmh-regulator-sf1-vreg-enable { + compatible = "qcom,rpmh-xob-regulator"; + qcom,resource-name = "gpioi7"; + status = "disabled"; + sf1_vreg_enable: regulator-sf1-vreg-enable { + regulator-name = "sf1_vreg_enable"; + qcom,set = ; + }; + }; + + rpmh-regulator-sf1-vreg-mode { + compatible = "qcom,rpmh-xob-regulator"; + qcom,resource-name = "gpioi10"; + status = "disabled"; + sf1_vreg_mode: regulator-sf1-vreg-mode { + regulator-name = "sf1_vreg_mode"; + qcom,set = ; + }; + }; + + rpmh-regulator-vrmsd { + compatible = "qcom,rpmh-pbs-regulator"; + qcom,resource-name = "vrm.sd"; + + L24B_PBS: + pm6450_l24_pbs: regulator-pm6450-l24-pbs { + regulator-name = "pm6450_l24_pbs"; + qcom,set = ; + /* + * min/max voltages are voted on L24B and this regulator will + * only be voted for enabling/disabling conditions. + */ + }; + }; + + rpmh-regulator-vrmpx2 { + compatible = "qcom,rpmh-pbs-regulator"; + qcom,resource-name = "vrm.px2"; + + L28B_PBS: + pm6450_l28_pbs: regulator-pm6450-l28-pbs { + regulator-name = "pm6450_l28_pbs"; + qcom,set = ; + /* + * min/max voltages are voted on L28B and this regulator will + * only be voted for enabling/disabling conditions. + */ + }; + }; +}; diff --git a/qcom/ravelin-reserved-memory.dtsi b/qcom/ravelin-reserved-memory.dtsi new file mode 100644 index 00000000..03120f6d --- /dev/null +++ b/qcom/ravelin-reserved-memory.dtsi @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_dtlog_mem: xbl_dtlog_region@80600000 { + no-map; + reg = <0x0 0x80600000 0x0 0x40000>; + }; + + xbl_ramdump_mem: xbl_ramdump_region@80640000 { + no-map; + reg = <0x0 0x80640000 0x0 0x1c0000>; + }; + + aop_image_mem: aop_image_region@80800000 { + no-map; + reg = <0x0 0x80800000 0x0 0x60000>; + }; + + aop_cmd_db_mem: aop_cmd_db_region@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + aop_config_mem: aop_config_region@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x20000>; + }; + + tme_crash_dump_mem: tme_crash_dump_region@808a0000 { + no-map; + reg = <0x0 0x808a0000 0x0 0x40000>; + }; + + tme_log_mem: tme_log_region@808e0000 { + no-map; + reg = <0x0 0x808e0000 0x0 0x4000>; + }; + + uefi_log_mem: uefi_log_region@808e4000 { + no-map; + reg = <0x0 0x808e4000 0x0 0x10000>; + }; + + chipinfo_mem: chipinfo_region@808f4000 { + no-map; + reg = <0x0 0x808f4000 0x0 0x1000>; + }; + + smem_mem: smem_region@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + cpucp_fw_mem: cpucp_fw_region@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + wlan_msa_mem: wlan_msa_mem_region@82a00000 { + no-map; + reg = <0x0 0x82a00000 0x0 0xc00000>; + }; + + camera_mem: camera_region@84b00000 { + no-map; + reg = <0x0 0x84b00000 0x0 0x800000>; + }; + + wpss_moselle_mem: wpss_moselle_region@85300000 { + no-map; + reg = <0x0 0x85300000 0x0 0x1900000>; + }; + + video_mem: video_region@86c00000 { + no-map; + reg = <0x0 0x86c00000 0x0 0x700000>; + }; + + adsp_mem: adsp_region@87300000 { + no-map; + reg = <0x0 0x87300000 0x0 0x2100000>; + }; + + ipa_fw_mem: ipa_fw_region@89400000 { + no-map; + reg = <0x0 0x89400000 0x0 0x10000>; + }; + + ipa_gsi_mem: ipa_gsi_region@89410000 { + no-map; + reg = <0x0 0x89410000 0x0 0xa000>; + }; + + gpu_microcode_mem: gpu_microcode_region@8941a000 { + no-map; + reg = <0x0 0x8941a000 0x0 0x2000>; + }; + + mpss_mem: mpss_region@8a000000 { + no-map; + reg = <0x0 0x8a000000 0x0 0xda00000>; + }; + + xbl_sc_mem: xbl_sc_region@a6e00000 { + no-map; + reg = <0x0 0xa6e00000 0x0 0x40000>; + }; + + global_sync_mem: global_sync_region@a6f00000 { + no-map; + reg = <0x0 0xa6f00000 0x0 0x100000>; + }; + + cpusys_vm_mem: cpusys_vm_region@e0600000 { + no-map; + reg = <0x0 0xe0600000 0x0 0x400000>; + }; + + trust_ui_vm_mem: trust_ui_vm_region@e0b00000 { + no-map; + reg = <0x0 0xe0b00000 0x0 0x4af3000>; + }; + + trust_ui_vm_qrtr: trust_ui_vm_qrtr@e55f3000 { + no-map; + reg = <0x0 0xe55f3000 0x0 0x9000>; + }; + + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring@e55fc000 { + no-map; + reg = <0x0 0xe55fc000 0x0 0x4000>; + gunyah-label = <0x11>; + }; + + trust_ui_vm_swiotlb: trust_ui_vm_swiotlb@e5600000 { + no-map; + reg = <0x0 0xe5600000 0x0 0x100000>; + gunyah-label = <0x12>; + }; + + tz_stat_mem: tz_stat_region@e8800000 { + no-map; + reg = <0x0 0xe8800000 0x0 0x100000>; + }; + + tags_mem: tags_region@e8900000 { + no-map; + reg = <0x0 0xe8900000 0x0 0x680000>; + }; + + qtee_mem: qtee_region@e8f80000 { + no-map; + reg = <0x0 0xe8f80000 0x0 0x500000>; + }; + + trusted_apps_mem: trusted_apps_region@e9480000 { + no-map; + reg = <0x0 0xe9480000 0x0 0x1200000>; + }; + +}; diff --git a/qcom/ravelin-rumi-overlay.dts b/qcom/ravelin-rumi-overlay.dts new file mode 100644 index 00000000..50703f01 --- /dev/null +++ b/qcom/ravelin-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin RUMI"; + compatible = "qcom,ravelin-rumi", "qcom,ravelin", "qcom,rumi"; + qcom,msm-id = <568 0x10000>; + qcom,board-id = <0x1000F 0>; +}; + diff --git a/qcom/ravelin-rumi.dts b/qcom/ravelin-rumi.dts new file mode 100644 index 00000000..1c1ac6d6 --- /dev/null +++ b/qcom/ravelin-rumi.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/memreserve/ 0x90000000 0x00010000; + +#include "ravelin.dtsi" +#include "ravelin-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin RUMI"; + compatible = "qcom,ravelin-rumi", "qcom,ravelin", "qcom,rumi"; + qcom,board-id = <0x1000F 0>; +}; + diff --git a/qcom/ravelin-rumi.dtsi b/qcom/ravelin-rumi.dtsi new file mode 100644 index 00000000..8b32a2fc --- /dev/null +++ b/qcom/ravelin-rumi.dtsi @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + timer { + clock-frequency = <500000>; + }; + + timer@17420000 { + clock-frequency = <500000>; + }; + + qcom,wdt@17410000 { + status = "disabled"; + }; + + usb_emuphy: phy@a784000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a784000 0x9500>; + + qcom,emu-init-seq = <0xfffff 0x4 + 0xffff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x000001A0 0x20 + 0x00100000 0x3c + 0x0 0x3c + 0x0 0x4>; + }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <4>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <4>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; +}; + +&SILVER_CPU_OFF { + status = "nok"; +}; + +&SILVER_CPU_RAIL_OFF { + status = "nok"; +}; + +&GOLD_CPU_OFF { + status = "nok"; +}; + +&GOLD_CPU_RAIL_OFF { + status = "nok"; +}; + +&CLUSTER_OFF { + status = "nok"; +}; + +&CX_RET { + status = "nok"; +}; + +&disp_rsc { + status = "nok"; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emuphy>, <&usb_nop_phy>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + }; + + +}; + +&qupv3_se7_2uart { + qcom,rumi_platform; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&L5B>; + vdda-pll-supply = <&L16B>; + vdda-phy-max-microamp = <85710>; + vdda-pll-max-microamp = <18330>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <2>; /* HS Rate-B */ + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L24B>; + vcc-max-microamp = <1056000>; + + vccq-supply = <&L13B>; + vccq-max-microamp = <750000>; + + vccq2-supply = <&L19B>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L13B>; + qcom,vddp-ref-clk-max-microamp = <70>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + + status = "ok"; +}; + +&sdhc_1 { + status = "ok"; + vdd-supply = <&L5E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + /delete-property/ mmc-ddr-1_8v; + /delete-property/ mmc-hs200-1_8v; + /delete-property/ mmc-hs400-1_8v; + /delete-property/ mmc-hs400-enhanced-strobe; + max-frequency = <100000000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&L24B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L28B>; + qcom,vdd-io-voltage-level = <2960000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + is_rumi; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; +}; + +&gcc { + clocks = <&bi_tcxo>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; +}; + +&camcc { + clocks = <&bi_tcxo>, + <&gcc GCC_CAMERA_AHB_CLK>; +}; + +&dispcc { + clocks = <&bi_tcxo>, <&bi_tcxo_ao>, + <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>; +}; + +&gpucc { + clocks = <&bi_tcxo>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; +}; + +&debugcc { + clocks = <&bi_tcxo>, + <&gcc 0>, <&camcc 0>, + <&dispcc 0>, <&gpucc 0>; +}; + +&rpmhcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmhcc_clocks"; +}; + +&cpufreq_hw { + clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>; +}; + +&tsens0 { + status = "disabled"; +}; + +&tsens1 { + status = "disabled"; +}; + +&pcie0 { + reg = <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x01c05000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", + "rumi"; + qcom,target-link-speed = <0x1>; + qcom,link-check-max-count = <200>; /* 1 sec */ + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; diff --git a/qcom/ravelin-stub-regulator.dtsi b/qcom/ravelin-stub-regulator.dtsi new file mode 100644 index 00000000..34b19d5b --- /dev/null +++ b/qcom/ravelin-stub-regulator.dtsi @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + VDD_MODEM_LEVEL: + S1B_LEVEL: + pm6450_s1_level: regulator-pm6450-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_MX_LEVEL: + S2B_LEVEL: + pm6450_s2_level: regulator-pm6450_s2_level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s2_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL: + S5B_LEVEL: + pm6450_s5_level: regulator-pm6450-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + VDD_EBI_LEVEL: + S6B_LEVEL: + pm6450_s6: regulator-pm6450-s6-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s6_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + S7B: + pm6450_s7: regulator-pm6450-s7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + S8B: + pm6450_s8: regulator-pm6450-s8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <598000>; + regulator-max-microvolt = <1654000>; + }; + + S9B: + pm6450_s9: regulator-pm6450-s9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_s9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L1B: + pm6450_l1: regulator-pm6450-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l1"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <650000>; + }; + + VDD_LPI_CX_LEVEL: + L2B_LEVEL: + pm6450_l2_level: regulator-pm6450-l2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l2_level"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L3B: + pm6450_l3: regulator-pm6450-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l3"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + L5B: + pm6450_l5: regulator-pm6450-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l5"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + L6B: + pm6450_l6: regulator-pm6450-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l6"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + L7B: + pm6450_l7: regulator-pm6450-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l7"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + VDD_LPI_MX_LEVEL: + L8B_LEVEL: + pm6450_l8_level: regulator-pm6450-l8-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l8_level"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + }; + + L9B: + pm6450_l9: regulator-pm6450-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l9"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + L10B: + pm6450_l10: regulator-pm6450-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l10"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <901000>; + }; + + L11B: + pm6450_l11: regulator-pm6450-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l11"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <888000>; + }; + + L12B: + pm6450_l12: regulator-pm6450-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l12"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1139000>; + regulator-max-microvolt = <1236000>; + }; + + L13B: + pm6450_l13: regulator-pm6450-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l13"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + L14B: + pm6450_l14: regulator-pm6450-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l14"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + L15B: + pm6450_l15: regulator-pm6450-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l15"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + L16B: + pm6450_l16: regulator-pm6450-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l16"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + L17B: + pm6450_l17: regulator-pm6450-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l17"; + qcom,hpm-min-load = <30000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + L18B: + pm6450_l18: regulator-pm6450-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + L19B: + pm6450_l19: regulator-pm6450-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L20B: + pm6450_l20: regulator-pm6450-l20 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l20"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L21B: + pm6450_l21: regulator-pm6450-l21 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l21"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + L22B: + pm6450_l22: regulator-pm6450-l22 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l22"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1550000>; + regulator-max-microvolt = <2000000>; + }; + + L23B: + pm6450_l23: regulator-pm6450-l23 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l23"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + L24B: + pm6450_l24: regulator-pm6450-l24 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l24"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L25B: + pm6450_l25: regulator-pm6450-l25 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l25"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L26B: + pm6450_l26: regulator-pm6450-l26 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l26"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L27B: + pm6450_l27: regulator-pm6450-l27 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l27"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L28B: + pm6450_l28: regulator-pm6450-l28 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6450_l28"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + }; + + L1M: pm8010m_l1: regulator-pm8010m-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + qcom,hpm-min-load = <30000>; + }; + + L2M: pm8010m_l2: regulator-pm8010m-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l2"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,hpm-min-load = <30000>; + }; + + L3M: pm8010m_l3: regulator-pm8010m-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l3"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,hpm-min-load = <30000>; + }; + + L4M: pm8010m_l4: regulator-pm8010m-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l4"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,hpm-min-load = <30000>; + }; + + L6M: pm8010m_l6: regulator-pm8010m-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l6"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,hpm-min-load = <30000>; + }; + + L7M: pm8010m_l7: regulator-pm8010m-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010m_l7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,hpm-min-load = <30000>; + }; + + L1N: pm8010n_l1: regulator-pm8010n-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l1"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,hpm-min-load = <30000>; + }; + + L3N: pm8010n_l3: regulator-pm8010n-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l3"; + regulator-min-microvolt = <1792000>; + regulator-max-microvolt = <1900000>; + qcom,hpm-min-load = <30000>; + }; + + L4N: pm8010n_l4: regulator-pm8010n-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l4"; + regulator-min-microvolt = <1792000>; + regulator-max-microvolt = <1900000>; + qcom,hpm-min-load = <30000>; + }; + + L6N: pm8010n_l6: regulator-pm8010n-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010n_l6"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,hpm-min-load = <30000>; + }; + + L1E: pm8010e_l1: regulator-pm8010e-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010e_l1"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + qcom,hpm-min-load = <30000>; + }; + + L4E: pm8010e_l4: regulator-pm8010e-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010e_l4"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3312000>; + qcom,hpm-min-load = <30000>; + }; + + L5E: pm8010e_l5: regulator-pm8010e-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8010e_l5"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + qcom,hpm-min-load = <30000>; + }; +}; diff --git a/qcom/ravelin-thermal-modem.dtsi b/qcom/ravelin-thermal-modem.dtsi new file mode 100644 index 00000000..f0827432 --- /dev/null +++ b/qcom/ravelin-thermal-modem.dtsi @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = ; + + modem_lte_dsc: modem_lte_dsc { + qcom,qmi-dev-name = "modem_lte_dsc"; + #cooling-cells = <2>; + }; + + modem_lte_sub1_dsc: modem_lte_sub1_dsc { + qcom,qmi-dev-name = "modem_lte_sub1_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_dsc: modem_nr_dsc { + qcom,qmi-dev-name = "modem_nr_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_sub1_dsc: modem_nr_sub1_dsc { + qcom,qmi-dev-name = "modem_nr_sub1_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_scg_dsc: modem_nr_scg_dsc { + qcom,qmi-dev-name = "modem_nr_scg_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_scg_sub1_dsc: modem_nr_scg_sub1_dsc { + qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc"; + #cooling-cells = <2>; + }; + + sdr0_lte_dsc: sdr0_lte_dsc { + qcom,qmi-dev-name = "sdr0_lte_dsc"; + #cooling-cells = <2>; + }; + + sdr1_lte_dsc: sdr1_lte_dsc { + qcom,qmi-dev-name = "sdr1_lte_dsc"; + #cooling-cells = <2>; + }; + + sdr0_nr_dsc: sdr0_nr_dsc { + qcom,qmi-dev-name = "sdr0_nr_dsc"; + #cooling-cells = <2>; + }; + + sdr1_nr_dsc: sdr1_nr_dsc { + qcom,qmi-dev-name = "sdr1_nr_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr0_dsc: pa_lte_sdr0_dsc { + qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr1_dsc: pa_lte_sdr1_dsc { + qcom,qmi-dev-name = "pa_lte_sdr1_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr0_sub1_dsc: pa_lte_sdr0_sub1_dsc { + qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr1_sub1_dsc: pa_lte_sdr1_sub1_dsc { + qcom,qmi-dev-name = "pa_lte_sdr1_sub1_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr0_dsc: pa_nr_sdr0_dsc { + qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr1_dsc: pa_nr_sdr1_dsc { + qcom,qmi-dev-name = "pa_nr_sdr1_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr0_sub1_dsc: pa_nr_sdr0_sub1_dsc { + qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr1_sub1_dsc: pa_nr_sdr1_sub1_dsc { + qcom,qmi-dev-name = "pa_nr_sdr1_sub1_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr0_scg_dsc: pa_nr_sdr0_scg { + qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr1_scg_dsc: pa_nr_sdr1_scg { + qcom,qmi-dev-name = "pa_nr_sdr1_scg_dsc"; + #cooling-cells = <2>; + }; + + qmi_wlan: wlan { + qcom,qmi-dev-name = "wlan"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; + + qmi_sensor: qmi-ts-sensors { + compatible = "qcom,qmi-sensors"; + #thermal-sensor-cells = <1>; + + modem { + qcom,instance-id = ; + qcom,qmi-sensor-names = "pa", + "pa_1", + "modem_bcl_warn", + "modem_cfg", + "lte_cc", + "mcg_fr1_cc", + "scg_fr1_cc", + "sub1_modem_cfg", + "sub1_lte_cc", + "sub1_mcg_fr1_cc", + "sub1_scg_fr1_cc", + "sdr0_pa0", + "sdr1_pa0", + "sdr0", + "sdr1"; + }; + }; +}; + +&thermal_zones { + pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA_1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + bcl-warn { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BCL_WARN)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-cfg { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + lte-cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mcg-fr1-cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM4)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + scg-fr1-cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM6)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1-modem-cfg { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_MODEM_CFG)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1-lte-cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_LTE_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_mcg_fr1_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_MCG_FR1_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_scg_fr1_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_SCG_FR1_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr0-pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr1-pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/ravelin-thermal-overlay.dtsi b/qcom/ravelin-thermal-overlay.dtsi new file mode 100644 index 00000000..2f260292 --- /dev/null +++ b/qcom/ravelin-thermal-overlay.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&thermal_zones { + pm6450_tz { + cooling-maps { + pm6450_lte { + trip = <&pm6450_trip0>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + pm6450_nr { + trip = <&pm6450_trip0>; + cooling-device = <&modem_nr_scg_dsc 255 255>; + }; + + pm6450_cpu0 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu0_pause 1 1>; + }; + + pm6450_cpu1 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu1_pause 1 1>; + }; + + pm6450_cpu2 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu2_pause 1 1>; + }; + + pm6450_cpu3 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu3_pause 1 1>; + }; + + pm6450_cpu4 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu4_pause 1 1>; + }; + + pm6450_cpu5 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu5_pause 1 1>; + }; + + pm6450_cpu6_7 { + trip = <&pm6450_trip0>; + cooling-device = <&cpu_6_7_pause 1 1>; + }; + + pm6450_gpu { + trip = <&pm6450_trip0>; + cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/qcom/ravelin-thermal.dtsi b/qcom/ravelin-thermal.dtsi new file mode 100644 index 00000000..e0f26fff --- /dev/null +++ b/qcom/ravelin-thermal.dtsi @@ -0,0 +1,951 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&msm_gpu { + #cooling-cells = <2>; +}; + +&soc { + tsens0: thermal-sensor@c263000 { + compatible = "qcom,tsens-v2"; + reg = <0x0c263000 0x1ff>, /* TM */ + <0x0c222000 0x1ff>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + , + ; + interrupt-names = "uplow","critical", "cold"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,tsens-v2"; + reg = <0x0c265000 0x1ff>, /* TM */ + <0x0c223000 0x1ff>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + , + ; + interrupt-names = "uplow","critical", "cold"; + #thermal-sensor-cells = <1>; + }; + + qcom,cpu-pause { + compatible = "qcom,thermal-pause"; + + cpu0_pause: cpu0-pause { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "thermal-pause-1"; + #cooling-cells = <2>; + }; + + cpu1_pause: cpu1-pause { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "thermal-pause-2"; + #cooling-cells = <2>; + }; + + cpu2_pause: cpu2-pause { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "thermal-pause-4"; + #cooling-cells = <2>; + }; + + cpu3_pause: cpu3-pause { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "thermal-pause-8"; + #cooling-cells = <2>; + }; + + cpu4_pause: cpu4-pause { + qcom,cpus = <&CPU4>; + qcom,cdev-alias = "thermal-pause-10"; + #cooling-cells = <2>; + }; + + cpu5_pause: cpu5-pause { + qcom,cpus = <&CPU5>; + qcom,cdev-alias = "thermal-pause-20"; + #cooling-cells = <2>; + }; + + cpu6_pause: cpu6-pause { + qcom,cpus = <&CPU6>; + qcom,cdev-alias = "thermal-pause-40"; + #cooling-cells = <2>; + }; + + cpu7_pause: cpu7-pause { + qcom,cpus = <&CPU7>; + qcom,cdev-alias = "thermal-pause-80"; + #cooling-cells = <2>; + }; + + cpu_6_7_pause: cpu-6-7-pause { + qcom,cpus = <&CPU6 &CPU7>; + qcom,cdev-alias = "thermal-pause-C0"; + #cooling-cells = <2>; + }; + + /* Thermal-engine cooling devices */ + pause-cpu0 { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "pause-cpu0"; + }; + + pause-cpu1 { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "pause-cpu1"; + }; + + pause-cpu2 { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "pause-cpu2"; + }; + + pause-cpu3 { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "pause-cpu3"; + }; + + pause-cpu4 { + qcom,cpus = <&CPU4>; + qcom,cdev-alias = "pause-cpu4"; + }; + + pause-cpu5 { + qcom,cpus = <&CPU5>; + qcom,cdev-alias = "pause-cpu5"; + }; + + pause-cpu6 { + qcom,cpus = <&CPU6>; + qcom,cdev-alias = "pause-cpu6"; + }; + + pause-cpu7 { + qcom,cpus = <&CPU7>; + qcom,cdev-alias = "pause-cpu7"; + }; + }; + + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + qcom,cdev-alias = "cpu-hotplug0"; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + qcom,cdev-alias = "cpu-hotplug1"; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + qcom,cdev-alias = "cpu-hotplug2"; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + qcom,cdev-alias = "cpu-hotplug3"; + #cooling-cells = <2>; + }; + + cpu4_hotplug: cpu4-hotplug { + qcom,cpu = <&CPU4>; + qcom,cdev-alias = "cpu-hotplug4"; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + qcom,cdev-alias = "cpu-hotplug5"; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + qcom,cdev-alias = "cpu-hotplug6"; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + qcom,cdev-alias = "cpu-hotplug7"; + #cooling-cells = <2>; + }; + }; + + thermal_ddr_freq_table: thermal-ddr-freq-table { + qcom,freq-tbl = < 2092800 >; + }; + + ddr_cdev: qcom,ddr-cdev { + compatible = "qcom,ddr-cooling-device"; + #cooling-cells = <2>; + qcom,freq-table = <&thermal_ddr_freq_table>; + qcom,bus-width = <4>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + }; + + qcom,cpufreq-cdev { + compatible = "qcom,cpufreq-cdev"; + cpu-cluster0 { + qcom,cpus = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + }; + + cpu-cluster1 { + qcom,cpus = <&CPU6 &CPU7>; + }; + }; + + qcom,devfreq-cdev { + compatible = "qcom,devfreq-cdev"; + qcom,devfreq = <&msm_gpu>; + }; + + qcom,userspace-cdev { + compatible = "qcom,userspace-cooling-devices"; + + display_fps: display-fps { + qcom,max-level = <3>; + #cooling-cells = <2>; + }; + }; + + cx_sdpm@634000 { + compatible = "qcom,sdpm"; + reg = <0x00634000 0x1000>; + clock-names = "gpu_cc_gx_gfx3d", + "cam_cc_camnoc_axi", + "cam_cc_bps", + "gcc_video_venus", + "disp_cc_mdss_mdp"; + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_BPS_CLK_SRC>, + <&gcc GCC_VIDEO_VENUS_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + csr-id = <0 1 2 6 7>; + }; + + cx_pe: cx_rdpm_pe@635000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x635000 0x1000>; + interrupts = ; + }; +}; + +#include "ravelin-thermal-modem.dtsi" + +&thermal_zones { + aoss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu0_emerg: cpu0-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu00_cdev { + trip = <&cpu0_emerg>; + cooling-device = <&cpu0_pause 1 1>; + }; + }; + }; + + cpu-0-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu1_emerg: cpu1-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu01_cdev { + trip = <&cpu1_emerg>; + cooling-device = <&cpu1_pause 1 1>; + }; + }; + }; + + cpu-0-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu2_emerg: cpu2-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu02_cdev { + trip = <&cpu2_emerg>; + cooling-device = <&cpu2_pause 1 1>; + }; + }; + }; + + cpu-0-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu3_emerg: cpu3-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu03_cdev { + trip = <&cpu3_emerg>; + cooling-device = <&cpu3_pause 1 1>; + }; + }; + }; + + cpu-0-4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu4_emerg: cpu4-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu04_cdev { + trip = <&cpu4_emerg>; + cooling-device = <&cpu4_pause 1 1>; + }; + }; + }; + + cpu-0-5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu5_emerg: cpu5-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu05_cdev { + trip = <&cpu5_emerg>; + cooling-device = <&cpu5_pause 1 1>; + }; + }; + }; + + cpuss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu6_emerg0: cpu6-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu10_cdev { + trip = <&cpu6_emerg0>; + cooling-device = <&cpu6_pause 1 1>; + }; + }; + }; + + cpu-1-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu6_emerg1: cpu6-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu11_cdev { + trip = <&cpu6_emerg1>; + cooling-device = <&cpu6_pause 1 1>; + }; + }; + }; + + cpu-1-2 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu7_emerg0: cpu7-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu12_cdev { + trip = <&cpu7_emerg0>; + cooling-device = <&cpu7_pause 1 1>; + }; + }; + }; + + cpu-1-3 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu7_emerg1: cpu7-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu13_cdev { + trip = <&cpu7_emerg1>; + cooling-device = <&cpu7_pause 1 1>; + }; + }; + }; + + gpuss { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpu_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + camera { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddr { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + ddr_config0: ddr0-config { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + ddr_cdev { + trip = <&ddr_config0>; + cooling-device = <&ddr_cdev 1 1>; + }; + }; + }; + + mdmss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + zeroc-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 128>; + trips { + thermal-engine-config { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + min_temp_0_trip: cold-trip { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + zeroc-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 128>; + trips { + thermal-engine-config { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + min_temp_1_trip: cold-trip { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + cx-pe { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&cx_pe>; + + trips { + cx_pe_config1: cx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&cx_pe_config1>; + cooling-device = <&msm_gpu 3 3>; + }; + + }; + }; +}; diff --git a/qcom/ravelin-usb.dtsi b/qcom/ravelin-usb.dtsi new file mode 100644 index 00000000..3038be02 --- /dev/null +++ b/qcom/ravelin-usb.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + + qcom,use-pdc-interrupts; + + qcom,core-clk-rate = <133333333>; + qcom,core-clk-rate-hs = <66666667>; + qcom,pm-qos-latency = <2>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + + usb-role-switch; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre2_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>; + + extcon = <&eud>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd800>; + + iommus = <&apps_smmu 0x540 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; + + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + tx-fifo-resize; + dr_mode = "otg"; + maximum-speed = "super-speed"; + usb-role-switch; + }; + + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; + }; + + /* USB port related High Speed PHY */ + usb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x11c>, + <0x088e2000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L5B>; + vdda18-supply = <&L23B>; + vdda33-supply = <&L25B>; + qcom,vdd-voltage-level = <0 880000 920000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EUSB3_0_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L16B>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_0_CLKREF_EN>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "com_aux_clk", "ref_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_default>; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x100f 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; + +}; diff --git a/qcom/ravelin-wcn6750.dtsi b/qcom/ravelin-wcn6750.dtsi new file mode 100644 index 00000000..1944911e --- /dev/null +++ b/qcom/ravelin-wcn6750.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,smp2p-wpss { + smp2p_wlan_2_in: qcom,smp2p-wlan-2-in { + qcom,entry-name = "wlan_soc_wake"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_2_out: qcom,smp2p-wlan-2-out { + qcom,entry-name = "wlan_soc_wake"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_wlan_3_out: qcom,smp2p-wlan-3-out { + qcom,entry-name = "wlan_ep_power_save"; + #qcom,smem-state-cells = <1>; + }; + }; + + wpss_pas: remoteproc-wpss@8a00000 { + firmware-name = "qca6750/wpss.mdt"; + }; + + icnss2: qcom,wcn6750 { + status = "disabled"; + compatible = "qcom,wcn6750"; + reg = <0x17210040 0x0>, + <0xb0000000 0x10000>; + reg-names = "msi_addr", "smmu_iova_ipa"; + qcom,rproc-handle = <&wpss_pas>; + iommus = <&apps_smmu 0x1400 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + dma-coherent; + qcom,fw-prefix; + qcom,wlan; + tsens = "quiet-therm"; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + vdd-cx-mx-supply = <&S7B>; + qcom,vdd-cx-mx-config = <1010000 1120000 0 0 1>; + vdd-1.8-xo-supply = <&S9B>; + qcom,vdd-1.8-xo-config = <1856000 2040000 0 0 0>; + vdd-1.3-rfa-supply = <&S8B>; + qcom,vdd-1.3-rfa-config = <1250000 1352000 0 0 0>; + + qcom,smem-states = <&smp2p_wlan_1_out 0>, + <&smp2p_wlan_2_out 0>, + <&smp2p_wlan_3_out 0>; + qcom,smem-state-names = "wlan-smp2p-out", + "wlan-soc-wake-smp2p-out", + "wlan-ep-powersave-smp2p-out"; + + icnss_cdev_apss: qcom,icnss_cdev1 { + #cooling-cells = <2>; + }; + + icnss_cdev_wpss: qcom,icnss_cdev2 { + #cooling-cells = <2>; + }; + + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + + qcom,smp2p_map_wlan_2_in { + interrupts-extended = <&smp2p_wlan_2_in 0 0>; + interrupt-names = "qcom,smp2p-soc-wake-ack"; + }; + }; + +}; + diff --git a/qcom/ravelin.dts b/qcom/ravelin.dts new file mode 100644 index 00000000..fd772285 --- /dev/null +++ b/qcom/ravelin.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SoC"; + compatible = "qcom,ravelin"; + qcom,board-id = <0 0>; +}; + diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi new file mode 100644 index 00000000..03f7f28e --- /dev/null +++ b/qcom/ravelin.dtsi @@ -0,0 +1,2569 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. Ravelin"; + compatible = "qcom,ravelin"; + qcom,msm-id = <568 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen: chosen { + stdout-path = "/soc/qcom,qup_uart@a88000:115200n8"; + bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat"; + }; + + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + ddr-regions { }; + + reserved_memory: reserved-memory { }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + mboxes = <&qmp_aop 0>; + }; + + aliases: aliases { + serial0 = &qupv3_se7_2uart; /* Debug UART */ + serial1 = &qupv3_se0_2uart; /* HST debug UART */ + hsuart0 = &qupv3_se2_4uart; + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + }; + + mmio_sram: mmio-sram@17D09100 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + reg = <0x0 0x17D09100 0x0 0x200>; + ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scp-shmem"; + reg = <0x0 0x0 0x0 0x200>; + }; + }; + + firmware: firmware {}; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 8>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 8>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 8>; + next-level-cache = <&L2_2>; + #cooling-cells = <2>; + L2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 8>; + next-level-cache = <&L2_3>; + #cooling-cells = <2>; + L2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + next-level-cache = <&L2_4>; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 0 8>; + L2_4: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0 8>; + next-level-cache = <&L2_5>; + #cooling-cells = <2>; + L2_5: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + capacity-dmips-mhz = <1945>; + dynamic-power-coefficient = <483>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1 8>; + next-level-cache = <&L2_6>; + #cooling-cells = <2>; + L2_6: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + capacity-dmips-mhz = <1945>; + dynamic-power-coefficient = <483>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1 8>; + next-level-cache = <&L2_7>; + #cooling-cells = <2>; + L2_7: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + SILVER_CPU_OFF: silver-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <350>; + exit-latency-us = <900>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + SILVER_CPU_RAIL_OFF: silver-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_CPU_OFF: gold-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <400>; + exit-latency-us = <1550>; + min-residency-us = <2207>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_CPU_RAIL_OFF: gold-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + CLUSTER_OFF: cluster-d4 { /* D4 */ + compatible = "domain-idle-state"; + idle-state-name = "l3-off"; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + arm,psci-suspend-param = <0x41000044>; + }; + + CX_RET: cx-ret { /* Cx Ret */ + compatible = "domain-idle-state"; + idle-state-name = "cx-ret"; + entry-latency-us = <1561>; + exit-latency-us = <2801>; + min-residency-us = <8550>; + arm,psci-suspend-param = <0x41003344>; + }; + }; + + soc: soc { }; + +}; + +#include "msm-arm-smmu-ravelin.dtsi" +#include "ravelin-dma-heaps.dtsi" +#include "ravelin-reserved-memory.dtsi" +#include "ravelin-dma-heaps.dtsi" +#include "ravelin-usb.dtsi" +#include "ravelin-coresight.dtsi" +#include "ravelin-debug.dtsi" + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + ramoops_mem: ramoops_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x200000>; + no-map; + }; + + va_md_mem: va_md_mem_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; + reusable; + size = <0 0x1000000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + adsp_mem_heap: adsp_heap_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1C00000>; + }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + size = <0x0 0x5c00000>; + alignment = <0x0 0x400000>; + }; +}; + +&firmware { + qcom_scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17200000 0x10000>, /* GICD */ + <0x17260000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + wdog: qcom,wdt@17410000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17410000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x17a00000 0x10000>, + <0x17a10000 0x10000>, + <0x17a20000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + + qcom,drv-count = <3>; + power-domains = <&CLUSTER_PD>; + + apps_rsc_drv2: drv@2 { + qcom,drv-id = <2>; + qcom,tcs-offset = <0xd00>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + rpmhcc: qcom,rpmhclk { + compatible = "qcom,sm4450-rpmh-clk"; + #clock-cells = <1>; + }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + }; + }; + + bluetooth: bt_wcn3990 { + compatible = "qcom,wcn3990"; + qcom,bt-sw-ctrl-gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>; + qcom,bt-vdd-io-supply = <&L21B>; /* IO */ + qcom,bt-vdd-core-supply = <&L14B>; /* RFA */ + qcom,bt-vdd-pa-supply = <&L7E>; /* CH0 */ + qcom,bt-vdd-xtal-supply = <&L23B>; /* XO */ + + qcom,bt-vdd-io-config = <1700000 1900000 1 0>; + qcom,bt-vdd-core-config = <1304000 1304000 1 0>; + qcom,bt-vdd-pa-config = <3000000 3312000 1 0>; + qcom,bt-vdd-xtal-config = <1700000 1900000 1 0>; + }; + + disp_rsc: rsc@af20000 { + lable = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + interrupts = ; + clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + qcom,drv-count = <1>; + + disp_rsc_drv0: drv@0 { + qcom,tcs-offset = <0x1c00>; + qcom,drv-id = <0>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + qcom,no-amc; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,ravelin-pdc", "qcom,pdc"; + reg = <0xb220000 0x30000>, <0x174000f0 0x64>; + reg-names = "pdc-interrupt-base", "apps-shared-spi-cfg"; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, + <126 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD4: cpu-pd4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD5: cpu-pd5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD6: cpu-pd6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD7: cpu-pd7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_OFF &CX_RET>; + }; + }; + + slimbam: bamdma@3304000 { + compatible = "qcom,bam-v1.7.0"; + qcom,controlled-remotely; + reg = <0x3304000 0x20000>, <0x326b000 0x1000>; + reg-names = "bam", "bam_remote_mem"; + num-channels = <31>; + interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,num-ees = <2>; + }; + + slim_msm: slim@3340000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0x3340000 0x2C000>, <0x326a000 0x1000>; + reg-names = "ctrl", "slimbus_remote_mem"; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x440>; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + }; + + cluster-device { + compatible = "qcom,lpm-cluster-dev"; + power-domains = <&CLUSTER_PD>; + }; + + cpuss-sleep-stats@17800054 { + compatible = "qcom,cpuss-sleep-stats"; + reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>, + <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>, + <0x17860054 0x4>, <0x17870054 0x4>, <0x17880098 0x4>, + <0x178C0000 0x10000>; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", + "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", + "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", + "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", + "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; + num-cpus = <8>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats-v3"; + reg = <0xc3f0000 0x400>; + ss-name = "modem", "adsp", "adsp_island", + "apss", "wpss"; + qcom,qmp = <&aoss_qmp>; + }; + + sys-pm-vx@c320000 { + compatible = "qcom,sys-pm-violators", "qcom,sys-pm-ravelin"; + reg = <0xc320000 0x0400>; + qcom,qmp = <&aoss_qmp>; + }; + + memtimer: timer@17420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17420000 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x17423000 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x17425000 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x17427000 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x17429000 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x1742b000 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x1742d000 0x1000>; + status = "disabled"; + }; + }; + + cpucp: qcom,cpucp@17400000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,cpucp"; + reg = <0x17400000 0x10>, + <0x17d90000 0x2000>; + reg-names = "rx", "tx"; + #mbox-cells = <1>; + interrupts = ; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&cpucp 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_pmu: protocol@86 { + reg = <0x86>; + #clock-cells = <1>; + }; + + scmi_plh: protocol@81 { + reg = <0x81>; + #clock-cells = <1>; + }; + + scmi_cpufreqstat: protocol@84 { + reg = <0x84>; + #clock-cells = <1>; + }; + + scmi_shared_rail: protocol@88 { + reg = <0x88>; + #clock-cells = <1>; + }; + }; + + cpucp_log: qcom,cpucp_log@17d09c00 { + compatible = "qcom,cpucp-log"; + reg = <0x17d09c00 0x200>, <0x17d09e00 0x200>; + mboxes = <&cpucp 1>; + }; + + qcom,secure-buffer { + compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; + }; + + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "supplier"; + qcom,vmid = <3>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + qcom_tzlog: tz-log@146AA720 { + compatible = "qcom,tz-log"; + reg = <0x146AA720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + tmecrashdump-address-offset = <0x808a0000>; + status = "ok"; + }; + + qcom_qseecom: qseecom@c1700000 { + memory-region = <&qseecom_mem>; + qseecom_mem = <&qseecom_mem>; + qseecom_ta_mem = <&qseecom_ta_mem>; + user_contig_mem = <&user_contig_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + ipcc_mproc: qcom,ipcc@ed18000 { + compatible = "qcom,ipcc"; + reg = <0xed18000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + pcie_0_pipe_clk: pcie_0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,sm4450-camcc", "syscon"; + reg = <0xade0000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm4450-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,sm4450-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", "sleep_clk", + "pcie_0_pipe_clk", "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm4450-gpucc", "syscon"; + reg = <0x3d90000 0xa000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "bi_tcxo", "gpll0_out_main", + "gpll0_out_main_div", "gcc_gpu_snoc_dvm_gfx_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apsscc: syscon@17aa0000 { + compatible = "syscon"; + reg = <0x17aa0000 0x1c>; + }; + + mccc: syscon@190ba000 { + compatible = "syscon"; + reg = <0x190ba000 0x54>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,sm4450-debugcc"; + qcom,gcc = <&gcc>; + qcom,dispcc = <&dispcc>; + qcom,camcc = <&camcc>; + qcom,gpucc = <&gpucc>; + qcom,apsscc = <&apsscc>; + qcom,mccc = <&mccc>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc 0>, + <&camcc 0>, + <&dispcc 0>, + <&gpucc 0>; + clock-names = "xo_clk_src", + "gcc", + "camcc", + "dispcc", + "gpucc"; + #clock-cells = <1>; + }; + + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-epss"; + reg = <0x17d91000 0x1000>, <0x17d92000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + qcom,lut-row-size = <4>; + qcom,skip-enable-check; + interrupts = , + ; + interrupt-names = "dcvsh0_int", "dcvsh1_int"; + #freq-domain-cells = <2>; + }; + + qcom,cpufreq-hw-debug { + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; + }; + + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_out: qcom,smp2p-wlan-1-out { + qcom,entry-name = "wlan"; + #qcom,smem-state-cells = <1>; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,aoss-qmp"; + reg = <0xc300000 0x400>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + qmp_aop: qcom,qmp-aop { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + qmp_tme: qcom,qmp-tme { + compatible = "qcom,qmp-mbox"; + qcom,remote-pid = <14>; + mboxes = <&ipcc_mproc IPCC_CLIENT_TME + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "tme_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "tme"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qcom,tmecom-qmp-client { + compatible = "qcom,tmecom-qmp-client"; + mboxes = <&qmp_tme 0>; + mbox-names = "tmecom"; + label = "tmecom"; + depends-on-supply = <&qmp_tme>; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + interconnect-names = "data_path"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x0480 0x0>, + <&apps_smmu 0x0481 0x0>; + qcom,iommu-dma = "atomic"; + dma-coherent; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x0481 0x0>; + dma-coherent; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x0483 0x0>; + qcom,iommu-vmid = <0x9>; + qcom,secure-context-bank; + dma-coherent; + }; + }; + + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe10>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_aux_clk", "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_0_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x8000>, + <0x1d90000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre2_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 136 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + iommus = <&apps_smmu 0x580 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + + status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <44>; + perf; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; + + qcom_pmu: qcom,pmu { + compatible = "qcom,pmu"; + reg = < 0x17D09300 0x300>; + reg-names = "pmu-base"; + qcom,pmu-events-tbl = + < 0x0008 0xFF 0xFF 0x02 >, + < 0x0011 0xFF 0xFF 0x00 >, + < 0x0017 0xFF 0xFF 0xFF >, + < 0x002A 0xFF 0xFF 0xFF >, + < 0x4005 0xC0 0xFF 0xFF >; + }; + + ddr_freq_table: ddr-freq-table { + ddr4 { + qcom,ddr-type = <7>; + qcom,freq-tbl = + < 547000 >, + < 768000 >, + < 1017000 >, + < 1353600 >, + < 1555000 >, + < 1708000 >, + < 2092000 >; + }; + + ddr5 { + qcom,ddr-type = <8>; + qcom,freq-tbl = + < 547000 >, + < 768000 >, + < 1555000 >, + < 1708000 >, + < 2092000 >, + < 2736000 >, + < 3196000 >; + }; + }; + + ddrqos_freq_table: ddrqos-freq-table { + qcom,freq-tbl = + < 0 >, + < 1 >; + }; + + qcom_dcvs: qcom,dcvs { + compatible = "qcom,dcvs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom_l3_dcvs_hw: l3 { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <2>; + qcom,bus-width = <32>; + reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>; + reg-names = "l3-base", "l3tbl-base"; + + l3_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + qcom,shared-offset = <0x0090>; + }; + }; + + qcom_ddr_dcvs_hw: ddr { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <0>; + qcom,bus-width = <4>; + qcom,freq-tbl = <&ddr_freq_table>; + + ddr_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &mc_virt SLAVE_EBI1>; + }; + }; + + qcom_ddrqos_dcvs_hw: ddrqos { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <3>; + qcom,bus-width = <1>; + qcom,freq-tbl = <&ddrqos_freq_table>; + + ddrqos_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + qcom_memlat: qcom,memlat { + compatible = "qcom,memlat"; + qcom,be-stall-ev = <0x4005>; + + ddr { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + qcom,sampling-path = <&ddr_dcvs_sp>; + qcom,miss-ev = <0x2A>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1094400 547000 >, + < 1478400 768000 >, + < 1804800 1017000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1094400 547000 >, + < 1478400 768000 >, + < 1804800 1555000 >; + }; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 960000 547000 >, + < 1190400 1017000 >, + < 1497600 1353600 >, + < 1651200 1555000 >, + < 2131200 1708000 >, + < 2400000 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 960000 547000 >, + < 1651200 1555000 >, + < 1900800 1708000 >, + < 2131200 2092000 >, + < 2400000 3196000 >; + }; + }; + + silver-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,sampling-enabled; + qcom,compute-mon; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1478400 547000 >, + < 1804800 768000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1478400 547000 >, + < 1804800 768000 >; + }; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,sampling-enabled; + qcom,compute-mon; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1190400 547000 >, + < 1497600 768000 >, + < 1651200 1017000 >, + < 1900800 1555000 >, + < 2131200 1708000 >, + < 2400000 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1190400 547000 >, + < 1497600 768000 >, + < 1651200 1017000 >, + < 2054400 1555000 >, + < 2131200 1708000 >, + < 2400000 2092000 >; + }; + }; + + }; + + l3 { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_l3_dcvs_hw>; + qcom,sampling-path = <&l3_dcvs_sp>; + qcom,miss-ev = <0x17>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cpufreq-memfreq-tbl = + < 499200 307200 >, + < 672000 556800 >, + < 806400 652800 >, + < 921600 825600 >, + < 1094400 940800 >, + < 1286400 1075200 >, + < 1478400 1209600 >, + < 1632000 1305600 >, + < 1804800 1440000 >; + qcom,sampling-enabled; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 691200 307200 >, + < 960000 556800 >, + < 1190400 825600 >, + < 1344000 940800 >, + < 1651200 1209600 >, + < 1900800 1305600 >, + < 2054400 1401600 >, + < 2208000 1440000 >; + qcom,sampling-enabled; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2054400 307200 >, + < 2361600 1401600 >; + qcom,sampling-enabled; + qcom,compute-mon; + }; + + }; + + ddrqos { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddrqos_dcvs_hw>; + qcom,sampling-path = <&ddrqos_dcvs_sp>; + qcom,miss-ev = <0x2A>; + + ddrqos_gold_lat: gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2300000 0 >, + < 3000000 1 >; + qcom,sampling-enabled; + }; + + }; + }; + + bwmon_ddr: qcom,bwmon-ddr@19091000 { + compatible = "qcom,bwmon5"; + reg = <0x19091000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + }; + + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <1600000 280000>; + opp-avg-kBps = <104000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <5600000 1500000>; + opp-avg-kBps = <400000 0>; + }; + }; + + sdhc_1: sdhci@7C4000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, + <0x007C8000 0x8000>, <0x007D0000 0x9000>; + reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <8>; + non-removable; + supports-cqe; + + no-sd; + no-sdio; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + cap-mmc-hw-reset; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F642C 0x0 0x01 + 0x2C010800 0x80040868>; + + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + + iommus = <&apps_smmu 0x560 0x0>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + + interconnects = <&aggre2_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDC1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc1_opp_table>; + + qos0 { + mask = <0x03>; + vote = <44>; + }; + + qos1 { + mask = <0x3f>; + vote = <44>; + }; + }; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <1600000 280000>; + opp-avg-kBps = <50000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <5600000 1500000>; + opp-avg-kBps = <104000 0>; + }; + }; + + sdhc_2: sdhci@8804000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + no-sdio; + no-mmc; + qcom,restore-after-cx-collapse; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642C 0x0 0x10 + 0x2C010800 0x80040868>; + + iommus = <&apps_smmu 0x140 0x0>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + + interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc2_opp_table>; + + qos0 { + mask = <0x03>; + vote = <44>; + }; + + qos1 { + mask = <0x3f>; + vote = <44>; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + msm_gpu: qcom,kgsl-3d0@3d00000 { }; + + qcom,msm-imem@146aa000 { + compatible = "qcom,msm-imem"; + ranges = <0x0 0x146aa000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + qcom_ramoops { + compatible = "qcom,ramoops"; + memory-region = <&ramoops_mem>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + logbuf: qcom,logbuf-vendor-hooks { + compatible = "qcom,logbuf-vendor-hooks"; + }; + + mini_dump_node { + compatible = "qcom,minidump"; + status = "ok"; + }; + + va_mini_dump { + compatible = "qcom,va-minidump"; + memory-region = <&va_md_mem>; + status = "ok"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem_heap>; + restrict-access; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + qcom,rpc-latency-us = <235>; + qcom,fastrpc-gids = <2908>; + qcom,qos-cores = <0 1 2 3 4 5>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1003 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1004 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1005 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + shared-cb = <4>; + }; + }; + + clk_virt: interconnect@0 { + compatible = "qcom,ravelin-clk_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,ravelin-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + reg = <0x16E0000 0x13080>; + compatible = "qcom,ravelin-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_SDCC2_AHB_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + reg = <0x1700000 0x1B080>; + compatible = "qcom,ravelin-aggre2_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + }; + + cnoc2: interconnect@1500000 { + reg = <0x1500000 0x6200>; + compatible = "qcom,ravelin-cnoc2"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cnoc3: interconnect@1510000 { + reg = <0x01510000 0xF200>; + compatible = "qcom,ravelin-cnoc3"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@19100000 { + reg = <0x19100000 0xBC080>; + compatible = "qcom,ravelin-gem_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + lpass_ag_noc: interconnect@3C40000 { + reg = <0x3C40000 0x17200>; + compatible = "qcom,ravelin-lpass_ag_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0x1740000 0x19080>; + compatible = "qcom,ravelin-mmss_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp"; + qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; + }; + + pcie_anoc: interconnect@16C0000 { + reg = <0x16C0000 0x7080>; + compatible = "qcom,ravelin-pcie_anoc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + }; + + system_noc: interconnect@1680000 { + reg = <0x1680000 0x19080>; + compatible = "qcom,ravelin-system_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + video_aggre_noc: interconnect@1760000 { + reg = <0x1760000 0x1100>; + compatible = "qcom,ravelin-video_aggre_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + qfprom: qfprom@221c8000 { + compatible = "qcom,ravelin-qfprom", "qcom,qfprom"; + reg = <0x221c8000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + feat_conf12: feat_conf12@0130 { + reg = <0x0130 0x4>; + }; + + feat_conf13: feat_conf13@0134 { + reg = <0x0134 0x4>; + }; + + boot_config: boot_config@600 { + reg = <0x600 0x1>; + }; + + gpu_speed_bin: gpu_speed_bin@119 { + reg = <0x119 0x2>; + bits = <5 8>; + }; + }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + nvmem-cells = <&feat_conf12>, + <&feat_conf13>, + <&boot_config>, + <&gpu_speed_bin>; + nvmem-cell-names = "feat_conf12", + "feat_conf13", + "boot_config", + "gpu_speed_bin"; + }; + + adsp_pas: remoteproc-adsp@03000000 { + compatible = "qcom,ravelin-adsp-pas"; + reg = <0x03000000 0x10000>; + status = "ok"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_LPI_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_LPI_MX_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "crypto_ddr"; + + qcom,qmp = <&aoss_qmp>; + memory-region = <&adsp_mem>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink_edge: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + + qcom,no-wake-svc = <0x190>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; + + }; + + modem_pas: remoteproc-mss@04080000 { + compatible = "qcom,ravelin-modem-pas"; + reg = <0x4080000 0x10000>; + status = "ok"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MODEM_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr","crypto_ddr"; + + qcom,qmp = <&aoss_qmp>; + memory-region = <&mpss_mem &system_cma>; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + }; + }; + + wpss_pas: remoteproc-wpss@8a00000 { + compatible = "qcom,ravelin-wpss-pas"; + reg = <0x08a00000 0x10000>; + status = "ok"; + + memory-region = <&wpss_moselle_mem>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MX_LEVEL>; + mx-uV-uA = ; + reg-names = "cx","mx"; + + qcom,qmp = <&aoss_qmp>; + + /* Inputs from wpss */ + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 0 0>, + <&wpss_smp2p_in 2 0>, + <&wpss_smp2p_in 1 0>, + <&wpss_smp2p_in 3 0>, + <&wpss_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to wpss */ + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <13>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "wpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "wpss"; + qcom,glink-label = "wpss"; + + qcom,wpss_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + }; + }; + + spmi_bus: spmi0_bus: qcom,spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc42d000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4c0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <0>; + }; + + spmi0_debug_bus: qcom,spmi-debug@10b14000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x10b14000 0x60>, <0x221c8784 0x4>; + reg-names = "core", "fuse"; + clocks = <&aoss_qmp>; + clock-names = "core_clk"; + qcom,fuse-enable-bit = <18>; + #address-cells = <2>; + #size-cells = <0>; + depends-on-supply = <&spmi0_bus>; + + qcom,pmk8350-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm6450-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8010-debug@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmg1110-debug@6 { + compatible = "qcom,spmi-pmic"; + reg = <6 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + + qcom,pmic_glink { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; + qcom,subsys-name = "lpass"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; + depends-on-supply = <&ipcc_mproc>; + status = "disabled"; + + battery_charger: qcom,battery_charger { + compatible = "qcom,battery-charger"; + status = "disabled"; + }; + + ucsi: qcom,ucsi { + compatible = "qcom,ucsi-glink"; + status = "disabled"; + connector { + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; + }; + }; + + altmode: qcom,altmode { + compatible = "qcom,altmode-glink"; + #altmode-cells = <1>; + status = "disabled"; + }; + }; + + thermal_zones: thermal-zones { + }; + + eud: qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupt-parent = <&pdc>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x088e0000 0x2000>, + <0x088e2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + clocks = <&gcc GCC_EUSB3_0_CLKREF_EN>; + clock-names = "eud_clkref_clk"; + qcom,secure-eud-en; + status = "ok"; + }; + + qrtr-gunyah { + compatible = "qcom,qrtr-gunyah"; + qcom,master; + gunyah-label = <3>; + peer-name = <2>; + shared-buffer = <&trust_ui_vm_qrtr>; + }; + + trust_ui_vm: qcom,trust_ui_vm@e55fc000 { + reg = <0xe55fc000 0x104000>; + vm_name = "trustedvm"; + shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_swiotlb>; + }; + + qcom,virtio_backend@0 { + compatible = "qcom,virtio_backend"; + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x11>; + }; + + vendor_hooks: qcom,cpu-vendor-hooks { + compatible = "qcom,cpu-vendor-hooks"; + }; + +}; + +#include "ravelin-pinctrl.dtsi" +#include "diwali-gdsc.dtsi" +#include "ipcc-test-ravelin.dtsi" +#include "ravelin-qupv3.dtsi" +#include "ravelin-regulators.dtsi" +#include "ravelin-pcie.dtsi" +#include "ravelin-wcn6750.dtsi" + +&qupv3_se7_2uart { + status = "ok"; +}; + +&qupv3_se2_4uart { + status = "ok"; +}; + +&gcc_pcie_0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_vcodec0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_venus_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&cam_cc_camss_top_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&disp_cc_mdss_core_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_cc_cx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_cc_gx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + sw-reset = <&gpu_cc_gx_sw_reset>; + status = "ok"; +}; + +&qupv3_se8_i2c { + status = "ok"; + fsa4480: fsa4480@42 { + reg = <0x42>; + }; +}; + +#include "ravelin-thermal.dtsi" +#include "ravelin-msm-rdbg.dtsi" diff --git a/qcom/ravelinp-4gb.dts b/qcom/ravelinp-4gb.dts new file mode 100644 index 00000000..892d1dfa --- /dev/null +++ b/qcom/ravelinp-4gb.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP 4Gb SoC"; + compatible = "qcom,ravelinp"; + qcom,board-id = <0 0x600>; +}; diff --git a/qcom/ravelinp-4gb.dtsi b/qcom/ravelinp-4gb.dtsi new file mode 100644 index 00000000..55da1771 --- /dev/null +++ b/qcom/ravelinp-4gb.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelinp.dtsi" +#include "ravelin-low-memory.dtsi" +/ { +}; + +&soc { +}; diff --git a/qcom/ravelinp-atp.dts b/qcom/ravelinp-atp.dts new file mode 100644 index 00000000..13710535 --- /dev/null +++ b/qcom/ravelinp-atp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp.dtsi" +#include "ravelinp-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP ATP"; + compatible = "qcom,ravelinp-atp", "qcom,ravelinp", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/ravelinp-atp.dtsi b/qcom/ravelinp-atp.dtsi new file mode 100644 index 00000000..1a4b89e5 --- /dev/null +++ b/qcom/ravelinp-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-atp.dtsi" diff --git a/qcom/ravelinp-idp-wcn3950-amoled-rcm.dts b/qcom/ravelinp-idp-wcn3950-amoled-rcm.dts new file mode 100644 index 00000000..8e9e430e --- /dev/null +++ b/qcom/ravelinp-idp-wcn3950-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp.dtsi" +#include "ravelinp-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP WCN3950 IDP + AMOLED + RCM"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi new file mode 100644 index 00000000..47d70c57 --- /dev/null +++ b/qcom/ravelinp-idp-wcn3950-amoled-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp-wcn3950-amoled-rcm.dtsi" diff --git a/qcom/ravelinp-idp-wcn3988-4gb.dts b/qcom/ravelinp-idp-wcn3988-4gb.dts new file mode 100644 index 00000000..b3a2acf8 --- /dev/null +++ b/qcom/ravelinp-idp-wcn3988-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-4gb.dtsi" +#include "ravelinp-idp-wcn3988-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP IDP 4GB DDR + WCN3988"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 0x601>; +}; diff --git a/qcom/ravelinp-idp-wcn3988-4gb.dtsi b/qcom/ravelinp-idp-wcn3988-4gb.dtsi new file mode 100644 index 00000000..228c590a --- /dev/null +++ b/qcom/ravelinp-idp-wcn3988-4gb.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp-wcn3988-4gb.dtsi" + diff --git a/qcom/ravelinp-idp.dts b/qcom/ravelinp-idp.dts new file mode 100644 index 00000000..b93d89fe --- /dev/null +++ b/qcom/ravelinp-idp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp.dtsi" +#include "ravelinp-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP IDP"; + compatible = "qcom,ravelinp-idp", "qcom,ravelinp", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/ravelinp-idp.dtsi b/qcom/ravelinp-idp.dtsi new file mode 100644 index 00000000..122b06c7 --- /dev/null +++ b/qcom/ravelinp-idp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-idp.dtsi" diff --git a/qcom/ravelinp-qrd-4gb.dts b/qcom/ravelinp-qrd-4gb.dts new file mode 100644 index 00000000..9b1d66c8 --- /dev/null +++ b/qcom/ravelinp-qrd-4gb.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp-4gb.dtsi" +#include "ravelinp-qrd-4gb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP QRD 4GB DDR"; + compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd"; + qcom,board-id = <0x1000B 0x600>; +}; diff --git a/qcom/ravelinp-qrd-4gb.dtsi b/qcom/ravelinp-qrd-4gb.dtsi new file mode 100644 index 00000000..c0e0c1bc --- /dev/null +++ b/qcom/ravelinp-qrd-4gb.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-qrd.dtsi" diff --git a/qcom/ravelinp-qrd.dts b/qcom/ravelinp-qrd.dts new file mode 100644 index 00000000..ecfcb70e --- /dev/null +++ b/qcom/ravelinp-qrd.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp.dtsi" +#include "ravelinp-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP QRD"; + compatible = "qcom,ravelinp-qrd", "qcom,ravelinp", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; + diff --git a/qcom/ravelinp-qrd.dtsi b/qcom/ravelinp-qrd.dtsi new file mode 100644 index 00000000..c0e0c1bc --- /dev/null +++ b/qcom/ravelinp-qrd.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-qrd.dtsi" diff --git a/qcom/ravelinp.dts b/qcom/ravelinp.dts new file mode 100644 index 00000000..184fdca6 --- /dev/null +++ b/qcom/ravelinp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelinp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. RavelinP SoC"; + compatible = "qcom,ravelinp"; + qcom,board-id = <0 0>; +}; + diff --git a/qcom/ravelinp.dtsi b/qcom/ravelinp.dtsi new file mode 100644 index 00000000..a3bc1041 --- /dev/null +++ b/qcom/ravelinp.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin.dtsi" +/ { + model = "Qualcomm Technologies, Inc. RavelinP"; + compatible = "qcom,ravelinp"; + qcom,msm-id = <602 0x10000>; +}; From af104388b56015c01ead589be10a565ec169dc3d Mon Sep 17 00:00:00 2001 From: kamasali Satyanarayan Date: Tue, 7 May 2024 17:07:05 +0530 Subject: [PATCH 58/59] ARM: dts: msm: Fix for EMMC & SD card enumeration for Parrot Parrot target doesn't support IO coherency. So, remove the coherent property from storage nodes. Change-Id: I061c1fc21b08769e5cf345be8d60ac2b092444ec Signed-off-by: kamasali Satyanarayan --- qcom/parrot.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 59743695..8b707a25 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -1463,7 +1463,6 @@ reset-names = "core_reset"; iommus = <&apps_smmu 0x60 0x0>; - dma-coherent; qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; @@ -1526,7 +1525,6 @@ 0x2C010800 0x80040868>; iommus = <&apps_smmu 0x540 0x0>; - dma-coherent; qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; From 840ca8a6723cc9a4c090395d54a2097433ec2774 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Wed, 12 Jun 2024 17:11:19 -0700 Subject: [PATCH 59/59] ARM: dts: msm: Add qcom,msgq-names property on pineapple Probe of mem-buf device fails unless this property is present. Fixes: c811ad67a603 ("ARM: dts: msm: Add support for mem-buf-msgq between oemvm and pvm") Change-Id: I8ec7302fb79f554edf20e55b2d15ae61486f6d0c Signed-off-by: Patrick Daly --- qcom/pineapple-vm.dtsi | 3 ++- qcom/pineapple.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/pineapple-vm.dtsi b/qcom/pineapple-vm.dtsi index ed4ab46b..c6a5b3c1 100644 --- a/qcom/pineapple-vm.dtsi +++ b/qcom/pineapple-vm.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -318,6 +318,7 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; }; virtio_mem_device { diff --git a/qcom/pineapple.dtsi b/qcom/pineapple.dtsi index 5b41ab58..ef9c9d1a 100644 --- a/qcom/pineapple.dtsi +++ b/qcom/pineapple.dtsi @@ -2406,7 +2406,8 @@ }; qcom,mem-buf-msgq { - compatible = "qcom,mem-buf-msgq"; + compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; }; qti,smmu-proxy {