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Merge "ARM: dts: qcom: add PMIC devices for Sun"

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This commit is contained in:
qctecmdr
2023-10-11 09:33:38 -07:00
committed by Gerrit - the friendly Code Review server
parent 1523c85584 0720a9afe6
commit 6136a71333
13 changed files with 318 additions and 83 deletions
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20
bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@@ -53,9 +53,11 @@ properties:
- qcom,pm8994-gpio
- qcom,pm8998-gpio
- qcom,pma8084-gpio
- qcom,pmd802x-gpio
- qcom,pmi8950-gpio
- qcom,pmi8994-gpio
- qcom,pmi8998-gpio
- qcom,pmih010x-gpio
- qcom,pmk8350-gpio
- qcom,pmk8550-gpio
- qcom,pmm8155au-gpio
@@ -136,6 +138,7 @@ allOf:
- qcom,pm8005-gpio
- qcom,pm8450-gpio
- qcom,pm8916-gpio
- qcom,pmd802x-gpio
- qcom,pmk8350-gpio
- qcom,pmr735a-gpio
- qcom,pmr735b-gpio
@@ -309,6 +312,21 @@ allOf:
minItems: 1
maxItems: 8
- if:
properties:
comptaible:
contains:
enum:
- qcom,pmih010x-gpio
then:
properties:
gpio-line-names:
minItems: 18
maxItems: 18
gpio-reserved-ranges:
minItems: 1
maxItems: 9
- if:
properties:
compatible:
@@ -439,8 +457,10 @@ $defs:
- gpio1-gpio22 for pm8994
- gpio1-gpio26 for pm8998
- gpio1-gpio22 for pma8084
- gpio1-gpio4 for pmd802x
- gpio1-gpio2 for pmi8950
- gpio1-gpio10 for pmi8994
- gpio1-gpio18 for pmih010x
- gpio1-gpio4 for pmk8350
- gpio1-gpio6 for pmk8550
- gpio1-gpio10 for pmm8155au

108
qcom/pineapple-pmic-overlay.dtsi
View File

@@ -13,6 +13,46 @@
#include "pmk8550.dtsi"
#include "pmr735d.dtsi"
&pm8550vs_c {
status = "ok";
};
&pm8550vs_d {
status = "ok";
};
&pm8550vs_e {
status = "ok";
};
&pm8550vs_g {
status = "ok";
};
&pm8550ve_i {
status = "ok";
};
&pm8550vs_c_temp_alarm {
status = "ok";
};
&pm8550vs_d_temp_alarm {
status = "ok";
};
&pm8550vs_e_temp_alarm {
status = "ok";
};
&pm8550vs_g_temp_alarm {
status = "ok";
};
&pm8550ve_i_temp_alarm {
status = "ok";
};
&pm8550_gpios {
key_vol_up {
key_vol_up_default: key_vol_up_default {
@@ -71,7 +111,7 @@
io-channel-names = "thermal";
};
&pm8550ve_tz {
&pm8550ve_i_tz {
io-channels = <&pmk8550_vadc PM8550VE_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
@@ -162,6 +202,72 @@
reg = <PM8550B_ADC5_GEN3_ICHG_FB>;
label = "pm8550b_ichg_fb";
};
pm8550b_offset_ref {
reg = <PM8550B_ADC5_GEN3_OFFSET_REF>;
label = "pm8550b_offset_ref";
qcom,pre-scaling = <1 1>;
};
pm8550b_vref_1p25 {
reg = <PM8550B_ADC5_GEN3_1P25VREF>;
label = "pm8550b_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pm8550b_die_temp {
reg = <PM8550B_ADC5_GEN3_DIE_TEMP>;
label = "pm8550b_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550b_lite_die_temp {
reg = <PM8550B_ADC5_GEN3_TEMP_ALARM_LITE>;
label = "pm8550b_lite_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550b_vph_pwr {
reg = <PM8550B_ADC5_GEN3_VPH_PWR>;
label = "pm8550b_vph_pwr";
qcom,pre-scaling = <1 3>;
};
pm8550b_vbat_sns_qbg {
reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>;
label = "pm8550b_vbat_sns_qbg";
qcom,pre-scaling = <1 3>;
};
pm8550vs_c_die_temp {
reg = <PM8550VS_C_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_c_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550vs_d_die_temp {
reg = <PM8550VS_D_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_d_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550vs_e_die_temp {
reg = <PM8550VS_E_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_e_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550vs_g_die_temp {
reg = <PM8550VS_G_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_g_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550ve_die_temp {
reg = <PM8550VE_ADC5_GEN3_DIE_TEMP>;
label = "pm8550ve_die_temp";
qcom,pre-scaling = <1 1>;
};
};
&pmk8550_gpios {

6
qcom/pineapple-thermal-overlay.dtsi
View File

@@ -226,10 +226,10 @@
};
};
pm8550ve_tz {
pm8550ve_i_tz {
cooling-maps {
pm8550ve_nsp {
trip = <&pm8550ve_trip0>;
pm8550ve_i_nsp {
trip = <&pm8550ve_i_trip0>;
cooling-device = <&cdsp_sw_hvx 5 THERMAL_NO_LIMIT>;
};
};

52
qcom/pm8550ve.dtsi
View File

@@ -12,20 +12,55 @@
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm8550ve@8 {
pm8550ve_d: qcom,pm8550ve@3 {
compatible = "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pm8550ve_d_gpios: pinctrl@8800 {
compatible = "qcom,pm8550ve-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8550ve_g: qcom,pm8550ve@6 {
compatible = "qcom,spmi-pmic";
reg = <0x6 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pm8550ve_g_gpios: pinctrl@8800 {
compatible = "qcom,pm8550ve-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8550ve_i: qcom,pm8550ve@8 {
compatible = "qcom,spmi-pmic";
reg = <0x8 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pm8550ve_tz: pm8550ve-temp-alarm@a00 {
pm8550ve_i_tz: pm8550ve-i-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8550ve_gpios: pinctrl@8800 {
pm8550ve_i_gpios: pinctrl@8800 {
compatible = "qcom,pm8550ve-gpio";
reg = <0x8800>;
gpio-controller;
@@ -37,26 +72,27 @@
};
&thermal_zones {
pm8550ve_temp_alarm: pm8550ve_tz {
pm8550ve_i_temp_alarm: pm8550ve_i_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550ve_tz>;
thermal-sensors = <&pm8550ve_i_tz>;
status = "disabled";
trips {
pm8550ve_trip0: trip0 {
pm8550ve_i_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8550ve_trip1: trip1 {
pm8550ve_i_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
pm8550ve_trip2: trip2 {
pm8550ve_i_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";

42
qcom/pm8550vs.dtsi
View File

@@ -17,6 +17,7 @@
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pm8550vs_c_tz: pm8550vs-c-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
@@ -40,6 +41,7 @@
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pm8550vs_d_tz: pm8550vs-d-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
@@ -63,6 +65,7 @@
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pm8550vs_e_tz: pm8550vs-e-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
@@ -81,11 +84,29 @@
};
};
pm8550vs_f: qcom,pm8550vs@5 {
compatible = "qcom,spmi-pmic";
reg = <0x5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pm8550vs_f_gpios: pinctrl@8800 {
compatible = "qcom,pm8550vs-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm8550vs_g: qcom,pm8550vs@6 {
compatible = "qcom,spmi-pmic";
reg = <0x6 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pm8550vs_g_tz: pm8550vs-g-temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
@@ -103,6 +124,23 @@
#interrupt-cells = <2>;
};
};
pm8550vs_j: qcom,pm8550vs@9 {
compatible = "qcom,spmi-pmic";
reg = <0x9 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pm8550vs_j_gpios: pinctrl@8800 {
compatible = "qcom,pm8550vs-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&thermal_zones {
@@ -111,6 +149,7 @@
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550vs_c_tz>;
status = "disabled";
trips {
pm8550vs_c_trip0: trip0 {
@@ -138,6 +177,7 @@
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550vs_d_tz>;
status = "disabled";
trips {
pm8550vs_d_trip0: trip0 {
@@ -165,6 +205,7 @@
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550vs_e_tz>;
status = "disabled";
trips {
pm8550vs_e_trip0: trip0 {
@@ -192,6 +233,7 @@
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8550vs_g_tz>;
status = "disabled";
trips {
pm8550vs_g_trip0: trip0 {

29
qcom/pmd802x.dtsi Normal file
View File

@@ -0,0 +1,29 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pmd802x@4 {
compatible = "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmd802x_gpios: pinctrl@8800 {
compatible = "qcom,pmd802x-gpio";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

29
qcom/pmih010x.dtsi Normal file
View File

@@ -0,0 +1,29 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pmih010x@7 {
compatible = "qcom,spmi-pmic";
reg = <0x7 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmih010x_gpios: pinctrl@8800 {
compatible = "qcom,pmih010x-gpio";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

71
qcom/pmk8550.dtsi
View File

@@ -161,77 +161,6 @@
qcom,pre-scaling = <1 3>;
};
/* PM8550B Channel nodes */
pm8550b_offset_ref {
reg = <PM8550B_ADC5_GEN3_OFFSET_REF>;
label = "pm8550b_offset_ref";
qcom,pre-scaling = <1 1>;
};
pm8550b_vref_1p25 {
reg = <PM8550B_ADC5_GEN3_1P25VREF>;
label = "pm8550b_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pm8550b_die_temp {
reg = <PM8550B_ADC5_GEN3_DIE_TEMP>;
label = "pm8550b_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550b_lite_die_temp {
reg = <PM8550B_ADC5_GEN3_TEMP_ALARM_LITE>;
label = "pm8550b_lite_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8550b_vph_pwr {
reg = <PM8550B_ADC5_GEN3_VPH_PWR>;
label = "pm8550b_vph_pwr";
qcom,pre-scaling = <1 3>;
};
pm8550b_vbat_sns_qbg {
reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG>;
label = "pm8550b_vbat_sns_qbg";
qcom,pre-scaling = <1 3>;
};
/* PM8550VS_C Channel nodes */
pm8550vs_c_die_temp {
reg = <PM8550VS_C_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_c_die_temp";
qcom,pre-scaling = <1 1>;
};
/* PM8550VS_D Channel nodes */
pm8550vs_d_die_temp {
reg = <PM8550VS_D_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_d_die_temp";
qcom,pre-scaling = <1 1>;
};
/* PM8550VS_E Channel nodes */
pm8550vs_e_die_temp {
reg = <PM8550VS_E_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_e_die_temp";
qcom,pre-scaling = <1 1>;
};
/* PM8550VS_G Channel nodes */
pm8550vs_g_die_temp {
reg = <PM8550VS_G_ADC5_GEN3_DIE_TEMP>;
label = "pm8550vs_g_die_temp";
qcom,pre-scaling = <1 1>;
};
/* PM8550VE Channel nodes */
pm8550ve_die_temp {
reg = <PM8550VE_ADC5_GEN3_DIE_TEMP>;
label = "pm8550ve_die_temp";
qcom,pre-scaling = <1 1>;
};
};
};
};

1
qcom/sun-cdp.dtsi
View File

@@ -3,3 +3,4 @@
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-pmic-overlay.dtsi"

1
qcom/sun-mtp.dtsi
View File

@@ -3,3 +3,4 @@
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-pmic-overlay.dtsi"

39
qcom/sun-pmic-overlay.dtsi Normal file
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@@ -0,0 +1,39 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include "pm8010.dtsi"
#include "pm8550.dtsi"
#include "pm8550ve.dtsi"
#include "pm8550vs.dtsi"
#include "pmd802x.dtsi"
#include "pmih010x.dtsi"
#include "pmk8550.dtsi"
#include "pmr735d.dtsi"
&pm8550vs_f {
status = "ok";
};
&pm8550vs_j {
status = "ok";
};
&pm8550ve_d {
status = "ok";
};
&pm8550ve_g {
status = "ok";
};
&pm8550ve_i {
status = "ok";
};
&pm8550ve_i_temp_alarm {
status = "ok";
};

1
qcom/sun-qrd.dtsi
View File

@@ -3,3 +3,4 @@
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-pmic-overlay.dtsi"

2
qcom/sun-rumi.dtsi
View File

@@ -7,6 +7,8 @@
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include "sun-pmic-overlay.dtsi"
&reserved_memory {
spintable: spintable_region@90000000 {
no-map;