samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge "ARM: dts: msm: tuna: Add capacity and DPC properties"

Browse Source
This commit is contained in:
QCTECMDR Service
2024-09-23 06:58:49 -07:00
committed by Gerrit - the friendly Code Review server
parent 325199722a 9ada1c9254
commit 5f1c2327be
1 changed files with 16 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
qcom/tuna.dtsi
View File

@@ -93,6 +93,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -115,6 +117,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_1>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -133,6 +137,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_2>;
capacity-dmips-mhz = <1321>;
dynamic-power-coefficient = <121>;
L2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -150,6 +156,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_3>;
capacity-dmips-mhz = <1321>;
dynamic-power-coefficient = <121>;
L2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -167,6 +175,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_4>;
capacity-dmips-mhz = <1321>;
dynamic-power-coefficient = <121>;
L2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -184,6 +194,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_5>;
capacity-dmips-mhz = <1321>;
dynamic-power-coefficient = <121>;
L2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -201,6 +213,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_6>;
capacity-dmips-mhz = <1321>;
dynamic-power-coefficient = <121>;
L2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -218,6 +232,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_7>;
capacity-dmips-mhz = <1935>;
dynamic-power-coefficient = <295>;
L2_7: l2-cache {
compatible = "cache";
cache-level = <2>;