From 9ada1c9254d82af6bb9493a9977e29936569d152 Mon Sep 17 00:00:00 2001 From: Ankit Sharma Date: Fri, 20 Sep 2024 15:34:31 +0530 Subject: [PATCH] ARM: dts: msm: tuna: Add capacity and DPC properties The "capacity-dmips-mhz" and "dynamic-power-coefficient" are used to build Energy Model which in turn is used by EAS to take placement decisions. Change-Id: Iac04bf0b435d6741fd6b5ae10c4cc38675ac5170 Signed-off-by: Ankit Sharma --- qcom/tuna.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 07467382..0adf9746 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -93,6 +93,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -115,6 +117,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -133,6 +137,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_2>; + capacity-dmips-mhz = <1321>; + dynamic-power-coefficient = <121>; L2_2: l2-cache { compatible = "cache"; cache-level = <2>; @@ -150,6 +156,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_3>; + capacity-dmips-mhz = <1321>; + dynamic-power-coefficient = <121>; L2_3: l2-cache { compatible = "cache"; cache-level = <2>; @@ -167,6 +175,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_4>; + capacity-dmips-mhz = <1321>; + dynamic-power-coefficient = <121>; L2_4: l2-cache { compatible = "cache"; cache-level = <2>; @@ -184,6 +194,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_5>; + capacity-dmips-mhz = <1321>; + dynamic-power-coefficient = <121>; L2_5: l2-cache { compatible = "cache"; cache-level = <2>; @@ -201,6 +213,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_6>; + capacity-dmips-mhz = <1321>; + dynamic-power-coefficient = <121>; L2_6: l2-cache { compatible = "cache"; cache-level = <2>; @@ -218,6 +232,8 @@ power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_7>; + capacity-dmips-mhz = <1935>; + dynamic-power-coefficient = <295>; L2_7: l2-cache { compatible = "cache"; cache-level = <2>;