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ARM: dts: msm: tuna: Add capacity and DPC properties

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The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn is used by EAS to take
placement decisions.

Change-Id: Iac04bf0b435d6741fd6b5ae10c4cc38675ac5170
Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
This commit is contained in:
Ankit Sharma
2024-09-20 15:34:31 +05:30
parent c4b678839d
commit 9ada1c9254
1 changed files with 16 additions and 0 deletions
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16
qcom/tuna.dtsi
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@@ -93,6 +93,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -115,6 +117,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_1>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -133,6 +137,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_2>;
capacity-dmips-mhz = <1321>;
dynamic-power-coefficient = <121>;
L2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -150,6 +156,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_3>;
capacity-dmips-mhz = <1321>;
dynamic-power-coefficient = <121>;
L2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -167,6 +175,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_4>;
capacity-dmips-mhz = <1321>;
dynamic-power-coefficient = <121>;
L2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -184,6 +194,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_5>;
capacity-dmips-mhz = <1321>;
dynamic-power-coefficient = <121>;
L2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -201,6 +213,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_6>;
capacity-dmips-mhz = <1321>;
dynamic-power-coefficient = <121>;
L2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -218,6 +232,8 @@
power-domain-names = "psci";
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_7>;
capacity-dmips-mhz = <1935>;
dynamic-power-coefficient = <295>;
L2_7: l2-cache {
compatible = "cache";
cache-level = <2>;