samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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ARM: dts: msm: dt snabpshot for Monaco SoC

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Add dt snapshot of cpu level cache from branch msm-5.15.c2
commit 8ae5ffe89e0f ("ARM: dts: msm: Add mdsp heap for mDSP compute").

Change-Id: Id833a1f0894f29753c0ce08839bf3111b8d57a61
Signed-off-by: Pradnya Dahiwale <quic_pdahiwal@quicinc.com>
This commit is contained in:
Pradnya Dahiwale
2024-06-05 14:47:10 +05:30
parent 1a1d6a94be
commit 58daad1f6c
1 changed files with 11 additions and 11 deletions
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22
qcom/monaco.dtsi
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@@ -54,17 +54,17 @@
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_0: l2-cache {
/* compatible = "arm,arch-cache"; */
cache-size = <0x80000>;
cache-level = <2>;
compatible = "cache";
cache-size = <0x80000>;
cache-level = <2>;
};
L1_I_0: l1-icache {
/* compatible = "arm,arch-cache"; */
compatible = "cache";
};
L1_D_0: l1-dcache {
/* compatible = "arm,arch-cache"; */
compatible = "cache";
};
};
@@ -85,11 +85,11 @@
qcom,lmh-dcvs = <&lmh_dcvs0>;
L1_I_1: l1-icache {
/* compatible = "arm,arch-cache"; */
compatible = "cache";
};
L1_D_1: l1-dcache {
/* compatible = "arm,arch-cache"; */
compatible = "cache";
};
};
@@ -110,11 +110,11 @@
qcom,lmh-dcvs = <&lmh_dcvs0>;
L1_I_2: l1-icache {
/* compatible = "arm,arch-cache"; */
compatible = "cache";
};
L1_D_2: l1-dcache {
/* compatible = "arm,arch-cache"; */
compatible = "cache";
};
};
@@ -135,11 +135,11 @@
qcom,lmh-dcvs = <&lmh_dcvs0>;
L1_I_3: l1-icache {
/* compatible = "arm,arch-cache"; */
compatible = "cache";
};
L1_D_3: l1-dcache {
/* compatible = "arm,arch-cache"; */
compatible = "cache";
};
};