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Change-Id: Ia9ea91446fa043b36e432e74fe48863b00eac4cd
This commit is contained in:
Linux Build Service Account
2024-09-20 04:57:31 -07:00
parent 8682a98d54 a9ff298e9d
commit 4fdbd4a3cb
61 changed files with 4607 additions and 379 deletions
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25
bindings/arm/msm/msm.yaml
View File

@@ -122,10 +122,35 @@ properties:
- description: Qualcomm Technologies, Inc. TUNA
items:
- enum:
- qcom,tuna-atp
- qcom,atp
- qcom,tuna-cdp
- qcom,cdp
- qcom,tuna-mtp
- qcom,mtp
- qcom,tuna-qrd
- qcom,qrd
- qcom,tuna-rcm
- qcom,rcm
- qcom,tuna-rumi
- qcom,rumi
- const: qcom,tuna
- description: Qualcomm Technologies, Inc. TUNAP
items:
- enum:
- qcom,tunap-atp
- qcom,atp
- qcom,tunap-cdp
- qcom,cdp
- qcom,tunap-mtp
- qcom,mtp
- qcom,tunap-qrd
- qcom,qrd
- qcom,tunap-rcm
- qcom,rcm
- const: qcom,tunap
- description: Qualcomm Technologies, Inc. KERA
items:
- enum:

1
bindings/arm/msm/qcom,llcc.yaml
View File

@@ -36,6 +36,7 @@ properties:
- qcom,pineapple-llcc
- qcom,sun-llcc
- qcom,sdxpinn-llcc
- qcom,tuna-llcc
- qcom,kera-llcc
- qcom,x1e80100-llcc

1
bindings/clock/qcom,debugcc.yaml
View File

@@ -19,6 +19,7 @@ properties:
- qcom,pineapple-debugcc
- qcom,sun-debugcc
- qcom,parrot-debugcc
- qcom,sdx75-debugcc
- qcom,sm4450-debugcc
- qcom,monaco-debugcc

4
bindings/clock/qcom,dispcc-sm8x50.yaml
View File

@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding for SM8x50
title: Qualcomm Technologies, Inc. Display Clock & Reset Controller for SM8x50
maintainers:
- Jonathan Marek <jonathan@marek.ca>
@@ -19,6 +19,7 @@ description: |
dt-bindings/clock/qcom,dispcc-sm8350.h
dt-bindings/clock/qcom,dispcc-pineapple.h
dt-bindings/clock/qcom,dispcc-sun.h
dt-bindings/clock/qcom,dispcc-tuna.h
properties:
compatible:
@@ -29,6 +30,7 @@ properties:
- qcom,sm8350-dispcc
- qcom,pineapple-dispcc
- qcom,sun-dispcc
- qcom,tuna-dispcc
clocks:
items:

1
bindings/clock/qcom,evacc-sun.yaml
View File

@@ -21,6 +21,7 @@ properties:
enum:
- qcom,sun-evacc
- qcom,tuna-evacc
- qcom,sun-evacc-v2
clocks:
items:

5
bindings/i2c/qcom,i2c-msm-geni.yaml
View File

@@ -54,6 +54,11 @@ properties:
reg:
maxItems: 1
qcom,old-i2c-freq-cfg:
type: boolean
deprecated: true
description: Configure the I2C bus speed using the older counter settings
required:
- compatible
- reg

141
bindings/leds/leds-aw2016.yaml Normal file
View File

@@ -0,0 +1,141 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/leds-aw2016.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AWINIC AW2016 3-channel LED Driver
maintainers:
- Kamal Wadhwa <quic_kamalw@quicinc.com>
description: |
AW2016 LED device supports 3 LED channels and the driver
register each channel as a single LED class device and
exports interfaces to update brightness, set timer trigger
and enable HW based blink functionalities.
properties:
compatible:
const: awinic,aw2016_led
reg:
description: |
The 7-bit I2C address for AW2016 chip.
patternProperties:
"^awinic,[0-9a-z]+$":
type: object
$ref: common.yaml#
unevaluatedProperties: false
properties:
awinic,name:
description: |
Name of the LED which will be register as the LED class
device name.
$ref: /schemas/types.yaml#/definitions/string
awinic,id:
description: |
It represents the LED hardware channel index. The valid
values are 0, 1, 2.
$ref: /schemas/types.yaml#/definitions/uint32
awinic,imax:
description: |
The setting of the maximum current for the given LED channel,
the valid values are 0, 1, 2, 3, and the corresponding current
setting are 15mA, 30mA, 5mA, 10mA.
$ref: /schemas/types.yaml#/definitions/uint32
awinic,led-current:
description: |
The setting of the current when the LED channel is enabled.
$ref: /schemas/types.yaml#/definitions/uint32
awinic,max-brightness:
description: |
The maximum brightness value for the LED class device.
$ref: /schemas/types.yaml#/definitions/uint32
awinic,rise-time-ms:
description: |
The duration of the led ramping from 0 to maximum brightness
when breath function is enabled.
awinic,hold-time-ms:
description: |
The duration of the led staying at the maximum brightness
when breath function is enabled.
awinic,fall-time-ms:
description: |
The duration of the led ramping down from maximum brightness
to 0 when breath function is enabled.
awinic,off-time-ms:
description: |
The duration of the led staying at 0 brightness when breath
function is enabled.
required:
- awinic,name
- awinic,id
- awinic,imax
- awinic,led-current
- awinic,max-brightness
- awinic,rise-time-ms
- awinic,hold-time-ms
- awinic,fall-time-ms
- awinic,off-time-ms
required:
- compatible
- reg
additionalProperties: false
examples:
- |
awinic@64 {
compatible = "awinic,aw2016_led";
reg = <0x64>;
awinic,red {
awinic,name = "red";
awinic,id = <0>;
awinic,imax = <2>;
awinic,led-current = <3>;
awinic,max-brightness = <255>;
awinic,rise-time-ms = <6>;
awinic,hold-time-ms = <0>;
awinic,fall-time-ms = <6>;
awinic,off-time-ms = <4>;
};
awinic,green {
awinic,name = "green";
awinic,id = <1>;
awinic,imax = <2>;
awinic,led-current = <3>;
awinic,max-brightness = <255>;
awinic,rise-time-ms = <6>;
awinic,hold-time-ms = <0>;
awinic,fall-time-ms = <6>;
awinic,off-time-ms = <4>;
};
awinic,blue {
awinic,name = "blue";
awinic,id = <2>;
awinic,imax = <2>;
awinic,led-current = <3>;
awinic,max-brightness = <255>;
awinic,rise-time-ms = <6>;
awinic,hold-time-ms = <0>;
awinic,fall-time-ms = <6>;
awinic,off-time-ms = <4>;
};
};
...

6
bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@@ -56,6 +56,7 @@ properties:
- qcom,pm8998-gpio
- qcom,pma8084-gpio
- qcom,pmd802x-gpio
- qcom,pmi632-gpio
- qcom,pmi8950-gpio
- qcom,pmi8994-gpio
- qcom,pmi8998-gpio
@@ -71,6 +72,7 @@ properties:
- qcom,pms405-gpio
- qcom,pmx55-gpio
- qcom,pmx65-gpio
- qcom,pmx75-gpio
- qcom,pmxr2230-gpio
- enum:
@@ -182,6 +184,7 @@ allOf:
- qcom,pm8550ve-gpio
- qcom,pm8950-gpio
- qcom,pm7550ba-gpio
- qcom,pmi632-gpio
then:
properties:
gpio-line-names:
@@ -308,6 +311,7 @@ allOf:
contains:
enum:
- qcom,pmx65-gpio
- qcom,pmx75-gpio
- qcom,pm5100-gpio
then:
properties:
@@ -465,6 +469,7 @@ $defs:
- gpio1-gpio26 for pm8998
- gpio1-gpio22 for pma8084
- gpio1-gpio4 for pmd802x
- gpio1-gpio8 for pmi632
- gpio1-gpio2 for pmi8950
- gpio1-gpio10 for pmi8994
- gpio1-gpio18 for pmih010x
@@ -481,6 +486,7 @@ $defs:
- gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
and gpio11)
- gpio1-gpio16 for pmx65
- gpio1-gpio16 for pmx75
- gpio1-gpio12 for pmxr2230
- gpio1-gpio16 for pm5100

1
bindings/remoteproc/qcom,adsp.yaml
View File

@@ -37,6 +37,7 @@ properties:
- qcom,sdm845-adsp-pas
- qcom,sdm845-cdsp-pas
- qcom,sdx55-mpss-pas
- qcom,sdxpinn-modem-pas
- qcom,sm6350-adsp-pas
- qcom,sm6350-cdsp-pas
- qcom,sm6350-mpss-pas

32
bindings/soc/qcom/qcom,dynpf.yaml Normal file
View File

@@ -0,0 +1,32 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,dynpf.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) DYNPF Driver
maintainers:
- Amir Vajid <quic_avajid@quicinc.com>
- Shivnandan Kumar <quic_kshivnan@quicinc.com>
description: |
The Qualcomm Technologies, Inc. (QTI) DYNPF Driver provides a sysfs
interface to userspace to send parameters to CPUCP firmware over SCMI
in order to configure the DYNPF feature.
properties:
compatible:
const: qcom,dynpf
required:
- compatible
additionalProperties: false
examples:
- |
qcom_dynpf: qcom,dynpf {
compatible = "qcom,dynpf";
};

15
qcom/Makefile
View File

@@ -54,7 +54,15 @@ sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_B
TUNA_BASE_DTB += tuna.dtb
NOAPQ_TUNA_BOARDS += \
tuna-rumi-overlay.dtbo
tuna-atp-overlay.dtbo \
tuna-cdp-overlay.dtbo \
tuna-mtp-kiwi-overlay.dtbo \
tuna-mtp-overlay.dtbo \
tuna-mtp-qmp1000-overlay.dtbo \
tuna-qrd-overlay.dtbo \
tuna-rcm-kiwi-overlay.dtbo \
tuna-rcm-overlay.dtbo \
tuna-rumi-overlay.dtbo
sun-dtb-$(CONFIG_ARCH_TUNA) += \
$(call add-overlays, $(NOAPQ_TUNA_BOARDS),$(TUNA_BASE_DTB))
@@ -174,7 +182,10 @@ ifeq ($(CONFIG_ARCH_SDXKOVA), y)
sdxkova-dtb-$(CONFIG_ARCH_SDXKOVA) += sdxkova-idp-cpe.dtb \
sdxkova-idp-mbb.dtb \
sdxkova-idp-m2.dtb
dtb-y += $(sdxkova-dtb-y)
sdxkova-cpe-wkk-dtb-$(CONFIG_ARCH_SDXKOVA) += sdxkova-idp-cpe.dtb
dtb-y += $($(MSM_ARCH)-dtb-y)
endif

13
qcom/ipcc-test-sdxkova.dtsi Normal file
View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ipcc-test.dtsi"
&soc {
/delete-node/ ipcc-self-ping-adsp;
/delete-node/ ipcc-self-ping-cdsp;
/delete-node/ ipcc-self-ping-slpi;
};

5
qcom/kera-usb.dtsi
View File

@@ -36,6 +36,11 @@
compatible = "snps,dwc3";
reg = <0xa600000 0xd93c>;
iommus = <&apps_smmu 0x40 0x0>;
qcom,iommu-dma = "bypass";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
snps,disable-clk-gating;
snps,has-lpm-erratum;

154
qcom/kera.dtsi
View File

@@ -478,6 +478,160 @@
reg = <0x1fc0000 0x30000>;
};
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
sleepstate_smp2p_out: sleepstate-out {
qcom,entry-name = "sleepstate";
#qcom,smem-state-cells = <1>;
};
sleepstate_smp2p_in: qcom,sleepstate-in {
qcom,entry-name = "sleepstate_see";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
/* ipa - inbound entry from mss */
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_smem_mailbox_1_out: qcom,smp2p-smem-mailbox-1-out {
qcom,entry-name = "smem-mailbox";
#qcom,smem-state-cells = <1>;
};
smp2p_smem_mailbox_1_in: qcom,smp2p-smem-mailbox-1-in {
qcom,entry-name = "smem-mailbox";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-soccp {
compatible = "qcom,smp2p";
qcom,smem = <617>, <616>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <19>;
soccp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
soccp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p_sleepstate {
compatible = "qcom,smp2p-sleepstate";
qcom,smem-states = <&sleepstate_smp2p_out 0>;
interrupt-parent = <&sleepstate_smp2p_in>;
interrupts = <0 0>;
interrupt-names = "smp2p-sleepstate-in";
};
eud: qcom,msm-eud@88e0000 {
compatible = "qcom,msm-eud";
interrupt-names = "eud_irq";

8
qcom/monaco.dtsi
View File

@@ -190,7 +190,7 @@
soc: soc { };
chosen {
bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kpti=off kernel.panic_on_rcu_stall=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-3 ftrace_dump_on_oops fw_devlink.strict=1 printk.console_no_auto_verbose=1 irqaffinity=0-2 cpufreq.default_governor=performance slub_debug=- randomize_kstack_offset=on ";
bootargs = "loglevel=6 log_buf_len=256K kpti=off kernel.panic_on_rcu_stall=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-3 ftrace_dump_on_oops fw_devlink.strict=1 printk.console_no_auto_verbose=1 irqaffinity=0-2 cpufreq.default_governor=performance slub_debug=- randomize_kstack_offset=on ";
};
reserved_memory: reserved-memory {
@@ -1678,9 +1678,8 @@
sdhc_1: sdhci@4744000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>,
<0x04748000 0x8000>, <0x04750000 0x9000>;
reg-names = "hc", "cqhci", "cqhci_ice",
"cqhci_ice_hwkm";
<0x04748000 0x18000>;
reg-names = "hc", "cqhci", "ice";
iommus = <&apps_smmu 0xC0 0x0>;
qcom,iommu-dma = "bypass";
@@ -1689,6 +1688,7 @@
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,ice-use-hwkm;
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;

6
qcom/msm-arm-smmu-sun.dtsi
View File

@@ -281,7 +281,7 @@
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x7d3000 0x1000>;
qcom,stream-id-range = <0xc00 0x400>;
qcom,iova-width = <34>;
qcom,iova-width = <32>;
interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <2>;
};
@@ -299,7 +299,7 @@
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x16cd000 0x1000>;
qcom,stream-id-range = <0x1400 0x400>;
qcom,iova-width = <36>;
qcom,iova-width = <32>;
interconnects = <&pcie_noc MASTER_PCIE_3 &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <1>;
qcom,opt-out-tbu-halting;
@@ -309,7 +309,7 @@
compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
reg = <0x17d1000 0x1000>;
qcom,stream-id-range = <0x1800 0x400>;
qcom,iova-width = <36>;
qcom,iova-width = <32>;
interconnects = <&mmss_noc MASTER_VIDEO_EVA &mc_virt SLAVE_EBI1>;
qcom,num-qtb-ports = <2>;
};

24
qcom/msm-arm-smmu-tuna.dtsi
View File

@@ -200,18 +200,18 @@
<0x0801 0x0000 0x00000001>,
/* NSP:Compute */
<0x0c01 0x0040 0x00000303>,
<0x0c02 0x0020 0x00000303>,
<0x0c03 0x0040 0x00000303>,
<0x0c04 0x0040 0x00000303>,
<0x0c05 0x0040 0x00000303>,
<0x0c06 0x0020 0x00000303>,
<0x0c07 0x0040 0x00000303>,
<0x0c08 0x0020 0x00000303>,
<0x0c09 0x0040 0x00000303>,
<0x0c0c 0x0040 0x00000303>,
<0x0c0d 0x0020 0x00000303>,
<0x0c0e 0x0040 0x00000303>,
<0x0c01 0x0000 0x00000303>,
<0x0c02 0x0000 0x00000303>,
<0x0c03 0x0000 0x00000303>,
<0x0c04 0x0000 0x00000303>,
<0x0c05 0x0000 0x00000303>,
<0x0c06 0x0000 0x00000303>,
<0x0c07 0x0000 0x00000303>,
<0x0c08 0x0000 0x00000303>,
<0x0c09 0x0000 0x00000303>,
<0x0c0c 0x0000 0x00000303>,
<0x0c0d 0x0000 0x00000303>,
<0x0c0e 0x0000 0x00000303>,
/* SF:Camera */
<0x1800 0x00c0 0x00000001>,

2
qcom/parrot-coresight.dtsi
View File

@@ -570,7 +570,7 @@
coresight-name = "coresight-snoc";
qcom,dummy-source;
atid = <125>;
atid = <108>;
out-ports {
port {
snoc_out_funnel_in0: endpoint {

524
qcom/parrot-debug.dtsi
View File

@@ -11,9 +11,7 @@
ranges;
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xc00000>;
};
@@ -1447,299 +1445,313 @@
compatible = "qcom,mem-dump";
memory-region = <&dump_mem>;
c0_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x0>;
static_mem_dump {
qcom,static-mem-dump;
c0_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x0>;
};
c100_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x1>;
};
c200_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x2>;
};
c300_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x3>;
};
c400_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x4>;
};
c500_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x5>;
};
c600_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x6>;
};
c700_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x7>;
};
rpmh {
qcom,dump-size = <0x400000>;
qcom,dump-id = <0xec>;
};
rpm_sw {
qcom,dump-size = <0x28000>;
qcom,dump-id = <0xea>;
};
pmic {
qcom,dump-size = <0x200000>;
qcom,dump-id = <0xe4>;
};
fcm {
qcom,dump-size = <0x8400>;
qcom,dump-id = <0xee>;
};
etf_swao {
qcom,dump-size = <0x10000>;
qcom,dump-id = <0xf1>;
};
etr_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x100>;
};
etr1_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x105>;
};
etfswao_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x102>;
};
misc_data {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0xe8>;
};
etf_lpass {
qcom,dump-size = <0x4000>;
qcom,dump-id = <0xf4>;
};
etflpass_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x104>;
};
osm_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x163>;
};
pcu_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x164>;
};
fsm_data {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x165>;
};
};
c100_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x1>;
};
dynamic_mem_dump {
qcom,dynamic-mem-dump;
c200_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x2>;
};
cpuss_reg {
cpuss_reg {
qcom,dump-size = <0x30000>;
qcom,dump-id = <0xef>;
};
};
c300_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x3>;
};
l1 {
l1_icache0 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x60>;
};
c400_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x4>;
};
l1_icache100 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x61>;
};
c500_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x5>;
};
l1_icache200 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x62>;
};
c600_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x6>;
};
l1_icache300 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x63>;
};
c700_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x7>;
};
l1_icache400 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x64>;
};
cpuss_reg {
qcom,dump-size = <0x30000>;
qcom,dump-id = <0xef>;
};
l1_icache500 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x65>;
};
l1_icache0 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x60>;
};
l1_icache600 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x66>;
};
l1_icache100 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x61>;
};
l1_icache700 {
qcom,dump-size = <0x32100>;
qcom,dump-id = <0x67>;
};
l1_icache200 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x62>;
};
l1_dcache0 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x80>;
};
l1_icache300 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x63>;
};
l1_dcache100 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x81>;
};
l1_icache400 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x64>;
};
l1_dcache200 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x82>;
};
l1_icache500 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x65>;
};
l1_dcache300 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x83>;
};
l1_icache600 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x66>;
};
l1_dcache400 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x84>;
};
l1_icache700 {
qcom,dump-size = <0x32100>;
qcom,dump-id = <0x67>;
};
l1_dcache500 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x85>;
};
l1_dcache0 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x80>;
};
l1_dcache600 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x86>;
};
l1_dcache100 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x81>;
};
l1_dcache700 {
qcom,dump-size = <0x12100>;
qcom,dump-id = <0x87>;
};
l1_dcache200 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x82>;
};
l1_itlb400 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x24>;
};
l1_dcache300 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x83>;
};
l1_itlb500 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x25>;
};
l1_dcache400 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x84>;
};
l1_itlb600 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x26>;
};
l1_dcache500 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x85>;
};
l1_itlb700 {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x27>;
};
l1_dcache600 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x86>;
};
l1_dtlb400 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x44>;
};
l1_dcache700 {
qcom,dump-size = <0x12100>;
qcom,dump-id = <0x87>;
};
l1_dtlb500 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x45>;
};
l1_itlb400 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x24>;
};
l1_dtlb600 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x46>;
};
l1_itlb500 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x25>;
};
l1_dtlb700 {
qcom,dump-size = <0x3a0>;
qcom,dump-id = <0x47>;
};
};
l1_itlb600 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x26>;
};
l2 {
l2_cache400 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc4>;
};
l1_itlb700 {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x27>;
};
l2_cache500 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc5>;
};
l1_dtlb400 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x44>;
};
l2_cache600 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc6>;
};
l1_dtlb500 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x45>;
};
l2_cache700 {
qcom,dump-size = <0x120100>;
qcom,dump-id = <0xc7>;
};
l1_dtlb600 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x46>;
};
l2_tlb0 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x120>;
};
l1_dtlb700 {
qcom,dump-size = <0x3a0>;
qcom,dump-id = <0x47>;
};
l2_tlb100 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x121>;
};
l2_cache400 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc4>;
};
l2_tlb200 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x122>;
};
l2_cache500 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc5>;
};
l2_tlb300 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x123>;
};
l2_cache600 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc6>;
};
l2_tlb400 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x124>;
};
l2_cache700 {
qcom,dump-size = <0x120100>;
qcom,dump-id = <0xc7>;
};
l2_tlb500 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x125>;
};
l2_tlb0 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x120>;
};
l2_tlb600 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x126>;
};
l2_tlb100 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x121>;
};
l2_tlb200 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x122>;
};
l2_tlb300 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x123>;
};
l2_tlb400 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x124>;
};
l2_tlb500 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x125>;
};
l2_tlb600 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x126>;
};
l2_tlb700 {
qcom,dump-size = <0xc100>;
qcom,dump-id = <0x127>;
};
rpmh {
qcom,dump-size = <0x400000>;
qcom,dump-id = <0xec>;
};
rpm_sw {
qcom,dump-size = <0x28000>;
qcom,dump-id = <0xea>;
};
pmic {
qcom,dump-size = <0x200000>;
qcom,dump-id = <0xe4>;
};
fcm {
qcom,dump-size = <0x8400>;
qcom,dump-id = <0xee>;
};
etf_swao {
qcom,dump-size = <0x10000>;
qcom,dump-id = <0xf1>;
};
etr_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x100>;
};
etr1_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x105>;
};
etfswao_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x102>;
};
misc_data {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0xe8>;
};
etf_lpass {
qcom,dump-size = <0x4000>;
qcom,dump-id = <0xf4>;
};
etflpass_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x104>;
};
osm_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x163>;
};
pcu_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x164>;
};
fsm_data {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x165>;
l2_tlb700 {
qcom,dump-size = <0xc100>;
qcom,dump-id = <0x127>;
};
};
};
};
};

1
qcom/parrot-pmic-overlay.dtsi
View File

@@ -406,6 +406,7 @@
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,old-i2c-freq-cfg;
pm8010i@8 {
compatible = "qcom,i2c-pmic";

40
qcom/parrot-qupv3.dtsi
View File

@@ -82,7 +82,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>;
@@ -101,7 +101,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
@@ -124,7 +124,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
@@ -148,7 +148,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
@@ -171,7 +171,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
@@ -195,7 +195,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
@@ -219,7 +219,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
@@ -243,7 +243,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
@@ -266,7 +266,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
@@ -290,7 +290,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
@@ -313,7 +313,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
@@ -384,7 +384,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
@@ -406,7 +406,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
@@ -430,7 +430,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>;
@@ -453,7 +453,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>,
@@ -477,7 +477,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
@@ -500,7 +500,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
@@ -524,7 +524,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
@@ -547,7 +547,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
@@ -572,7 +572,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se11_default_cts>, <&qupv3_se11_default_rts>,

19
qcom/parrot-vm.dtsi
View File

@@ -4,6 +4,7 @@
*/
#include "waipio-vm.dtsi"
#include <dt-bindings/clock/qcom,gcc-parrot.h>
/ {
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
@@ -35,6 +36,13 @@
status = "disabled";
};
gcc: clock-controller@100000 {
compatible = "qcom,dummycc";
clock-output-names = "gcc_clocks";
#clock-cells = <1>;
#reset-cells = <1>;
};
vgic: interrupt-controller@17200000 {
compatible = "arm,gic-v3";
interrupt-controller;
@@ -74,7 +82,8 @@
/delete-node/ spi@990000;
qup_iommu_group: qup_common_iommu_group {
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>,
<&qupv3_1 0x00000000 0x00020000>;
};
gpi_dma1: qcom,gpi-dma@a00000 {
@@ -84,6 +93,7 @@
reg-names = "gpi-top";
iommus = <&apps_smmu 0x418 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
@@ -109,9 +119,16 @@
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0x418 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
memory-region = <&qup_iommu_group>;
dma-coherent;
ranges;
status = "ok";
/* TUI over I2C */

17
qcom/platform_map.bzl
View File

@@ -10,6 +10,15 @@ _platform_map = {
# keep sorted
],
},
"sdxkova.cpe.wkk": {
"dtb_list": [
# keep sorted
{"name": "sdxkova-idp-cpe.dtb"},
],
"dtbo_list": [
# keep sorted
],
},
"sun": {
"dtb_list": [
# keep sorted
@@ -73,6 +82,14 @@ _platform_map = {
"name": "tuna-rumi-overlay.dtbo",
"apq": False,
},
{"name": "tuna-atp-overlay.dtbo"},
{"name": "tuna-cdp-overlay.dtbo"},
{"name": "tuna-mtp-kiwi-overlay.dtbo"},
{"name": "tuna-mtp-overlay.dtbo"},
{"name": "tuna-mtp-qmp1000-overlay.dtbo"},
{"name": "tuna-qrd-overlay.dtbo"},
{"name": "tuna-rcm-kiwi-overlay.dtbo"},
{"name": "tuna-rcm-overlay.dtbo"},
],
},
"kera": {

87
qcom/pmx75.dtsi Normal file
View File

@@ -0,0 +1,87 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pmx75@1 {
compatible = "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmx75_tz: qcom,temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmx75_vbus_detect: qcom,pmd-vbus-det@1500 {
compatible = "qcom,pm8941-misc";
reg = <0x1500>;
interrupts = <0x1 0x15 0x0 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "usb_vbus";
status = "disabled";
};
pmx75_gpios: pinctrl@8800 {
compatible = "qcom,pmx75-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmx75_pwm: pwms@e800 {
compatible = "qcom,pwm-lpg";
reg = <0xe800>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <4>;
};
pmx75_eusb2_repeater: qcom,eusb2-repeater@fd00 {
compatible = "qcom,pmic-eusb2-repeater";
reg = <0xfd00>;
status = "disabled";
};
};
};
&thermal_zones {
pmx75_temp_alarm: pmx75_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmx75_tz>;
trips {
pmx75_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmx75_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
pmx75_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

2
qcom/ravelin-coresight.dtsi
View File

@@ -553,7 +553,7 @@
coresight-name = "coresight-snoc";
qcom,dummy-source;
atid = <125>;
atid = <108>;
out-ports {
port {
snoc_out_funnel_in0: endpoint {

1
qcom/ravelin-idp.dtsi
View File

@@ -12,6 +12,7 @@
&qupv3_se8_i2c {
awinic@64 {
compatible = "awinic,aw2016_led";
reg = <0x64>;
awinic,red {

1
qcom/ravelin-pmic-overlay.dtsi
View File

@@ -472,6 +472,7 @@
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,old-i2c-freq-cfg;
pm8010m@8 {
compatible = "qcom,i2c-pmic";

36
qcom/ravelin-qupv3.dtsi
View File

@@ -82,7 +82,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>,
@@ -106,7 +106,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
@@ -125,7 +125,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
@@ -146,7 +146,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
@@ -170,7 +170,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
@@ -193,7 +193,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
@@ -217,7 +217,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
@@ -241,7 +241,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
@@ -264,7 +264,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
@@ -334,7 +334,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
@@ -353,7 +353,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
@@ -376,7 +376,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
@@ -400,7 +400,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
@@ -423,7 +423,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
@@ -447,7 +447,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
@@ -471,7 +471,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
@@ -495,7 +495,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
@@ -518,7 +518,7 @@
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;

6
qcom/ravelin.dtsi
View File

@@ -1765,8 +1765,8 @@
compatible = "qcom,sdhci-msm-v5";
reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>,
<0x007C8000 0x8000>, <0x007D0000 0x9000>;
reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm";
<0x007C8000 0x18000>;
reg-names = "hc", "cqhci", "ice";
iommus = <&apps_smmu 0x560 0x0>;
qcom,iommu-dma = "fastmap";
@@ -1781,6 +1781,7 @@
nvmem-cells = <&boot_config>;
nvmem-cell-names = "boot_conf";
qcom,ice-use-hwkm;
bus-width = <8>;
non-removable;
supports-cqe;
@@ -2574,6 +2575,7 @@
&qupv3_se8_i2c {
status = "ok";
fsa4480: fsa4480@42 {
compatible = "qcom,fsa4480-i2c";
reg = <0x42>;
};
};

49
qcom/sdxkova-idp-cpe.dtsi
View File

@@ -2,3 +2,52 @@
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sdxkova-pmic-overlay.dtsi"
&sdhc_1 {
status = "ok";
reg = <0x0 0x08804000 0x0 0x1000>, <0x0 0x08805000 0x0 0x1000>;
reg-names = "hc", "cqhci";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
bus-width = <8>;
no-sd;
non-removable;
supports-cqe;
cap-mmc-hw-reset;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x000F442C 0x0 0x01
0x090106C0 0x80040868>;
/* Add dt entry for gcc hw reset */
resets = <&gcc GCC_EMMC_BCR>;
reset-names = "core_reset";
vdd-supply = <&vreg_sdc1_emmc_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L6B>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_emmc_on>;
pinctrl-1 = <&sdc1_emmc_off>;
operating-points-v2 = <&sdhc1_opp_table>;
};
&pmx75_vbus_detect {
status = "ok";
};

63
qcom/sdxkova-idp-mbb.dtsi
View File

@@ -2,3 +2,66 @@
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include "sdxkova-pmic-overlay.dtsi"
#include "pm7550ba.dtsi"
&sdhc_1 {
status = "disabled";
no-mmc;
max-frequency = <192000000>;
vdd-supply = <&vreg_sdc1_emmc_sd_vdd>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&vreg_sdc1_sd_ls_vccb>;
qcom,vdd-io-voltage-level = <1800000 2850000>;
qcom,vdd-io-current-level = <0 22000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_sd_on>;
pinctrl-1 = <&sdc1_sd_off>;
cd-gpios = <&tlmm 103 GPIO_ACTIVE_LOW>;
operating-points-v2 = <&sdhc2_opp_table>;
};
&pmk8550_vadc {
/* PM8550BA Channel nodes */
pm7550ba_offset_ref {
status = "ok";
};
pm7550ba_vref_1p25 {
status = "ok";
};
pm7550ba_die_temp {
status = "ok";
};
pm7550ba_vph_pwr {
status = "ok";
};
pm7550ba_chg_temp {
status = "ok";
};
pm7550ba_iin_fb {
status = "ok";
};
pm7550ba_ichg_fb {
status = "ok";
};
};
&pm7550ba_tz {
io-channels = <&pmk8550_vadc PM7550BA_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};

396
qcom/sdxkova-pmic-overlay.dtsi Normal file
View File

@@ -0,0 +1,396 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm7550ba.h>
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmx75.h>
#include "pmk8550.dtsi"
#include "pmx75.dtsi"
/ {
vreg_sdc1_sd_ls_vccb: sdc1-sd-ls-gpio-regulator {
compatible = "regulator-gpio";
regulator-name = "sdc1_sd_ls_vccb";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2850000>;
enable-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
states = <1800000 0>,
<2850000 1>;
startup-delay-us = <5000>;
enable-active-high;
};
vreg_sdc1_emmc_sd_vdd: sdc1-emmc-sd-fixed-regulator {
compatible = "qcom,stub-regulator";
regulator-name = "sdc1_emmc_sd_vdd";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
parent-supply = <&vreg_sdc1_sd_ls_vccb>;
};
};
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pmg1110@a {
compatible = "qcom,spmi-pmic";
reg = <10 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmg1110_tz: qcom,temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
};
};
&thermal_zones {
pmg1110_temp_alarm: pmg1110_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmg1110_tz>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
&pmk8550_vadc {
/delete-node/ pm8550_offset_ref;
/delete-node/ pm8550_vref_1p25;
/delete-node/ pm8550_die_temp;
/delete-node/ pm8550_vph_pwr;
/* PM8550BA Channel nodes */
pm7550ba_offset_ref {
reg = <PM7550BA_ADC5_GEN3_OFFSET_REF>;
label = "pm7550ba_offset_ref";
qcom,pre-scaling = <1 1>;
status = "disabled";
};
pm7550ba_vref_1p25 {
reg = <PM7550BA_ADC5_GEN3_1P25VREF>;
label = "pm7550ba_vref_1p25";
qcom,pre-scaling = <1 1>;
status = "disabled";
};
pm7550ba_die_temp {
reg = <PM7550BA_ADC5_GEN3_DIE_TEMP>;
label = "pm7550ba_die_temp";
qcom,pre-scaling = <1 1>;
status = "disabled";
};
pm7550ba_vph_pwr {
reg = <PM7550BA_ADC5_GEN3_VPH_PWR>;
label = "pm7550ba_vph_pwr";
qcom,pre-scaling = <1 3>;
status = "disabled";
};
pm7550ba_chg_temp {
reg = <PM7550BA_ADC5_GEN3_CHG_TEMP_V>;
label = "pm7550ba_chg_temp";
status = "disabled";
};
pm7550ba_iin_fb {
reg = <PM7550BA_ADC5_GEN3_IIN_FB>;
label = "pm7550ba_iin_fb";
status = "disabled";
};
pm7550ba_ichg_fb {
reg = <PM7550BA_ADC5_GEN3_ICHG_FB>;
label = "pm7550ba_ichg_fb";
status = "disabled";
};
/* PMX75 Channel nodes */
pmx75_offset_ref {
reg = <PMX75_ADC5_GEN3_OFFSET_REF>;
label = "pmx75_offset_ref";
qcom,pre-scaling = <1 1>;
};
pmx75_vref_1p25 {
reg = <PMX75_ADC5_GEN3_1P25VREF>;
label = "pmx75_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pmx75_die_temp {
reg = <PMX75_ADC5_GEN3_DIE_TEMP>;
label = "pmx75_die_temp";
qcom,pre-scaling = <1 1>;
};
pmx75_vph_pwr {
reg = <PMX75_ADC5_GEN3_VPH_PWR>;
label = "pmx75_vph_pwr";
qcom,pre-scaling = <1 3>;
};
pmx75_pa_therm1 {
reg = <PMX75_ADC5_GEN3_AMUX_THM1_100K_PU>;
label = "pmx75_pa_therm1";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pmx75_pa_therm2 {
reg = <PMX75_ADC5_GEN3_AMUX_THM2_100K_PU>;
label = "pmx75_pa_therm2";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pmx75_sdx_case_therm {
reg = <PMX75_ADC5_GEN3_AMUX_THM3_100K_PU>;
label = "pmx75_sdx_case_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pmx75_ambient_therm {
reg = <PMX75_ADC5_GEN3_AMUX_THM4_100K_PU>;
label = "pmx75_ambient_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pmx75_qtm_therm {
reg = <PMX75_ADC5_GEN3_AMUX_THM5_100K_PU>;
label = "pmx75_qtm_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pmx75_sdr_skin_therm {
reg = <PMX75_ADC5_GEN3_AMUX_THM6_100K_PU>;
label = "pmx75_sdr_skin_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
};
&pmx75_tz {
io-channels = <&pmk8550_vadc PMX75_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&thermal_zones {
sys-therm-1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM1_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM2_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM3_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM4_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM5_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-6 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM6_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
xo-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
pmg1110_temp_alarm: pmg1110_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmg1110_tz>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
&soc {
pmic-pon-log {
compatible = "qcom,pmic-pon-log";
nvmem = <&pmk8550_sdam_5>, <&pmk8550_sdam_6>;
nvmem-names = "pon_log0", "pon_log1";
};
reboot_reason {
compatible = "qcom,reboot-reason";
nvmem-cells = <&restart_reason>;
nvmem-cell-names = "restart_reason";
};
};

554
qcom/sdxkova-regulators.dtsi Normal file
View File

@@ -0,0 +1,554 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
&apps_rsc_drv2 {
rpmh-regulator-msslvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "mss.lvl";
VDD_MODEM_LEVEL: VDD_MSS_LEVEL: S1B_LEVEL:
pmx75_s1_level: regulator-pmx75-s1-level {
regulator-name = "pmx75_s1_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-mxclvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "mxc.lvl";
proxy-supply = <&VDD_MXC_LEVEL>;
VDD_MXC_LEVEL: S3B_LEVEL:
pmx75_s3_level: regulator-pmx75-s3-level {
regulator-name = "pmx75_s3_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-voltage =
<RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_MAX>;
};
};
rpmh-regulator-mxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "mx.lvl";
proxy-supply = <&VDD_MXA_LEVEL>;
VDD_MXA_LEVEL: VDD_MX_LEVEL: L17B_LEVEL:
pmx75_l17_level: regulator-pmx75-l17-level {
regulator-name = "pmx75_l17_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-voltage =
<RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_MXA_LEVEL_AO: VDD_MX_LEVEL_AO: L17B_LEVEL_AO:
pmx75_l17_level_ao: regulator-pmx75-l17-level-ao {
regulator-name = "pmx75_l17_level_ao";
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-cxlvl {
compatible = "qcom,rpmh-arc-regulator";
qcom,resource-name = "cx.lvl";
proxy-supply = <&VDD_CX_LEVEL>;
VDD_CX_LEVEL: S5B_LEVEL:
pmx75_s5_level: regulator-pmx75-s5-level {
regulator-name = "pmx75_s5_level";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,proxy-consumer-enable;
qcom,proxy-consumer-voltage =
<RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_MAX>;
};
VDD_CX_LEVEL_AO: S5B_LEVEL_AO:
pmx75_s5_level_ao: regulator-pmx75-s5-level-ao {
regulator-name = "pmx75_s5_level_ao";
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
regulator-min-microvolt =
<RPMH_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,init-voltage-level =
<RPMH_REGULATOR_LEVEL_RETENTION>;
};
};
rpmh-regulator-smpb2 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb2";
S2B: pmx75_s2: regulator-pmx75-s2 {
regulator-name = "pmx75_s2";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1224000>;
regulator-max-microvolt = <1350000>;
qcom,init-voltage = <1224000>;
};
};
rpmh-regulator-smpb4 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb4";
S4B: pmx75_s4: regulator-pmx75-s4 {
regulator-name = "pmx75_s4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1824000>;
regulator-max-microvolt = <1904000>;
qcom,init-voltage = <1824000>;
};
};
rpmh-regulator-smpb7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb7";
S7B: pmx75_s7: regulator-pmx75-s7 {
regulator-name = "pmx75_s7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <352000>;
regulator-max-microvolt = <1060000>;
qcom,init-voltage = <936000>;
};
};
rpmh-regulator-smpb8 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb8";
S8B: pmx75_s8: regulator-pmx75-s8 {
regulator-name = "pmx75_s8";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1100000>;
qcom,init-voltage = <824000>;
};
};
rpmh-regulator-smpb9 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpb9";
S9B: pmx75_s9: regulator-pmx75-s9 {
regulator-name = "pmx75_s9";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1040000>;
qcom,init-voltage = <800000>;
};
};
rpmh-regulator-ldob1 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob1";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L1B: pmx75_l1: regulator-pmx75-l1 {
regulator-name = "pmx75_l1";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob2 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob2";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L2B: pmx75_l2: regulator-pmx75-l2 {
regulator-name = "pmx75_l2";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1160000>;
qcom,init-voltage = <1128000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob3 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob3";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L3B: pmx75_l3: regulator-pmx75-l3 {
regulator-name = "pmx75_l3";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1040000>;
qcom,init-voltage = <896000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob4 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob4";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L4B: pmx75_l4: regulator-pmx75-l4 {
regulator-name = "pmx75_l4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <864000>;
regulator-max-microvolt = <912000>;
qcom,init-voltage = <880000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob5 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob5";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L5B: pmx75_l5: regulator-pmx75-l5 {
regulator-name = "pmx75_l5";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1770000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1776000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob6 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob6";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L6B: pmx75_l6: regulator-pmx75-l6 {
regulator-name = "pmx75_l6";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob7";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L7B: pmx75_l7: regulator-pmx75-l7 {
regulator-name = "pmx75_l7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <960000>;
qcom,init-voltage = <904000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob8 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob8";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L8B: pmx75_l8: regulator-pmx75-l8 {
regulator-name = "pmx75_l8";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
qcom,init-voltage = <800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob9 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob9";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L9B: pmx75_l9: regulator-pmx75-l9 {
regulator-name = "pmx75_l9";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <752000>;
regulator-max-microvolt = <800000>;
qcom,init-voltage = <752000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob10 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob10";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L10B: pmx75_l10: regulator-pmx75-l10 {
regulator-name = "pmx75_l10";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3088000>;
qcom,init-voltage = <3080000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob11 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob11";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L11B: pmx75_l11: regulator-pmx75-l11 {
regulator-name = "pmx75_l11";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob12 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob12";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L12B: pmx75_l12: regulator-pmx75-l12 {
regulator-name = "pmx75_l12";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob13 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob13";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L13B: pmx75_l13: regulator-pmx75-l13 {
regulator-name = "pmx75_l13";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob14 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob14";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L14B: pmx75_l14: regulator-pmx75-l14 {
regulator-name = "pmx75_l14";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <800000>;
qcom,init-voltage = <624000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob15 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob15";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L15B: pmx75_l15: regulator-pmx75-l15 {
regulator-name = "pmx75_l15";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob16 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob16";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L16B: pmx75_l16: regulator-pmx75-l16 {
regulator-name = "pmx75_l16";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <920000>;
qcom,init-voltage = <912000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob19 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob19";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L19B: pmx75_l19: regulator-pmx75-l19 {
regulator-name = "pmx75_l19";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <960000>;
qcom,init-voltage = <952000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob20 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob20";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L20B: pmx75_l20: regulator-pmx75-l20 {
regulator-name = "pmx75_l20";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <952000>;
qcom,init-voltage = <912000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldob21 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldob21";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L21B: pmx75_l21: regulator-pmx75-l21 {
regulator-name = "pmx75_l21";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1000000>;
qcom,init-voltage = <856000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-smpk1 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpk1";
S1K: pmg1110_s1: regulator-pmg1110-s1 {
regulator-name = "pmg1110_s1";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
qcom,init-voltage = <916000>;
};
};
};

2
qcom/sdxkova-reserved-memory.dtsi
View File

@@ -64,6 +64,8 @@
};
smem_mem: smem_region@87e20000 {
compatible = "qcom,smem";
hwlocks = <&tcsr_mutex 3>;
no-map;
reg = <0x0 0x87e20000 0x0 0xc0000>;
};

235
qcom/sdxkova-usb.dtsi Normal file
View File

@@ -0,0 +1,235 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/phy/qcom,usb3-4nm-qmp-uni.h>
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
&soc {
usb: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0x0 0xa600000 0x0 0x100000>;
reg-names = "core_base";
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_RISING>,
<&pdc 9 IRQ_TYPE_EDGE_RISING>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event_irq", "dp_hs_phy_irq",
"dm_hs_phy_irq", "ss_phy_irq";
qcom,use-pdc-interrupts;
USB3_GDSC-supply = <&gcc_usb30_gdsc>;
clocks = <&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_USB30_SLV_AHB_CLK>,
<&gcc GCC_USB30_MSTR_AXI_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>;
clock-names = "core_clk", "iface_clk",
"bus_aggr_clk", "utmi_clk",
"sleep_clk";
resets = <&gcc GCC_USB30_BCR>;
reset-names = "core_reset";
qcom,sleep-clk-bcr;
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,core-clk-rate-disconnected = <133333333>;
dwc3: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0x0 0xa600000 0x0 0xd93c>;
iommus = <&apps_smmu 0x80 0x0>;
qcom,iommu-dma = "atomic";
memory-region = <&dwc3_mem_region>;
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb_nop_phy>, <&usb_qmp_phy>;
snps,has-lpm-erratum;
snps,is-utmi-l1-suspend;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis_u2_susphy_quirk;
snps,hird-threshold = /bits/ 8 <0x10>;
tx-fifo-resize;
/* set host mode interrupt moderation to 1 us */
imod-interval-ns = <1000>;
maximum-speed = "super-speed-plus";
usb-role-switch;
dr_mode = "peripheral";
};
};
dwc3_mem_region: dwc3_mem_region {
iommu-addresses = <&dwc3 0x0 0x0 0x0 0x90000000>,
<&dwc3 0x0 0xf0000000 0xffffffff 0x10000000>;
};
/* USB port related QMP USB UNI PHY */
usb_qmp_phy: ssphy@ff6000 {
compatible = "qcom,usb-ssphy-qmp-v2";
reg = <0x0 0xff6000 0x0 0x2000>,
<0x0 0xff7400 0x0 0x4>;
reg-names = "qmp_phy_base",
"pcs_clamp_enable_reg";
vdd-supply = <&L4B>;
qcom,vdd-voltage-level = <0 880000 880000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&L1B>;
qcom,core-max-load-uA = <15000>;
usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK>,
<&gcc GCC_USB3_PHY_PIPE_CLK_SRC>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
<&gcc GCC_USB3_PRIM_CLKREF_EN>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
"pipe_clk_ext_src", "ref_clk", "ref_clk_src",
"cfg_ahb_clk";
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy_reset", "phy_phy_reset";
qcom,qmp-phy-init-seq =
/* <reg_offset, value> */
<QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x9E
QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x06
QSERDES_COM_CP_CTRL_MODE1 0x02
QSERDES_COM_PLL_RCTRL_MODE1 0x16
QSERDES_COM_PLL_CCTRL_MODE1 0x36
QSERDES_COM_CORECLK_DIV_MODE1 0x04
QSERDES_COM_LOCK_CMP1_MODE1 0x2E
QSERDES_COM_LOCK_CMP2_MODE1 0x82
QSERDES_COM_DEC_START_MODE1 0x82
QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
QSERDES_COM_HSCLK_SEL_1 0x01
QSERDES_COM_VCO_TUNE1_MODE1 0x25
QSERDES_COM_VCO_TUNE2_MODE1 0x02
QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xB7
QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xB7
QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x9E
QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x06
QSERDES_COM_CP_CTRL_MODE0 0x02
QSERDES_COM_PLL_RCTRL_MODE0 0x16
QSERDES_COM_PLL_CCTRL_MODE0 0x36
QSERDES_COM_LOCK_CMP1_MODE0 0x12
QSERDES_COM_LOCK_CMP2_MODE0 0x34
QSERDES_COM_DEC_START_MODE0 0x82
QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
QSERDES_COM_VCO_TUNE1_MODE0 0x25
QSERDES_COM_VCO_TUNE2_MODE0 0x02
QSERDES_COM_BG_TIMER 0x0E
QSERDES_COM_SSC_EN_CENTER 0x01
QSERDES_COM_SSC_PER1 0x31
QSERDES_COM_SSC_PER2 0x01
QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
QSERDES_COM_SYSCLK_EN_SEL 0x1A
QSERDES_COM_LOCK_CMP_CFG 0x14
QSERDES_COM_VCO_TUNE_MAP 0x04
QSERDES_COM_CORE_CLK_EN 0x20
QSERDES_COM_CMN_CONFIG_1 0x16
QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0xB6
QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x4B
QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x37
QSERDES_COM_ADDITIONAL_MISC 0x0C
PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xC4
PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x89
PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
PCIE_USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
PCIE_USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21
PCIE_USB3_UNI_PCS_RX_SIGDET_LVL 0xAA
PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
PCIE_USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
PCIE_USB3_UNI_PCS_CDR_RESET_TIME 0x0A
PCIE_USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
PCIE_USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
PCIE_USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C
PCIE_USB3_UNI_PCS_EQ_CONFIG1 0x4B
PCIE_USB3_UNI_PCS_EQ_CONFIG5 0x10
QSERDES_TX_RES_CODE_LANE_TX 0x00
QSERDES_TX_RES_CODE_LANE_RX 0x00
QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x1F
QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x09
QSERDES_TX_LANE_MODE_1 0xF5
QSERDES_TX_LANE_MODE_3 0x3F
QSERDES_TX_LANE_MODE_4 0x3F
QSERDES_TX_LANE_MODE_5 0x5F
QSERDES_TX_RCV_DETECT_LVL_2 0x12
QSERDES_TX_PI_QEC_CTRL 0x21
QSERDES_RX_UCDR_FO_GAIN 0x0A
QSERDES_RX_UCDR_SO_GAIN 0x06
QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F
QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7F
QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF
QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F
QSERDES_RX_UCDR_PI_CONTROLS 0x99
QSERDES_RX_UCDR_SB2_THRESH1 0x08
QSERDES_RX_UCDR_SB2_THRESH2 0x08
QSERDES_RX_UCDR_SB2_GAIN1 0x00
QSERDES_RX_UCDR_SB2_GAIN2 0x0A
QSERDES_RX_AUX_DATA_TCOARSE_TFINE 0xA0
QSERDES_RX_VGA_CAL_CNTRL1 0x54
QSERDES_RX_VGA_CAL_CNTRL2 0x0F
QSERDES_RX_GM_CAL 0x13
QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F
QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4A
QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A
QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x07
QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00
QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
QSERDES_RX_SIGDET_CNTRL 0x04
QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E
QSERDES_RX_RX_MODE_00_LOW 0x3F
QSERDES_RX_RX_MODE_00_HIGH 0xBF
QSERDES_RX_RX_MODE_00_HIGH2 0xFF
QSERDES_RX_RX_MODE_00_HIGH3 0xDF
QSERDES_RX_RX_MODE_00_HIGH4 0xED
QSERDES_RX_RX_MODE_01_LOW 0xDC
QSERDES_RX_RX_MODE_01_HIGH 0x5C
QSERDES_RX_RX_MODE_01_HIGH2 0x9C
QSERDES_RX_RX_MODE_01_HIGH3 0x1D
QSERDES_RX_RX_MODE_01_HIGH4 0x09
QSERDES_RX_DFE_EN_TIMER 0x04
QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38
QSERDES_RX_DCC_CTRL1 0x0C
QSERDES_RX_VTH_CODE 0x10
QSERDES_RX_SIGDET_CAL_CTRL1 0x14
QSERDES_RX_SIGDET_CAL_TRIM 0x08
PCIE_USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
PCIE_USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
PCIE_USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
PCIE_USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00>;
qcom,qmp-phy-reg-offset =
<PCIE_USB3_UNI_PCS_PCS_STATUS1
PCIE_USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
PCIE_USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
PCIE_USB3_UNI_PCS_POWER_DOWN_CONTROL
PCIE_USB3_UNI_PCS_SW_RESET
PCIE_USB3_UNI_PCS_START_CONTROL>;
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
};

2010
qcom/sdxkova.dtsi
View File

File diff suppressed because it is too large Load Diff

2
qcom/sun-oemvm.dtsi
View File

@@ -76,7 +76,7 @@
vm-guid = "847bfe26-0b12-5728-812a-06103f6bdec0";
qcom,sensitive;
vm-attrs = "crash-fatal", "context-dump", "crash-restart";
vm-attrs = "context-dump", "crash-restart";
memory {
#address-cells = <0x2>;

4
qcom/sun-v2.dtsi
View File

@@ -18,6 +18,10 @@
compatible = "qcom,sun-cambistmclkcc-v2", "syscon";
};
&evacc {
compatible = "qcom,sun-evacc-v2", "syscon";
};
&tsens1 {
#qcom,sensors = <7>;
};

24
qcom/sun-vm-dma-heaps.dtsi
View File

@@ -39,6 +39,30 @@
qcom,dynamic-heap;
};
qcom,ms4 {
qcom,dma-heap-name = "qcom,ms4";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms5 {
qcom,dma-heap-name = "qcom,ms5";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms6 {
qcom,dma-heap-name = "qcom,ms6";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms7 {
qcom,dma-heap-name = "qcom,ms7";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,tui_test {
qcom,dma-heap-name = "qcom,tui_test";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;

2
qcom/sun-vm.dtsi
View File

@@ -102,7 +102,7 @@
vm-guid = "598085da-c516-5b25-a9c1-927a02819770";
qcom,sensitive;
vm-attrs = "crash-fatal", "context-dump", "crash-restart";
vm-attrs = "context-dump", "crash-restart";
iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0

2
qcom/sun.dtsi
View File

@@ -2566,7 +2566,7 @@
* device tree, but it is calculated in the driver.
*/
qcom,dll-hsr-list = <0x0007442C 0x0 0x10
0x090106C0 0x80040868>;
0x294106C0 0x80040868>;
iommus = <&apps_smmu 0x540 0x0>;
qcom,iommu-dma = "fastmap";

18
qcom/tuna-atp-overlay.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-atp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna ATP";
compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap",
"qcom,atp";
qcom,msm-id = <681 0x10000>, <655 0x10000>;
qcom,board-id = <33 0>;
};

6
qcom/tuna-atp.dtsi Normal file
View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-mtp.dtsi"

18
qcom/tuna-cdp-overlay.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna CDP";
compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap",
"qcom,cdp";
qcom,msm-id = <681 0x10000>, <655 0x10000>;
qcom,board-id = <1 0>;
};

4
qcom/tuna-cdp.dtsi Normal file
View File

@@ -0,0 +1,4 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/

12
qcom/tuna-dma-heaps.dtsi
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@@ -15,5 +15,17 @@
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&cdsp_secure_heap_cma>;
};
qcom,qseecom {
qcom,dma-heap-name = "qcom,qseecom";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_mem>;
};
qcom,qseecom_ta {
qcom,dma-heap-name = "qcom,qseecom-ta";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_ta_mem>;
};
};
};

17
qcom/tuna-mtp-kiwi-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-mtp-kiwi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
"qcom,mtp";
qcom,msm-id = <681 0x10000>, <655 0x10000>;
qcom,board-id = <8 2>;
};

6
qcom/tuna-mtp-kiwi.dtsi Normal file
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@@ -0,0 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-mtp.dtsi"

17
qcom/tuna-mtp-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
"qcom,mtp";
qcom,msm-id = <681 0x10000>, <655 0x10000>;
qcom,board-id = <8 0>;
};

17
qcom/tuna-mtp-qmp1000-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-mtp-qmp1000.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP QMP1000";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
"qcom,mtp";
qcom,msm-id = <681 0x10000>, <655 0x10000>;
qcom,board-id = <8 1>;
};

6
qcom/tuna-mtp-qmp1000.dtsi Normal file
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@@ -0,0 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-mtp.dtsi"

4
qcom/tuna-mtp.dtsi Normal file
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@@ -0,0 +1,4 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/

17
qcom/tuna-qrd-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna QRD";
compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap",
"qcom,qrd";
qcom,msm-id = <681 0x10000>, <655 0x10000>;
qcom,board-id = <11 0>;
};

4
qcom/tuna-qrd.dtsi Normal file
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@@ -0,0 +1,4 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/

17
qcom/tuna-rcm-kiwi-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-rcm-kiwi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna RCM + kiwi WLAN";
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap",
"qcom,rcm";
qcom,msm-id = <681 0x10000>, <655 0x10000>;
qcom,board-id = <21 1>;
};

6
qcom/tuna-rcm-kiwi.dtsi Normal file
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@@ -0,0 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-cdp.dtsi"

17
qcom/tuna-rcm-overlay.dts Normal file
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@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-rcm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna RCM";
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap",
"qcom,rcm";
qcom,msm-id = <681 0x10000>, <655 0x10000>;
qcom,board-id = <21 0>;
};

6
qcom/tuna-rcm.dtsi Normal file
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@@ -0,0 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-cdp.dtsi"

30
qcom/tuna-vm-dma-heaps.dtsi Normal file
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@@ -0,0 +1,30 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
&soc {
qcom,dma-heaps {
compatible = "qcom,dma-heaps";
depends-on-supply = <&qcom_scm>;
qcom,ms1 {
qcom,dma-heap-name = "qcom,ms1";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms2 {
qcom,dma-heap-name = "qcom,ms2";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
qcom,ms3 {
qcom,dma-heap-name = "qcom,ms3";
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
qcom,dynamic-heap;
};
};
};

24
qcom/tuna-walt.dtsi Normal file
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@@ -0,0 +1,24 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
walt {
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom,cycle-cntr {
compatible = "qcom,epss";
reg = <0x17D91000 0x1000>,
<0x17D92000 0x1000>,
<0x17D93000 0x1000>,
<0x17D94000 0x1000>;
reg-names = "freq-domain0",
"freq-domain1",
"freq-domain2",
"freq-domain3";
};
};
};

219
qcom/tuna.dtsi
View File

@@ -358,12 +358,21 @@
#include "tuna-reserved-memory.dtsi"
#include "msm-arm-smmu-tuna.dtsi"
#include "tuna-dma-heaps.dtsi"
#include "tuna-vm-dma-heaps.dtsi"
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cdsp_eva_mem: cdsp_eva_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
};
/* global autoconfigured region for contiguous allocations */
system_cma: linux,cma {
compatible = "shared-dma-pool";
@@ -375,6 +384,21 @@
};
};
&firmware {
qcom_scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x19000>;
};
qcom_smcinvoke {
compatible = "qcom,smcinvoke";
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -442,6 +466,11 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
qcom,hdcp {
compatible = "qcom,hdcp";
qcom,use-smcinvoke = <1>;
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
@@ -510,6 +539,20 @@
};
};
cache-controller@24800000 {
compatible = "qcom,tuna-llcc";
reg = <0x24800000 0x200000>, <0x25800000 0x200000>,
<0x24C00000 0x200000>, <0x25C00000 0x200000>,
<0x26800000 0x200000>, <0x26C00000 0x200000>;
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
"llcc3_base", "llcc_broadcast_or_base",
"llcc_broadcast_and_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
cap-based-alloc-and-pwr-collapse;
};
apps_rsc: rsc@17a00000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
@@ -654,7 +697,7 @@
pdc: interrupt-controller@b220000 {
compatible = "qcom,tuna-pdc", "qcom,pdc";
reg = <0xb220000 0x10000>, <0x17c000f0 0x60>;
reg = <0xb220000 0x10000>, <0x174000f0 0x64>;
qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>,
<10 230 1>, <11 724 1>, <12 716 1>,
<13 727 1>, <14 720 1>, <15 726 1>,
@@ -683,6 +726,36 @@
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
qcom,gpios-reserved = <54>;
};
slimbam: bamdma@6c04000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x6c04000 0x20000>, <0x6c8f000 0x1000>;
reg-names = "bam", "bam_remote_mem";
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
num-channels = <31>;
#dma-cells = <1>;
qcom,controlled-remotely;
qcom,ee = <1>;
qcom,num-ees = <2>;
};
slim_msm: slim@6c40000 {
compatible = "qcom,slim-ngd-v1.5.0";
reg = <0x6c40000 0x2c000>, <0x6c8E000 0x1000>;
reg-names = "ctrl", "slimbus_remote_mem";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&slimbam 3>, <&slimbam 4>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
qcom,sps {
compatible = "qcom,msm-sps-4k";
qcom,pipe-attr-ee;
};
tcsr_mutex_block: syscon@1f40000 {
@@ -743,6 +816,14 @@
#mbox-cells = <1>;
};
qcom,tmecom-qmp-client {
compatible = "qcom,tmecom-qmp-client";
mboxes = <&qmp_tme 0>;
mbox-names = "tmecom";
label = "tmecom";
depends-on-supply = <&qmp_tme>;
};
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
@@ -867,6 +948,28 @@
};
};
qcom,smp2p-wpss {
compatible = "qcom,smp2p";
qcom,smem = <617>, <616>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <13>;
wpss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
wpss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-soccp {
compatible = "qcom,smp2p";
qcom,smem = <617>, <616>;
@@ -1250,13 +1353,17 @@
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>;
reg-names = "ufs_mem";
reg = <0x1d84000 0x3000>,
<0x1d88000 0x18000>;
reg-names = "ufs_mem", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
qcom,ice-use-hwkm;
lanes-per-direction = <2>;
clock-names =
"core_clk",
@@ -1310,6 +1417,69 @@
status = "disabled";
};
qcom_tzlog: tz-log@14680720 {
compatible = "qcom,tz-log";
reg = <0x14680720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
tmecrashdump-address-offset = <0x81CA0000>;
};
qcom_cedev: qcedev@1de0000 {
compatible = "qcom,qcedev";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x28000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <2>;
qcom,offload-ops-support;
qcom,bam-pipe-offload-cpb-hlos = <1>;
qcom,bam-pipe-offload-hlos-cpb = <3>;
qcom,bam-pipe-offload-hlos-cpb-1 = <8>;
qcom,bam-pipe-offload-hlos-hlos = <4>;
qcom,bam-pipe-offload-hlos-hlos-1 = <9>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,bam-ee = <0>;
qcom,smmu-s1-enable;
qcom,no-clock-support;
qcom,no-clk-gating;
interconnect-names = "data_path";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
iommus = <&apps_smmu 0x0480 0x0>,
<&apps_smmu 0x0481 0x0>;
qcom,iommu-dma = "atomic";
dma-coherent;
qcom_cedev_ns_cb {
compatible = "qcom,qcedev,context-bank";
label = "ns_context";
iommus = <&apps_smmu 0x0481 0x0>;
dma-coherent;
};
qcom_cedev_s_cb {
compatible = "qcom,qcedev,context-bank";
label = "secure_context";
iommus = <&apps_smmu 0x0483 0x0>;
qcom,iommu-vmid = <0x9>;
qcom,secure-context-bank;
dma-noncoherent;
};
};
rng: rng@10c3000 {
compatible = "qcom,trng";
reg = <0x10c3000 0x1000>;
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc42d000 0x4000>,
@@ -1477,6 +1647,14 @@
};
};
gh-secure-vm-loader@2 {
compatible = "qcom,gh-secure-vm-loader";
qcom,pas-id = <35>;
qcom,vmid = <50>;
qcom,firmware-name = "cpusys_vm";
memory-region = <&cpusys_vm_mem>;
};
qcom,pmic_glink_log {
compatible = "qcom,qti-pmic-glink";
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
@@ -1628,6 +1806,16 @@
#size-cells = <2>;
ranges;
gunyah_hyp_mem: gunyah_hyp_region@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0xe00000>;
};
cpusys_vm_mem: cpusys_vm_region@80e00000 {
no-map;
reg = <0x0 0x80e00000 0x0 0x400000>;
};
aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
compatible = "qcom,cmd-db";
no-map;
@@ -1649,6 +1837,30 @@
alignment = <0x0 0x400000>;
size = <0x0 0x4800000>;
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
size = <0x0 0xc800000>;
alignment = <0x0 0x400000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
};
#include "tuna-pinctrl.dtsi"
@@ -1657,6 +1869,7 @@
#include "tuna-qupv3.dtsi"
#include "msm-rdbg.dtsi"
#include "tuna-pmic-overlay.dtsi"
#include "tuna-walt.dtsi"
&qupv3_se7_2uart {
status = "ok";