diff --git a/bindings/arm/msm/msm.yaml b/bindings/arm/msm/msm.yaml index 750ed4a5..30c87d0b 100644 --- a/bindings/arm/msm/msm.yaml +++ b/bindings/arm/msm/msm.yaml @@ -122,10 +122,35 @@ properties: - description: Qualcomm Technologies, Inc. TUNA items: - enum: + - qcom,tuna-atp + - qcom,atp + - qcom,tuna-cdp + - qcom,cdp + - qcom,tuna-mtp + - qcom,mtp + - qcom,tuna-qrd + - qcom,qrd + - qcom,tuna-rcm + - qcom,rcm - qcom,tuna-rumi - qcom,rumi - const: qcom,tuna + - description: Qualcomm Technologies, Inc. TUNAP + items: + - enum: + - qcom,tunap-atp + - qcom,atp + - qcom,tunap-cdp + - qcom,cdp + - qcom,tunap-mtp + - qcom,mtp + - qcom,tunap-qrd + - qcom,qrd + - qcom,tunap-rcm + - qcom,rcm + - const: qcom,tunap + - description: Qualcomm Technologies, Inc. KERA items: - enum: diff --git a/bindings/arm/msm/qcom,llcc.yaml b/bindings/arm/msm/qcom,llcc.yaml index ddbc78f4..eb7c6bdd 100644 --- a/bindings/arm/msm/qcom,llcc.yaml +++ b/bindings/arm/msm/qcom,llcc.yaml @@ -36,6 +36,7 @@ properties: - qcom,pineapple-llcc - qcom,sun-llcc - qcom,sdxpinn-llcc + - qcom,tuna-llcc - qcom,kera-llcc - qcom,x1e80100-llcc diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index 2de7c538..abdaa90e 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -19,6 +19,7 @@ properties: - qcom,pineapple-debugcc - qcom,sun-debugcc - qcom,parrot-debugcc + - qcom,sdx75-debugcc - qcom,sm4450-debugcc - qcom,monaco-debugcc diff --git a/bindings/clock/qcom,dispcc-sm8x50.yaml b/bindings/clock/qcom,dispcc-sm8x50.yaml index 68c671cb..81a14145 100644 --- a/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding for SM8x50 +title: Qualcomm Technologies, Inc. Display Clock & Reset Controller for SM8x50 maintainers: - Jonathan Marek @@ -19,6 +19,7 @@ description: | dt-bindings/clock/qcom,dispcc-sm8350.h dt-bindings/clock/qcom,dispcc-pineapple.h dt-bindings/clock/qcom,dispcc-sun.h + dt-bindings/clock/qcom,dispcc-tuna.h properties: compatible: @@ -29,6 +30,7 @@ properties: - qcom,sm8350-dispcc - qcom,pineapple-dispcc - qcom,sun-dispcc + - qcom,tuna-dispcc clocks: items: diff --git a/bindings/clock/qcom,evacc-sun.yaml b/bindings/clock/qcom,evacc-sun.yaml index 8c610f17..3bcdcf09 100644 --- a/bindings/clock/qcom,evacc-sun.yaml +++ b/bindings/clock/qcom,evacc-sun.yaml @@ -21,6 +21,7 @@ properties: enum: - qcom,sun-evacc - qcom,tuna-evacc + - qcom,sun-evacc-v2 clocks: items: diff --git a/bindings/i2c/qcom,i2c-msm-geni.yaml b/bindings/i2c/qcom,i2c-msm-geni.yaml index 3c6a4a2f..bc69e351 100644 --- a/bindings/i2c/qcom,i2c-msm-geni.yaml +++ b/bindings/i2c/qcom,i2c-msm-geni.yaml @@ -54,6 +54,11 @@ properties: reg: maxItems: 1 + qcom,old-i2c-freq-cfg: + type: boolean + deprecated: true + description: Configure the I2C bus speed using the older counter settings + required: - compatible - reg diff --git a/bindings/leds/leds-aw2016.yaml b/bindings/leds/leds-aw2016.yaml new file mode 100644 index 00000000..f73d69f7 --- /dev/null +++ b/bindings/leds/leds-aw2016.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/leds-aw2016.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AWINIC AW2016 3-channel LED Driver + +maintainers: + - Kamal Wadhwa + +description: | + AW2016 LED device supports 3 LED channels and the driver + register each channel as a single LED class device and + exports interfaces to update brightness, set timer trigger + and enable HW based blink functionalities. + +properties: + compatible: + const: awinic,aw2016_led + + reg: + description: | + The 7-bit I2C address for AW2016 chip. + +patternProperties: + "^awinic,[0-9a-z]+$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + awinic,name: + description: | + Name of the LED which will be register as the LED class + device name. + $ref: /schemas/types.yaml#/definitions/string + + awinic,id: + description: | + It represents the LED hardware channel index. The valid + values are 0, 1, 2. + $ref: /schemas/types.yaml#/definitions/uint32 + + awinic,imax: + description: | + The setting of the maximum current for the given LED channel, + the valid values are 0, 1, 2, 3, and the corresponding current + setting are 15mA, 30mA, 5mA, 10mA. + $ref: /schemas/types.yaml#/definitions/uint32 + + awinic,led-current: + description: | + The setting of the current when the LED channel is enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + + awinic,max-brightness: + description: | + The maximum brightness value for the LED class device. + $ref: /schemas/types.yaml#/definitions/uint32 + + awinic,rise-time-ms: + description: | + The duration of the led ramping from 0 to maximum brightness + when breath function is enabled. + + awinic,hold-time-ms: + description: | + The duration of the led staying at the maximum brightness + when breath function is enabled. + + awinic,fall-time-ms: + description: | + The duration of the led ramping down from maximum brightness + to 0 when breath function is enabled. + + awinic,off-time-ms: + description: | + The duration of the led staying at 0 brightness when breath + function is enabled. + + required: + - awinic,name + - awinic,id + - awinic,imax + - awinic,led-current + - awinic,max-brightness + - awinic,rise-time-ms + - awinic,hold-time-ms + - awinic,fall-time-ms + - awinic,off-time-ms + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + awinic@64 { + compatible = "awinic,aw2016_led"; + reg = <0x64>; + + awinic,red { + awinic,name = "red"; + awinic,id = <0>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,green { + awinic,name = "green"; + awinic,id = <1>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + + awinic,blue { + awinic,name = "blue"; + awinic,id = <2>; + awinic,imax = <2>; + awinic,led-current = <3>; + awinic,max-brightness = <255>; + awinic,rise-time-ms = <6>; + awinic,hold-time-ms = <0>; + awinic,fall-time-ms = <6>; + awinic,off-time-ms = <4>; + }; + }; +... diff --git a/bindings/pinctrl/qcom,pmic-gpio.yaml b/bindings/pinctrl/qcom,pmic-gpio.yaml index cc3fbe2a..7fda52d1 100644 --- a/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -56,6 +56,7 @@ properties: - qcom,pm8998-gpio - qcom,pma8084-gpio - qcom,pmd802x-gpio + - qcom,pmi632-gpio - qcom,pmi8950-gpio - qcom,pmi8994-gpio - qcom,pmi8998-gpio @@ -71,6 +72,7 @@ properties: - qcom,pms405-gpio - qcom,pmx55-gpio - qcom,pmx65-gpio + - qcom,pmx75-gpio - qcom,pmxr2230-gpio - enum: @@ -182,6 +184,7 @@ allOf: - qcom,pm8550ve-gpio - qcom,pm8950-gpio - qcom,pm7550ba-gpio + - qcom,pmi632-gpio then: properties: gpio-line-names: @@ -308,6 +311,7 @@ allOf: contains: enum: - qcom,pmx65-gpio + - qcom,pmx75-gpio - qcom,pm5100-gpio then: properties: @@ -465,6 +469,7 @@ $defs: - gpio1-gpio26 for pm8998 - gpio1-gpio22 for pma8084 - gpio1-gpio4 for pmd802x + - gpio1-gpio8 for pmi632 - gpio1-gpio2 for pmi8950 - gpio1-gpio10 for pmi8994 - gpio1-gpio18 for pmih010x @@ -481,6 +486,7 @@ $defs: - gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10 and gpio11) - gpio1-gpio16 for pmx65 + - gpio1-gpio16 for pmx75 - gpio1-gpio12 for pmxr2230 - gpio1-gpio16 for pm5100 diff --git a/bindings/remoteproc/qcom,adsp.yaml b/bindings/remoteproc/qcom,adsp.yaml index f4e4f22b..842ebec6 100644 --- a/bindings/remoteproc/qcom,adsp.yaml +++ b/bindings/remoteproc/qcom,adsp.yaml @@ -37,6 +37,7 @@ properties: - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - qcom,sdx55-mpss-pas + - qcom,sdxpinn-modem-pas - qcom,sm6350-adsp-pas - qcom,sm6350-cdsp-pas - qcom,sm6350-mpss-pas diff --git a/bindings/soc/qcom/qcom,dynpf.yaml b/bindings/soc/qcom/qcom,dynpf.yaml new file mode 100644 index 00000000..e014e55c --- /dev/null +++ b/bindings/soc/qcom/qcom,dynpf.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,dynpf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) DYNPF Driver + +maintainers: + - Amir Vajid + - Shivnandan Kumar + + +description: | + The Qualcomm Technologies, Inc. (QTI) DYNPF Driver provides a sysfs + interface to userspace to send parameters to CPUCP firmware over SCMI + in order to configure the DYNPF feature. + +properties: + compatible: + const: qcom,dynpf + +required: + - compatible + +additionalProperties: false + +examples: + - | + qcom_dynpf: qcom,dynpf { + compatible = "qcom,dynpf"; + }; diff --git a/qcom/Makefile b/qcom/Makefile index 6c58c159..6ee3d039 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -54,7 +54,15 @@ sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_B TUNA_BASE_DTB += tuna.dtb NOAPQ_TUNA_BOARDS += \ - tuna-rumi-overlay.dtbo + tuna-atp-overlay.dtbo \ + tuna-cdp-overlay.dtbo \ + tuna-mtp-kiwi-overlay.dtbo \ + tuna-mtp-overlay.dtbo \ + tuna-mtp-qmp1000-overlay.dtbo \ + tuna-qrd-overlay.dtbo \ + tuna-rcm-kiwi-overlay.dtbo \ + tuna-rcm-overlay.dtbo \ + tuna-rumi-overlay.dtbo sun-dtb-$(CONFIG_ARCH_TUNA) += \ $(call add-overlays, $(NOAPQ_TUNA_BOARDS),$(TUNA_BASE_DTB)) @@ -174,7 +182,10 @@ ifeq ($(CONFIG_ARCH_SDXKOVA), y) sdxkova-dtb-$(CONFIG_ARCH_SDXKOVA) += sdxkova-idp-cpe.dtb \ sdxkova-idp-mbb.dtb \ sdxkova-idp-m2.dtb -dtb-y += $(sdxkova-dtb-y) + +sdxkova-cpe-wkk-dtb-$(CONFIG_ARCH_SDXKOVA) += sdxkova-idp-cpe.dtb + +dtb-y += $($(MSM_ARCH)-dtb-y) endif diff --git a/qcom/ipcc-test-sdxkova.dtsi b/qcom/ipcc-test-sdxkova.dtsi new file mode 100644 index 00000000..d80e7ab2 --- /dev/null +++ b/qcom/ipcc-test-sdxkova.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ipcc-test.dtsi" + +&soc { + /delete-node/ ipcc-self-ping-adsp; + /delete-node/ ipcc-self-ping-cdsp; + /delete-node/ ipcc-self-ping-slpi; +}; + diff --git a/qcom/kera-usb.dtsi b/qcom/kera-usb.dtsi index a0a8cc17..7798569b 100644 --- a/qcom/kera-usb.dtsi +++ b/qcom/kera-usb.dtsi @@ -36,6 +36,11 @@ compatible = "snps,dwc3"; reg = <0xa600000 0xd93c>; + iommus = <&apps_smmu 0x40 0x0>; + qcom,iommu-dma = "bypass"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; + interrupts = ; snps,disable-clk-gating; snps,has-lpm-erratum; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 0fbeb4e6..bd553f2e 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -478,6 +478,160 @@ reg = <0x1fc0000 0x30000>; }; + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_smem_mailbox_1_out: qcom,smp2p-smem-mailbox-1-out { + qcom,entry-name = "smem-mailbox"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_smem_mailbox_1_in: qcom,smp2p-smem-mailbox-1-in { + qcom,entry-name = "smem-mailbox"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-soccp { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <19>; + + soccp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + soccp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + eud: qcom,msm-eud@88e0000 { compatible = "qcom,msm-eud"; interrupt-names = "eud_irq"; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 3928427b..bfcaacb2 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -190,7 +190,7 @@ soc: soc { }; chosen { - bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kpti=off kernel.panic_on_rcu_stall=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-3 ftrace_dump_on_oops fw_devlink.strict=1 printk.console_no_auto_verbose=1 irqaffinity=0-2 cpufreq.default_governor=performance slub_debug=- randomize_kstack_offset=on "; + bootargs = "loglevel=6 log_buf_len=256K kpti=off kernel.panic_on_rcu_stall=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-3 ftrace_dump_on_oops fw_devlink.strict=1 printk.console_no_auto_verbose=1 irqaffinity=0-2 cpufreq.default_governor=performance slub_debug=- randomize_kstack_offset=on "; }; reserved_memory: reserved-memory { @@ -1678,9 +1678,8 @@ sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x04744000 0x1000>, <0x04745000 0x1000>, - <0x04748000 0x8000>, <0x04750000 0x9000>; - reg-names = "hc", "cqhci", "cqhci_ice", - "cqhci_ice_hwkm"; + <0x04748000 0x18000>; + reg-names = "hc", "cqhci", "ice"; iommus = <&apps_smmu 0xC0 0x0>; qcom,iommu-dma = "bypass"; @@ -1689,6 +1688,7 @@ ; interrupt-names = "hc_irq", "pwr_irq"; + qcom,ice-use-hwkm; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; diff --git a/qcom/msm-arm-smmu-sun.dtsi b/qcom/msm-arm-smmu-sun.dtsi index 88ddefaf..5367ee31 100644 --- a/qcom/msm-arm-smmu-sun.dtsi +++ b/qcom/msm-arm-smmu-sun.dtsi @@ -281,7 +281,7 @@ compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; reg = <0x7d3000 0x1000>; qcom,stream-id-range = <0xc00 0x400>; - qcom,iova-width = <34>; + qcom,iova-width = <32>; interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; @@ -299,7 +299,7 @@ compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; reg = <0x16cd000 0x1000>; qcom,stream-id-range = <0x1400 0x400>; - qcom,iova-width = <36>; + qcom,iova-width = <32>; interconnects = <&pcie_noc MASTER_PCIE_3 &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; qcom,opt-out-tbu-halting; @@ -309,7 +309,7 @@ compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; reg = <0x17d1000 0x1000>; qcom,stream-id-range = <0x1800 0x400>; - qcom,iova-width = <36>; + qcom,iova-width = <32>; interconnects = <&mmss_noc MASTER_VIDEO_EVA &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; diff --git a/qcom/msm-arm-smmu-tuna.dtsi b/qcom/msm-arm-smmu-tuna.dtsi index 8fcc06c3..db01ac18 100644 --- a/qcom/msm-arm-smmu-tuna.dtsi +++ b/qcom/msm-arm-smmu-tuna.dtsi @@ -200,18 +200,18 @@ <0x0801 0x0000 0x00000001>, /* NSP:Compute */ - <0x0c01 0x0040 0x00000303>, - <0x0c02 0x0020 0x00000303>, - <0x0c03 0x0040 0x00000303>, - <0x0c04 0x0040 0x00000303>, - <0x0c05 0x0040 0x00000303>, - <0x0c06 0x0020 0x00000303>, - <0x0c07 0x0040 0x00000303>, - <0x0c08 0x0020 0x00000303>, - <0x0c09 0x0040 0x00000303>, - <0x0c0c 0x0040 0x00000303>, - <0x0c0d 0x0020 0x00000303>, - <0x0c0e 0x0040 0x00000303>, + <0x0c01 0x0000 0x00000303>, + <0x0c02 0x0000 0x00000303>, + <0x0c03 0x0000 0x00000303>, + <0x0c04 0x0000 0x00000303>, + <0x0c05 0x0000 0x00000303>, + <0x0c06 0x0000 0x00000303>, + <0x0c07 0x0000 0x00000303>, + <0x0c08 0x0000 0x00000303>, + <0x0c09 0x0000 0x00000303>, + <0x0c0c 0x0000 0x00000303>, + <0x0c0d 0x0000 0x00000303>, + <0x0c0e 0x0000 0x00000303>, /* SF:Camera */ <0x1800 0x00c0 0x00000001>, diff --git a/qcom/parrot-coresight.dtsi b/qcom/parrot-coresight.dtsi index c9ced5f5..add9f724 100644 --- a/qcom/parrot-coresight.dtsi +++ b/qcom/parrot-coresight.dtsi @@ -570,7 +570,7 @@ coresight-name = "coresight-snoc"; qcom,dummy-source; - atid = <125>; + atid = <108>; out-ports { port { snoc_out_funnel_in0: endpoint { diff --git a/qcom/parrot-debug.dtsi b/qcom/parrot-debug.dtsi index 083def43..466febb0 100644 --- a/qcom/parrot-debug.dtsi +++ b/qcom/parrot-debug.dtsi @@ -11,9 +11,7 @@ ranges; dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; alignment = <0x0 0x400000>; size = <0x0 0xc00000>; }; @@ -1447,299 +1445,313 @@ compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; - c0_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x0>; + static_mem_dump { + qcom,static-mem-dump; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; }; - c100_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x1>; - }; + dynamic_mem_dump { + qcom,dynamic-mem-dump; - c200_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x2>; - }; + cpuss_reg { + cpuss_reg { + qcom,dump-size = <0x30000>; + qcom,dump-id = <0xef>; + }; + }; - c300_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x3>; - }; + l1 { + l1_icache0 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x60>; + }; - c400_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x4>; - }; + l1_icache100 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x61>; + }; - c500_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x5>; - }; + l1_icache200 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x62>; + }; - c600_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x6>; - }; + l1_icache300 { + qcom,dump-size = <0x10900>; + qcom,dump-id = <0x63>; + }; - c700_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x7>; - }; + l1_icache400 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x64>; + }; - cpuss_reg { - qcom,dump-size = <0x30000>; - qcom,dump-id = <0xef>; - }; + l1_icache500 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x65>; + }; - l1_icache0 { - qcom,dump-size = <0x10900>; - qcom,dump-id = <0x60>; - }; + l1_icache600 { + qcom,dump-size = <0x15100>; + qcom,dump-id = <0x66>; + }; - l1_icache100 { - qcom,dump-size = <0x10900>; - qcom,dump-id = <0x61>; - }; + l1_icache700 { + qcom,dump-size = <0x32100>; + qcom,dump-id = <0x67>; + }; - l1_icache200 { - qcom,dump-size = <0x10900>; - qcom,dump-id = <0x62>; - }; + l1_dcache0 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x80>; + }; - l1_icache300 { - qcom,dump-size = <0x10900>; - qcom,dump-id = <0x63>; - }; + l1_dcache100 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x81>; + }; - l1_icache400 { - qcom,dump-size = <0x15100>; - qcom,dump-id = <0x64>; - }; + l1_dcache200 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x82>; + }; - l1_icache500 { - qcom,dump-size = <0x15100>; - qcom,dump-id = <0x65>; - }; + l1_dcache300 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x83>; + }; - l1_icache600 { - qcom,dump-size = <0x15100>; - qcom,dump-id = <0x66>; - }; + l1_dcache400 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x84>; + }; - l1_icache700 { - qcom,dump-size = <0x32100>; - qcom,dump-id = <0x67>; - }; + l1_dcache500 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x85>; + }; - l1_dcache0 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x80>; - }; + l1_dcache600 { + qcom,dump-size = <0x9100>; + qcom,dump-id = <0x86>; + }; - l1_dcache100 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x81>; - }; + l1_dcache700 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x87>; + }; - l1_dcache200 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x82>; - }; + l1_itlb400 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x24>; + }; - l1_dcache300 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x83>; - }; + l1_itlb500 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x25>; + }; - l1_dcache400 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x84>; - }; + l1_itlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; - l1_dcache500 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x85>; - }; + l1_itlb700 { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x27>; + }; - l1_dcache600 { - qcom,dump-size = <0x9100>; - qcom,dump-id = <0x86>; - }; + l1_dtlb400 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x44>; + }; - l1_dcache700 { - qcom,dump-size = <0x12100>; - qcom,dump-id = <0x87>; - }; + l1_dtlb500 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x45>; + }; - l1_itlb400 { - qcom,dump-size = <0x300>; - qcom,dump-id = <0x24>; - }; + l1_dtlb600 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x46>; + }; - l1_itlb500 { - qcom,dump-size = <0x300>; - qcom,dump-id = <0x25>; - }; + l1_dtlb700 { + qcom,dump-size = <0x3a0>; + qcom,dump-id = <0x47>; + }; + }; - l1_itlb600 { - qcom,dump-size = <0x300>; - qcom,dump-id = <0x26>; - }; + l2 { + l2_cache400 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc4>; + }; - l1_itlb700 { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x27>; - }; + l2_cache500 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc5>; + }; - l1_dtlb400 { - qcom,dump-size = <0x300>; - qcom,dump-id = <0x44>; - }; + l2_cache600 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc6>; + }; - l1_dtlb500 { - qcom,dump-size = <0x300>; - qcom,dump-id = <0x45>; - }; + l2_cache700 { + qcom,dump-size = <0x120100>; + qcom,dump-id = <0xc7>; + }; - l1_dtlb600 { - qcom,dump-size = <0x300>; - qcom,dump-id = <0x46>; - }; + l2_tlb0 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x120>; + }; - l1_dtlb700 { - qcom,dump-size = <0x3a0>; - qcom,dump-id = <0x47>; - }; + l2_tlb100 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x121>; + }; - l2_cache400 { - qcom,dump-size = <0x90100>; - qcom,dump-id = <0xc4>; - }; + l2_tlb200 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x122>; + }; - l2_cache500 { - qcom,dump-size = <0x90100>; - qcom,dump-id = <0xc5>; - }; + l2_tlb300 { + qcom,dump-size = <0x5b00>; + qcom,dump-id = <0x123>; + }; - l2_cache600 { - qcom,dump-size = <0x90100>; - qcom,dump-id = <0xc6>; - }; + l2_tlb400 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x124>; + }; - l2_cache700 { - qcom,dump-size = <0x120100>; - qcom,dump-id = <0xc7>; - }; + l2_tlb500 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x125>; + }; - l2_tlb0 { - qcom,dump-size = <0x5b00>; - qcom,dump-id = <0x120>; - }; + l2_tlb600 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x126>; + }; - l2_tlb100 { - qcom,dump-size = <0x5b00>; - qcom,dump-id = <0x121>; - }; - - l2_tlb200 { - qcom,dump-size = <0x5b00>; - qcom,dump-id = <0x122>; - }; - - l2_tlb300 { - qcom,dump-size = <0x5b00>; - qcom,dump-id = <0x123>; - }; - - l2_tlb400 { - qcom,dump-size = <0x6100>; - qcom,dump-id = <0x124>; - }; - - l2_tlb500 { - qcom,dump-size = <0x6100>; - qcom,dump-id = <0x125>; - }; - - l2_tlb600 { - qcom,dump-size = <0x6100>; - qcom,dump-id = <0x126>; - }; - - l2_tlb700 { - qcom,dump-size = <0xc100>; - qcom,dump-id = <0x127>; - }; - - rpmh { - qcom,dump-size = <0x400000>; - qcom,dump-id = <0xec>; - }; - - rpm_sw { - qcom,dump-size = <0x28000>; - qcom,dump-id = <0xea>; - }; - - pmic { - qcom,dump-size = <0x200000>; - qcom,dump-id = <0xe4>; - }; - - fcm { - qcom,dump-size = <0x8400>; - qcom,dump-id = <0xee>; - }; - - etf_swao { - qcom,dump-size = <0x10000>; - qcom,dump-id = <0xf1>; - }; - - etr_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x100>; - }; - - etr1_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x105>; - }; - - etfswao_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x102>; - }; - - misc_data { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0xe8>; - }; - - etf_lpass { - qcom,dump-size = <0x4000>; - qcom,dump-id = <0xf4>; - }; - - etflpass_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x104>; - }; - - osm_reg { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x163>; - }; - - pcu_reg { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x164>; - }; - - fsm_data { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x165>; + l2_tlb700 { + qcom,dump-size = <0xc100>; + qcom,dump-id = <0x127>; + }; + }; }; }; }; diff --git a/qcom/parrot-pmic-overlay.dtsi b/qcom/parrot-pmic-overlay.dtsi index 736ff379..8c0a0e8b 100644 --- a/qcom/parrot-pmic-overlay.dtsi +++ b/qcom/parrot-pmic-overlay.dtsi @@ -406,6 +406,7 @@ #address-cells = <1>; #size-cells = <0>; status = "ok"; + qcom,old-i2c-freq-cfg; pm8010i@8 { compatible = "qcom,i2c-pmic"; diff --git a/qcom/parrot-qupv3.dtsi b/qcom/parrot-qupv3.dtsi index 8514544f..26683de2 100644 --- a/qcom/parrot-qupv3.dtsi +++ b/qcom/parrot-qupv3.dtsi @@ -82,7 +82,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se3_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>; @@ -101,7 +101,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; @@ -124,7 +124,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, @@ -148,7 +148,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; @@ -171,7 +171,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, @@ -195,7 +195,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; @@ -219,7 +219,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, @@ -243,7 +243,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; @@ -266,7 +266,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>, @@ -290,7 +290,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; @@ -313,7 +313,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A1NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>, @@ -384,7 +384,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; @@ -406,7 +406,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, @@ -430,7 +430,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>; @@ -453,7 +453,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>, @@ -477,7 +477,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>; @@ -500,7 +500,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>, @@ -524,7 +524,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>; @@ -547,7 +547,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>, @@ -572,7 +572,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se11_default_cts>, <&qupv3_se11_default_rts>, diff --git a/qcom/parrot-vm.dtsi b/qcom/parrot-vm.dtsi index a8f8d09a..82ea3d9d 100644 --- a/qcom/parrot-vm.dtsi +++ b/qcom/parrot-vm.dtsi @@ -4,6 +4,7 @@ */ #include "waipio-vm.dtsi" +#include / { qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, @@ -35,6 +36,13 @@ status = "disabled"; }; + gcc: clock-controller@100000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + vgic: interrupt-controller@17200000 { compatible = "arm,gic-v3"; interrupt-controller; @@ -74,7 +82,8 @@ /delete-node/ spi@990000; qup_iommu_group: qup_common_iommu_group { - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>, + <&qupv3_1 0x00000000 0x00020000>; }; gpi_dma1: qcom,gpi-dma@a00000 { @@ -84,6 +93,7 @@ reg-names = "gpi-top"; iommus = <&apps_smmu 0x418 0x0>; qcom,iommu-group = <&qup_iommu_group>; + memory-region = <&qup_iommu_group>; dma-coherent; interrupts = , , @@ -109,9 +119,16 @@ qupv3_1: qcom,qupv3_1_geni_se@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; iommus = <&apps_smmu 0x418 0x0>; qcom,iommu-group = <&qup_iommu_group>; + memory-region = <&qup_iommu_group>; dma-coherent; + ranges; status = "ok"; /* TUI over I2C */ diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 19f3ffec..13818ee9 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -10,6 +10,15 @@ _platform_map = { # keep sorted ], }, + "sdxkova.cpe.wkk": { + "dtb_list": [ + # keep sorted + {"name": "sdxkova-idp-cpe.dtb"}, + ], + "dtbo_list": [ + # keep sorted + ], + }, "sun": { "dtb_list": [ # keep sorted @@ -73,6 +82,14 @@ _platform_map = { "name": "tuna-rumi-overlay.dtbo", "apq": False, }, + {"name": "tuna-atp-overlay.dtbo"}, + {"name": "tuna-cdp-overlay.dtbo"}, + {"name": "tuna-mtp-kiwi-overlay.dtbo"}, + {"name": "tuna-mtp-overlay.dtbo"}, + {"name": "tuna-mtp-qmp1000-overlay.dtbo"}, + {"name": "tuna-qrd-overlay.dtbo"}, + {"name": "tuna-rcm-kiwi-overlay.dtbo"}, + {"name": "tuna-rcm-overlay.dtbo"}, ], }, "kera": { diff --git a/qcom/pmx75.dtsi b/qcom/pmx75.dtsi new file mode 100644 index 00000000..3838a32f --- /dev/null +++ b/qcom/pmx75.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmx75@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmx75_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmx75_vbus_detect: qcom,pmd-vbus-det@1500 { + compatible = "qcom,pm8941-misc"; + reg = <0x1500>; + interrupts = <0x1 0x15 0x0 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb_vbus"; + status = "disabled"; + }; + + pmx75_gpios: pinctrl@8800 { + compatible = "qcom,pmx75-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmx75_pwm: pwms@e800 { + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <4>; + }; + + pmx75_eusb2_repeater: qcom,eusb2-repeater@fd00 { + compatible = "qcom,pmic-eusb2-repeater"; + reg = <0xfd00>; + status = "disabled"; + }; + }; +}; + +&thermal_zones { + pmx75_temp_alarm: pmx75_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmx75_tz>; + + trips { + pmx75_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmx75_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + pmx75_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/ravelin-coresight.dtsi b/qcom/ravelin-coresight.dtsi index 586fac35..675502a7 100644 --- a/qcom/ravelin-coresight.dtsi +++ b/qcom/ravelin-coresight.dtsi @@ -553,7 +553,7 @@ coresight-name = "coresight-snoc"; qcom,dummy-source; - atid = <125>; + atid = <108>; out-ports { port { snoc_out_funnel_in0: endpoint { diff --git a/qcom/ravelin-idp.dtsi b/qcom/ravelin-idp.dtsi index 33924ecc..0c8d1e32 100644 --- a/qcom/ravelin-idp.dtsi +++ b/qcom/ravelin-idp.dtsi @@ -12,6 +12,7 @@ &qupv3_se8_i2c { awinic@64 { + compatible = "awinic,aw2016_led"; reg = <0x64>; awinic,red { diff --git a/qcom/ravelin-pmic-overlay.dtsi b/qcom/ravelin-pmic-overlay.dtsi index d94c9230..21b1b6e8 100644 --- a/qcom/ravelin-pmic-overlay.dtsi +++ b/qcom/ravelin-pmic-overlay.dtsi @@ -472,6 +472,7 @@ #address-cells = <1>; #size-cells = <0>; status = "ok"; + qcom,old-i2c-freq-cfg; pm8010m@8 { compatible = "qcom,i2c-pmic"; diff --git a/qcom/ravelin-qupv3.dtsi b/qcom/ravelin-qupv3.dtsi index cd4af450..e7e0092c 100644 --- a/qcom/ravelin-qupv3.dtsi +++ b/qcom/ravelin-qupv3.dtsi @@ -82,7 +82,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se2_default_cts>, <&qupv3_se2_default_rts>, @@ -106,7 +106,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; @@ -125,7 +125,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; @@ -146,7 +146,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; interrupts = ; clock-names = "se-clk"; @@ -170,7 +170,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; @@ -193,7 +193,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; interrupts = ; clock-names = "se-clk"; @@ -217,7 +217,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; @@ -241,7 +241,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; @@ -264,7 +264,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>, <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; @@ -334,7 +334,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; @@ -353,7 +353,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; @@ -376,7 +376,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; @@ -400,7 +400,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; @@ -423,7 +423,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; @@ -447,7 +447,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; @@ -471,7 +471,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; @@ -495,7 +495,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; @@ -518,7 +518,7 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, - <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; clock-names = "se-clk"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 5cfc434b..32b8915b 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -1765,8 +1765,8 @@ compatible = "qcom,sdhci-msm-v5"; reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, - <0x007C8000 0x8000>, <0x007D0000 0x9000>; - reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm"; + <0x007C8000 0x18000>; + reg-names = "hc", "cqhci", "ice"; iommus = <&apps_smmu 0x560 0x0>; qcom,iommu-dma = "fastmap"; @@ -1781,6 +1781,7 @@ nvmem-cells = <&boot_config>; nvmem-cell-names = "boot_conf"; + qcom,ice-use-hwkm; bus-width = <8>; non-removable; supports-cqe; @@ -2574,6 +2575,7 @@ &qupv3_se8_i2c { status = "ok"; fsa4480: fsa4480@42 { + compatible = "qcom,fsa4480-i2c"; reg = <0x42>; }; }; diff --git a/qcom/sdxkova-idp-cpe.dtsi b/qcom/sdxkova-idp-cpe.dtsi index 9df4770a..3d30e577 100644 --- a/qcom/sdxkova-idp-cpe.dtsi +++ b/qcom/sdxkova-idp-cpe.dtsi @@ -2,3 +2,52 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ + +#include "sdxkova-pmic-overlay.dtsi" + +&sdhc_1 { + status = "ok"; + + reg = <0x0 0x08804000 0x0 0x1000>, <0x0 0x08805000 0x0 0x1000>; + reg-names = "hc", "cqhci"; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + bus-width = <8>; + no-sd; + non-removable; + supports-cqe; + cap-mmc-hw-reset; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F442C 0x0 0x01 + 0x090106C0 0x80040868>; + + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_EMMC_BCR>; + reset-names = "core_reset"; + + vdd-supply = <&vreg_sdc1_emmc_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L6B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 200000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_emmc_on>; + pinctrl-1 = <&sdc1_emmc_off>; + + operating-points-v2 = <&sdhc1_opp_table>; +}; + +&pmx75_vbus_detect { + status = "ok"; +}; + diff --git a/qcom/sdxkova-idp-mbb.dtsi b/qcom/sdxkova-idp-mbb.dtsi index 9df4770a..15e414cb 100644 --- a/qcom/sdxkova-idp-mbb.dtsi +++ b/qcom/sdxkova-idp-mbb.dtsi @@ -2,3 +2,66 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ + +#include +#include "sdxkova-pmic-overlay.dtsi" +#include "pm7550ba.dtsi" + +&sdhc_1 { + status = "disabled"; + + no-mmc; + max-frequency = <192000000>; + + vdd-supply = <&vreg_sdc1_emmc_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_sdc1_sd_ls_vccb>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_sd_on>; + pinctrl-1 = <&sdc1_sd_off>; + + cd-gpios = <&tlmm 103 GPIO_ACTIVE_LOW>; + + operating-points-v2 = <&sdhc2_opp_table>; +}; + +&pmk8550_vadc { + /* PM8550BA Channel nodes */ + pm7550ba_offset_ref { + status = "ok"; + }; + + pm7550ba_vref_1p25 { + status = "ok"; + }; + + pm7550ba_die_temp { + status = "ok"; + }; + + pm7550ba_vph_pwr { + status = "ok"; + }; + + pm7550ba_chg_temp { + status = "ok"; + }; + + pm7550ba_iin_fb { + status = "ok"; + }; + + pm7550ba_ichg_fb { + status = "ok"; + }; +}; + +&pm7550ba_tz { + io-channels = <&pmk8550_vadc PM7550BA_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; +}; diff --git a/qcom/sdxkova-pmic-overlay.dtsi b/qcom/sdxkova-pmic-overlay.dtsi new file mode 100644 index 00000000..b4c705eb --- /dev/null +++ b/qcom/sdxkova-pmic-overlay.dtsi @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +#include "pmk8550.dtsi" +#include "pmx75.dtsi" + +/ { + vreg_sdc1_sd_ls_vccb: sdc1-sd-ls-gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "sdc1_sd_ls_vccb"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + enable-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; + states = <1800000 0>, + <2850000 1>; + startup-delay-us = <5000>; + enable-active-high; + }; + + vreg_sdc1_emmc_sd_vdd: sdc1-emmc-sd-fixed-regulator { + compatible = "qcom,stub-regulator"; + regulator-name = "sdc1_emmc_sd_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + parent-supply = <&vreg_sdc1_sd_ls_vccb>; + }; +}; + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmg1110@a { + compatible = "qcom,spmi-pmic"; + reg = <10 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmg1110_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; +}; + +&thermal_zones { + pmg1110_temp_alarm: pmg1110_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmg1110_tz>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; + +&pmk8550_vadc { + /delete-node/ pm8550_offset_ref; + /delete-node/ pm8550_vref_1p25; + /delete-node/ pm8550_die_temp; + /delete-node/ pm8550_vph_pwr; + + /* PM8550BA Channel nodes */ + pm7550ba_offset_ref { + reg = ; + label = "pm7550ba_offset_ref"; + qcom,pre-scaling = <1 1>; + status = "disabled"; + }; + + pm7550ba_vref_1p25 { + reg = ; + label = "pm7550ba_vref_1p25"; + qcom,pre-scaling = <1 1>; + status = "disabled"; + }; + + pm7550ba_die_temp { + reg = ; + label = "pm7550ba_die_temp"; + qcom,pre-scaling = <1 1>; + status = "disabled"; + }; + + pm7550ba_vph_pwr { + reg = ; + label = "pm7550ba_vph_pwr"; + qcom,pre-scaling = <1 3>; + status = "disabled"; + }; + + pm7550ba_chg_temp { + reg = ; + label = "pm7550ba_chg_temp"; + status = "disabled"; + }; + + pm7550ba_iin_fb { + reg = ; + label = "pm7550ba_iin_fb"; + status = "disabled"; + }; + + pm7550ba_ichg_fb { + reg = ; + label = "pm7550ba_ichg_fb"; + status = "disabled"; + }; + + /* PMX75 Channel nodes */ + pmx75_offset_ref { + reg = ; + label = "pmx75_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + pmx75_vref_1p25 { + reg = ; + label = "pmx75_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pmx75_die_temp { + reg = ; + label = "pmx75_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmx75_vph_pwr { + reg = ; + label = "pmx75_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + pmx75_pa_therm1 { + reg = ; + label = "pmx75_pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmx75_pa_therm2 { + reg = ; + label = "pmx75_pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmx75_sdx_case_therm { + reg = ; + label = "pmx75_sdx_case_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmx75_ambient_therm { + reg = ; + label = "pmx75_ambient_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmx75_qtm_therm { + reg = ; + label = "pmx75_qtm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmx75_sdr_skin_therm { + reg = ; + label = "pmx75_sdr_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; +}; + +&pmx75_tz { + io-channels = <&pmk8550_vadc PMX75_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&thermal_zones { + sys-therm-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM2_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM4_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM5_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMX75_ADC5_GEN3_AMUX_THM6_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pmg1110_temp_alarm: pmg1110_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmg1110_tz>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; + +&soc { + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pmk8550_sdam_5>, <&pmk8550_sdam_6>; + nvmem-names = "pon_log0", "pon_log1"; + }; + + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; +}; diff --git a/qcom/sdxkova-regulators.dtsi b/qcom/sdxkova-regulators.dtsi new file mode 100644 index 00000000..dddb3cf9 --- /dev/null +++ b/qcom/sdxkova-regulators.dtsi @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&apps_rsc_drv2 { + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + + VDD_MODEM_LEVEL: VDD_MSS_LEVEL: S1B_LEVEL: + pmx75_s1_level: regulator-pmx75-s1-level { + regulator-name = "pmx75_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-mxclvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mxc.lvl"; + proxy-supply = <&VDD_MXC_LEVEL>; + + VDD_MXC_LEVEL: S3B_LEVEL: + pmx75_s3_level: regulator-pmx75-s3-level { + regulator-name = "pmx75_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MXA_LEVEL>; + + VDD_MXA_LEVEL: VDD_MX_LEVEL: L17B_LEVEL: + pmx75_l17_level: regulator-pmx75-l17-level { + regulator-name = "pmx75_l17_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MXA_LEVEL_AO: VDD_MX_LEVEL_AO: L17B_LEVEL_AO: + pmx75_l17_level_ao: regulator-pmx75-l17-level-ao { + regulator-name = "pmx75_l17_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + + VDD_CX_LEVEL: S5B_LEVEL: + pmx75_s5_level: regulator-pmx75-s5-level { + regulator-name = "pmx75_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_CX_LEVEL_AO: S5B_LEVEL_AO: + pmx75_s5_level_ao: regulator-pmx75-s5-level-ao { + regulator-name = "pmx75_s5_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpb2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb2"; + + S2B: pmx75_s2: regulator-pmx75-s2 { + regulator-name = "pmx75_s2"; + qcom,set = ; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + qcom,init-voltage = <1224000>; + }; + }; + + rpmh-regulator-smpb4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb4"; + + S4B: pmx75_s4: regulator-pmx75-s4 { + regulator-name = "pmx75_s4"; + qcom,set = ; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1824000>; + }; + }; + + rpmh-regulator-smpb7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb7"; + + S7B: pmx75_s7: regulator-pmx75-s7 { + regulator-name = "pmx75_s7"; + qcom,set = ; + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <1060000>; + qcom,init-voltage = <936000>; + }; + }; + + rpmh-regulator-smpb8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb8"; + + S8B: pmx75_s8: regulator-pmx75-s8 { + regulator-name = "pmx75_s8"; + qcom,set = ; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + qcom,init-voltage = <824000>; + }; + }; + + rpmh-regulator-smpb9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb9"; + + S9B: pmx75_s9: regulator-pmx75-s9 { + regulator-name = "pmx75_s9"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1040000>; + qcom,init-voltage = <800000>; + }; + }; + + rpmh-regulator-ldob1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1B: pmx75_l1: regulator-pmx75-l1 { + regulator-name = "pmx75_l1"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2B: pmx75_l2: regulator-pmx75-l2 { + regulator-name = "pmx75_l2"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1160000>; + qcom,init-voltage = <1128000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L3B: pmx75_l3: regulator-pmx75-l3 { + regulator-name = "pmx75_l3"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1040000>; + qcom,init-voltage = <896000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L4B: pmx75_l4: regulator-pmx75-l4 { + regulator-name = "pmx75_l4"; + qcom,set = ; + regulator-min-microvolt = <864000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L5B: pmx75_l5: regulator-pmx75-l5 { + regulator-name = "pmx75_l5"; + qcom,set = ; + regulator-min-microvolt = <1770000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1776000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L6B: pmx75_l6: regulator-pmx75-l6 { + regulator-name = "pmx75_l6"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L7B: pmx75_l7: regulator-pmx75-l7 { + regulator-name = "pmx75_l7"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + qcom,init-voltage = <904000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L8B: pmx75_l8: regulator-pmx75-l8 { + regulator-name = "pmx75_l8"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L9B: pmx75_l9: regulator-pmx75-l9 { + regulator-name = "pmx75_l9"; + qcom,set = ; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <752000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L10B: pmx75_l10: regulator-pmx75-l10 { + regulator-name = "pmx75_l10"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3088000>; + qcom,init-voltage = <3080000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L11B: pmx75_l11: regulator-pmx75-l11 { + regulator-name = "pmx75_l11"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L12B: pmx75_l12: regulator-pmx75-l12 { + regulator-name = "pmx75_l12"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L13B: pmx75_l13: regulator-pmx75-l13 { + regulator-name = "pmx75_l13"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L14B: pmx75_l14: regulator-pmx75-l14 { + regulator-name = "pmx75_l14"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <624000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L15B: pmx75_l15: regulator-pmx75-l15 { + regulator-name = "pmx75_l15"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L16B: pmx75_l16: regulator-pmx75-l16 { + regulator-name = "pmx75_l16"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob19 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob19"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L19B: pmx75_l19: regulator-pmx75-l19 { + regulator-name = "pmx75_l19"; + qcom,set = ; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <960000>; + qcom,init-voltage = <952000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob20 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob20"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L20B: pmx75_l20: regulator-pmx75-l20 { + regulator-name = "pmx75_l20"; + qcom,set = ; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <952000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob21 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob21"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L21B: pmx75_l21: regulator-pmx75-l21 { + regulator-name = "pmx75_l21"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <856000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpk1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpk1"; + + S1K: pmg1110_s1: regulator-pmg1110-s1 { + regulator-name = "pmg1110_s1"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <916000>; + }; + }; +}; diff --git a/qcom/sdxkova-reserved-memory.dtsi b/qcom/sdxkova-reserved-memory.dtsi index 0a6f7f3f..aa76ab43 100644 --- a/qcom/sdxkova-reserved-memory.dtsi +++ b/qcom/sdxkova-reserved-memory.dtsi @@ -64,6 +64,8 @@ }; smem_mem: smem_region@87e20000 { + compatible = "qcom,smem"; + hwlocks = <&tcsr_mutex 3>; no-map; reg = <0x0 0x87e20000 0x0 0xc0000>; }; diff --git a/qcom/sdxkova-usb.dtsi b/qcom/sdxkova-usb.dtsi new file mode 100644 index 00000000..a48f3171 --- /dev/null +++ b/qcom/sdxkova-usb.dtsi @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + usb: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0 0xa600000 0x0 0x100000>; + reg-names = "core_base"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>, + <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&gcc_usb30_gdsc>; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_USB30_SLV_AHB_CLK>, + <&gcc GCC_USB30_MSTR_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", + "bus_aggr_clk", "utmi_clk", + "sleep_clk"; + + resets = <&gcc GCC_USB30_BCR>; + reset-names = "core_reset"; + + qcom,sleep-clk-bcr; + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,core-clk-rate-disconnected = <133333333>; + + dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0xa600000 0x0 0xd93c>; + + iommus = <&apps_smmu 0x80 0x0>; + qcom,iommu-dma = "atomic"; + memory-region = <&dwc3_mem_region>; + dma-coherent; + + interrupts = ; + usb-phy = <&usb_nop_phy>, <&usb_qmp_phy>; + snps,has-lpm-erratum; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,hird-threshold = /bits/ 8 <0x10>; + tx-fifo-resize; + /* set host mode interrupt moderation to 1 us */ + imod-interval-ns = <1000>; + maximum-speed = "super-speed-plus"; + usb-role-switch; + dr_mode = "peripheral"; + }; + + }; + + dwc3_mem_region: dwc3_mem_region { + iommu-addresses = <&dwc3 0x0 0x0 0x0 0x90000000>, + <&dwc3 0x0 0xf0000000 0xffffffff 0x10000000>; + }; + + /* USB port related QMP USB UNI PHY */ + usb_qmp_phy: ssphy@ff6000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x0 0xff6000 0x0 0x2000>, + <0x0 0xff7400 0x0 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&L4B>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L1B>; + qcom,core-max-load-uA = <15000>; + + usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk", "ref_clk_src", + "cfg_ahb_clk"; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; +}; diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index 2d686d77..48818679 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -3,18 +3,31 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include #include "sdx75.dtsi" /delete-node/ &apps_smmu; +/delete-node/ &tcsr_mutex; #include "msm-arm-smmu-sdxkova.dtsi" /{ qcom_tzlog: tz-log@14680720 { compatible = "qcom,tz-log"; - reg = <0x14680720 0x3000>; + reg = <0x0 0x14680720 0x0 0x3000>; qcom,hyplog-enabled; hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; }; + /delete-node/ timer; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + /delete-node/ reserved-memory; reserved_memory: reserved-memory { @@ -59,84 +72,1977 @@ ; }; - }; - }; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sdx75-rpmh-clk"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sdx75-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp-16 { - opp-level = ; + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; }; - rpmhpd_opp_min_svs: opp-48 { - opp-level = ; + rpmhcc: clock-controller { + compatible = "qcom,sdx75-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; }; - rpmhpd_opp_low_svs: opp-64 { - opp-level = ; - }; + rpmhpd: power-controller { + compatible = "qcom,sdx75-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; - rpmhpd_opp_svs: opp-128 { - opp-level = ; - }; + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; - rpmhpd_opp_svs_l1: opp-192 { - opp-level = ; - }; + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; - rpmhpd_opp_nom: opp-256 { - opp-level = ; - }; + rpmhpd_opp_min_svs: opp-48 { + opp-level = ; + }; - rpmhpd_opp_nom_l1: opp-320 { - opp-level = ; - }; + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; - rpmhpd_opp_nom_l2: opp-336 { - opp-level = ; - }; + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; - rpmhpd_opp_turbo: opp-384 { - opp-level = ; - }; + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; - rpmhpd_opp_turbo_l1: opp-416 { - opp-level = ; + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + }; }; }; }; }; + firmware: firmware { }; + aliases: aliases { serial0 = &uart1; + mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ + hsuart0 = &qupv3_se3_4uart; + hsuart1 = &qupv3_se4_2uart; + hsuart2 = &qupv3_se8_2uart; + i2c0 = &qupv3_se0_i2c; + i2c2 = &qupv3_se2_i2c; + i2c5 = &qupv3_se5_i2c; + i2c6 = &qupv3_se6_i2c; + i2c7 = &qupv3_se7_i2c; + spi0 = &qupv3_se0_spi; + spi2 = &qupv3_se2_spi; + spi6 = &qupv3_se6_spi; + spi7 = &qupv3_se7_spi; }; }; -&tlmm { - gpio-reserved-ranges = <110 6>; +&clk_virt { + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; }; +&mc_virt { + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; +}; + +&system_noc { + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + clocks = <&gcc GCC_SYS_NOC_MVMSS_CLK>; +}; + +&pcie_anoc { + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; +}; + +&dc_noc { + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; +}; + +&gem_noc { + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; +}; + +&tlmm { + /delete-property/ wakeup-parent; + /* TO DO: re-enable PDC dependency once we validate PDC changes */ + gpio-reserved-ranges = <110 6>; + sdc1_emmc_on: sdc1_emmc_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_emmc_off: sdc1_emmc_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sd_on: sdc1_sd_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio103"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc1_sd_off: sdc1_sd_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio103"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { + qupv3_se3_default_cts: qupv3_se3_default_cts { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_default_rts: qupv3_se3_default_rts { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_default_tx: qupv3_se3_default_tx { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_default_rx: qupv3_se3_default_rx { + mux { + pins = "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_cts: qupv3_se3_cts { + mux { + pins = "gpio52"; + function = "qup_se3"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_rts: qupv3_se3_rts { + mux { + pins = "gpio53"; + function = "qup_se3"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_tx: qupv3_se3_tx { + mux { + pins = "gpio54"; + function = "qup_se3"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_rx: qupv3_se3_rx { + mux { + pins = "gpio55"; + function = "qup_se3"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup_se0"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup_se0"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup_se0"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup_se0"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { + mux { + pins = "gpio10"; + function = "qup_se0"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { + mux { + pins = "gpio11"; + function = "qup_se0"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { + mux { + pins = "gpio14"; + function = "qup_se2"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { + mux { + pins = "gpio15"; + function = "qup_se2"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { + mux { + pins = "gpio14"; + function = "qup_se2"; + }; + + config { + pins = "gpio14"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { + mux { + pins = "gpio15"; + function = "qup_se2"; + }; + + config { + pins = "gpio15"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { + mux { + pins = "gpio16"; + function = "qup_se2"; + }; + + config { + pins = "gpio16"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { + mux { + pins = "gpio17"; + function = "qup_se2"; + }; + + config { + pins = "gpio17"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { + mux { + pins = "gpio52"; + function = "qup_se3"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio53"; + function = "qup_se3"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { + mux { + pins = "gpio52"; + function = "qup_se3"; + }; + + config { + pins = "gpio52"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { + mux { + pins = "gpio53"; + function = "qup_se3"; + }; + + config { + pins = "gpio53"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { + mux { + pins = "gpio54"; + function = "qup_se3"; + }; + + config { + pins = "gpio54"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { + mux { + pins = "gpio55"; + function = "qup_se3"; + }; + + config { + pins = "gpio55"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_tx_active: qupv3_se4_2uart_tx_active { + mux { + pins = "gpio64"; + function = "qup_se4"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_rx_active: qupv3_se4_2uart_rx_active { + mux { + pins = "gpio65"; + function = "qup_se4"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio64", "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { + mux { + pins = "gpio110"; + function = "qup_se5"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio111"; + function = "qup_se5"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio110", "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio110", "gpio111"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio112"; + function = "qup_se6"; + }; + + config { + pins = "gpio112"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio113"; + function = "qup_se6"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio112", "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio112", "gpio113"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio112"; + function = "qup_se6"; + }; + + config { + pins = "gpio112"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio113"; + function = "qup_se6"; + }; + + config { + pins = "gpio113"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio114"; + function = "qup_se6"; + }; + + config { + pins = "gpio114"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio115"; + function = "qup_se6"; + }; + + config { + pins = "gpio115"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio112", "gpio113", + "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio112", "gpio113", + "gpio114", "gpio115"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_sda_active: qupv3_se7_i2c_sda_active { + mux { + pins = "gpio116"; + function = "qup_se7"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_scl_active: qupv3_se7_i2c_scl_active { + mux { + pins = "gpio117"; + function = "qup_se7"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio116", "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio116", "gpio117"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_miso_active: qupv3_se7_spi_miso_active { + mux { + pins = "gpio116"; + function = "qup_se7"; + }; + + config { + pins = "gpio116"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_mosi_active: qupv3_se7_spi_mosi_active { + mux { + pins = "gpio117"; + function = "qup_se7"; + }; + + config { + pins = "gpio117"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_clk_active: qupv3_se7_spi_clk_active { + mux { + pins = "gpio118"; + function = "qup_se7"; + }; + + config { + pins = "gpio118"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_cs_active: qupv3_se7_spi_cs_active { + mux { + pins = "gpio119"; + function = "qup_se7"; + }; + + config { + pins = "gpio119"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio116", "gpio117", + "gpio118", "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio116", "gpio117", + "gpio118", "gpio119"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se8_2uart_pins: qupv3_se8_2uart_pins { + qupv3_se8_2uart_tx_active: qupv3_se8_2uart_tx_active { + mux { + pins = "gpio124"; + function = "qup_se8"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_rx_active: qupv3_se8_2uart_rx_active { + mux { + pins = "gpio125"; + function = "qup_se8"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_sleep: qupv3_se8_2uart_sleep { + mux { + pins = "gpio124", "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio124", "gpio125"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; +}; + +&scm { + qcom,dload-mode = <&tcsr 0x13000>; +}; + +&firmware { + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; +}; + +#include "sdxkova-regulators.dtsi" + +&chosen { + bootargs = "cpufreq.default_governor=performance"; +}; + +&soc { + + clocks { + emac0_sgmiiphy_mac_rclk: emac0_sgmiiphy_mac_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_mac_rclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_mac_tclk: emac0_sgmiiphy_mac_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_mac_tclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_rclk: emac0_sgmiiphy_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_rclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_tclk: emac0_sgmiiphy_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_tclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_mac_rclk: emac1_sgmiiphy_mac_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_mac_rclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_mac_tclk: emac1_sgmiiphy_mac_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_mac_tclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_rclk: emac1_sgmiiphy_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_rclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_tclk: emac1_sgmiiphy_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_tclk"; + #clock-cells = <0>; + }; + + pcie20_phy_aux_clk: pcie20_phy_aux_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie20_phy_aux_clk"; + #clock-cells = <0>; + }; + + pcie_1_pipe_clk: pcie_1_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_2_pipe_clk: pcie_2_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_2_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_pipe_clk: pcie_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_pipe_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + }; + + /* GCC GDSCs */ + gcc_emac0_gdsc: qcom,gdsc@f1004 { + compatible = "qcom,gdsc"; + reg = <0x0 0xf1004 0x0 0x4>; + regulator-name = "gcc_emac0_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + qcom,support-hw-trigger; + }; + + gcc_emac1_gdsc: qcom,gdsc@f2004 { + compatible = "qcom,gdsc"; + reg = <0x0 0xf2004 0x0 0x4>; + regulator-name = "gcc_emac1_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + qcom,support-hw-trigger; + }; + + gcc_pcie_1_gdsc: qcom,gdsc@e7004 { + compatible = "qcom,gdsc"; + reg = <0x0 0xe7004 0x0 0x4>; + regulator-name = "gcc_pcie_1_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + qcom,support-hw-trigger; + }; + + gcc_pcie_1_phy_gdsc: qcom,gdsc@d6004 { + compatible = "qcom,gdsc"; + reg = <0x0 0xd6004 0x0 0x4>; + regulator-name = "gcc_pcie_1_phy_gdsc"; + parent-supply = <&VDD_MXA_LEVEL>; + qcom,retain-regs; + qcom,support-hw-trigger; + }; + + gcc_pcie_2_gdsc: qcom,gdsc@e8004 { + compatible = "qcom,gdsc"; + reg = <0x0 0xe8004 0x0 0x4>; + regulator-name = "gcc_pcie_2_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + qcom,support-hw-trigger; + }; + + gcc_pcie_2_phy_gdsc: qcom,gdsc@ee004 { + compatible = "qcom,gdsc"; + reg = <0x0 0xee004 0x0 0x4>; + regulator-name = "gcc_pcie_2_phy_gdsc"; + parent-supply = <&VDD_MXA_LEVEL>; + qcom,retain-regs; + qcom,support-hw-trigger; + }; + + gcc_pcie_gdsc: qcom,gdsc@d3004 { + compatible = "qcom,gdsc"; + reg = <0x0 0xd3004 0x0 0x4>; + regulator-name = "gcc_pcie_gdsc"; + parent-supply = <&VDD_MXA_LEVEL>; + qcom,retain-regs; + qcom,support-hw-trigger; + }; + + gcc_pcie_phy_gdsc: qcom,gdsc@d4004 { + compatible = "qcom,gdsc"; + reg = <0x0 0xd4004 0x0 0x4>; + regulator-name = "gcc_pcie_phy_gdsc"; + parent-supply = <&VDD_MXA_LEVEL>; + qcom,retain-regs; + qcom,support-hw-trigger; + }; + + gcc_usb30_gdsc: qcom,gdsc@a7004 { + compatible = "qcom,gdsc"; + reg = <0x0 0xa7004 0x0 0x4>; + regulator-name = "gcc_usb30_gdsc"; + parent-supply = <&VDD_MXA_LEVEL>; + qcom,retain-regs; + }; + + gcc_usb3_phy_gdsc: qcom,gdsc@a8008 { + compatible = "qcom,gdsc"; + reg = <0x0 0xa8008 0x0 0x4>; + regulator-name = "gcc_usb3_phy_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + }; + + apsscc: syscon@17aa0000 { + compatible = "syscon"; + reg = <0x0 0x17aa0000 0x0 0x1c>; + }; + + mccc: syscon@190ba000 { + compatible = "syscon"; + reg = <0x0 0x190ba000 0x0 0x54>; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,sdx75-debugcc"; + qcom,apsscc = <&apsscc>; + qcom,gcc = <&gcc>; + qcom,mccc = <&mccc>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc 0>; + clock-names = "xo_clk_src", + "gcc"; + #clock-cells = <1>; + }; + + qcom,cpufreq-hw-debug { + compatible = "qcom,cpufreq-hw-epss-debug"; + qcom,freq-hw-domain = <&cpufreq_hw 0>; + }; + + ipcc_mproc: qcom,ipcc@408000 { + compatible = "qcom,ipcc"; + reg = <0x0 0x408000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + llcc_device: cache-controller@19200000 { + compatible = "qcom,sdxpinn-llcc"; + reg = <0x0 0x19200000 0x0 0x200000>; + reg-names = "llcc0_base"; + interrupts = ; + cap-based-alloc-and-pwr-collapse; + }; + + qcom,msm-imem@14680000 { + compatible = "qcom,msm-imem"; + reg = <0x0 0x14680000 0x0 0x1000>; + ranges = <0x0 0x0 0x14680000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x0 0x10 0x0 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x0 0x65c 0x0 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x0 0x1c 0x0 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x0 0x6b0 0x0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x0 0x6d0 0x0 0xc>; + }; + + pil@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x0 0x94c 0x0 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x0 0x6dc 0x0 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0x0 0xc8 0x0 0xc8>; + }; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x0 0x1f40000 0x0 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x0 0x1fc0000 0x0 0x30000>; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,aoss-qmp"; + reg = <0x0 0xc310000 0x0 0x1000>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + qmp_aop: qcom,qmp-aop { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + qmp_tme: qcom,qmp-tme { + compatible = "qcom,qmp-mbox"; + qcom,remote-pid = <14>; + mboxes = <&ipcc_mproc IPCC_CLIENT_TME + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "tme_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "tme"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <1600000 56000>; + opp-avg-kBps = <104000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <7000000 360000>; + opp-avg-kBps = <400000 0>; + }; + }; + + sdhc_1: sdhci@8804000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + no-sdio; + qcom,restore-after-cx-collapse; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface", "core"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007442C 0x0 0x10 + 0x090106C0 0x80040868>; + + iommus = <&apps_smmu 0x00A0 0x0>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + qcom,iommu-dma-addr-pool = <0x0 0x20000000 0x0 0x10000000>; + qcom,iommu-geometry = <0x0 0x20000000 0x0 0x10000000>; + + interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc1_opp_table>; + + qos0 { + mask = <0x0f>; + vote = <44>; + }; + }; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <1600000 56000>; + opp-avg-kBps = <50000 0>; + }; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-peak-kBps = <7000000 360000>; + opp-avg-kBps = <104000 0>; + }; + }; + + qup1_gpi_iommu_region: qup1_gpi_iommu_region { + iommu-addresses = <&gpi_dma0 0x0 0x100000>, <&gpi_dma0 0x200000 0xffe00000>; + }; + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x0 0x900000 0x0 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xf6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x7f>; + qcom,ev-factor = <2>; + memory-region = <&qup1_gpi_iommu_region>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + + qup1_se_iommu_region: qup1_se_iommu_region { + iommu-addresses = <&qupv3_id_0 0x0 0x40000000>, + <&qupv3_id_0 0x50000000 0xb0000000>; + }; + + /delete-node/ spmi@c400000; + spmi_bus: qcom,spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0xc42d000 0x0 0x4000>, + <0x0 0xc400000 0x0 0x2800>, + <0x0 0xc500000 0x0 0x200000>, + <0x0 0xc440000 0x0 0x3c000>, + <0x0 0xc4c0000 0x0 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts = ; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <0>; + }; + + spmi_debug_bus: qcom,spmi-debug@24b14000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x0 0x24b14000 0x0 0x60>, <0x0 0x221c8784 0x0 0x4>; + reg-names = "core", "fuse"; + clock-names = "core_clk"; + qcom,fuse-enable-bit = <18>; + #address-cells = <2>; + #size-cells = <0>; + depends-on-supply = <&spmi_bus>; + + qcom,pmk8550-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmx75-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm7550ba-debug@7 { + compatible = "qcom,spmi-pmic"; + reg = <7 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + + thermal_zones: thermal-zones { + }; + + pmic_glink: qcom,pmic_glink { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; + qcom,subsys-name = "mpss"; + status = "disabled"; + + ucsi: qcom,ucsi { + compatible = "qcom,ucsi-glink"; + }; + + qcom,battery_charger { + compatible = "qcom,battery-charger"; + qcom,wireless-charging-not-supported; + qcom,thermal-mitigation-step = <500000>; + }; + }; + + pmic_glink_log: qcom,pmic_glink_log { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + status = "disabled"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + pmic_glink_debug: qcom,pmic_glink_debug { + compatible = "qcom,pmic-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi_bus>; + + spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm7550ba-debug@7 { + compatible = "qcom,spmi-pmic"; + reg = <7 SPMI_USID>; + qcom,can-sleep; + }; + }; + }; + }; +}; + +&gcc { + compatible = "qcom,sdx75-gcc", "syscon"; + reg = <0x0 0x0080000 0x0 0x1f7400>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&emac0_sgmiiphy_mac_rclk>, + <&emac0_sgmiiphy_mac_tclk>, + <&emac0_sgmiiphy_rclk>, + <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_mac_rclk>, + <&emac1_sgmiiphy_mac_tclk>, + <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, + <&pcie20_phy_aux_clk>, + <&pcie_1_pipe_clk>, + <&pcie_2_pipe_clk>, + <&pcie_pipe_clk>, + <&sleep_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", + "emac0_sgmiiphy_mac_rclk", + "emac0_sgmiiphy_mac_tclk", + "emac0_sgmiiphy_rclk", + "emac0_sgmiiphy_tclk", + "emac1_sgmiiphy_mac_rclk", + "emac1_sgmiiphy_mac_tclk", + "emac1_sgmiiphy_rclk", + "emac1_sgmiiphy_tclk", + "pcie20_phy_aux_clk", + "pcie_1_pipe_clk", + "pcie_2_pipe_clk", + "pcie_pipe_clk", + "sleep_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + protected-clocks = , + ; + #clock-cells = <1>; + #reset-cells = <1>; +}; + +/* QUPv3_0 wrapper instance */ &qupv3_id_0 { + /delete-property/ interconnects; + /delete-property/ interconnect-names; + memory-region = <&qup1_se_iommu_region>; + qcom,iommu-geometry = <0x0 0x40000000 0x0 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; status = "ok"; + + /* HS UART Instance */ + qupv3_se3_4uart: qcom,qup_uart@98c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x0 0x98c000 0x0 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 55 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, + <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; + pinctrl-1 = <&qupv3_se3_cts>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>, <&qupv3_se3_rx>; + pinctrl-2 = <&qupv3_se3_cts>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>, <&qupv3_se3_default_rx>; + pinctrl-3 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, + <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se0_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, + <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,shared; + status = "disabled"; + }; + + qupv3_se2_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, + <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>, + <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* CV2X UART1 Instance */ + qupv3_se4_2uart: qcom,qup_uart@990000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x0 0x990000 0x0 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_tx_active>, <&qupv3_se4_2uart_rx_active>; + pinctrl-1 = <&qupv3_se4_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@994000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@998000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x998000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@998000 { + compatible = "qcom,spi-geni"; + reg = <0x0 0x998000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@99c000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0x99c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + dmas = <&gpi_dma0 0 7 3 64 0>, + <&gpi_dma0 1 7 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi: spi@99c000 { + compatible = "qcom,spi-geni"; + reg = <0x0 0x99c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>, + <&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + dmas = <&gpi_dma0 0 7 1 64 0>, + <&gpi_dma0 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* CV2X UART2 Instance */ + qupv3_se8_2uart: qcom,qup_uart@9a0000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x0 0x9a0000 0x0 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_2uart_tx_active>, <&qupv3_se8_2uart_rx_active>; + pinctrl-1 = <&qupv3_se8_2uart_sleep>; + status = "disabled"; + }; }; &uart1 { + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>; status = "ok"; }; + +#include "sdxkova-usb.dtsi" +#include "ipcc-test-sdxkova.dtsi" diff --git a/qcom/sun-oemvm.dtsi b/qcom/sun-oemvm.dtsi index 7bee5578..eb6bd809 100644 --- a/qcom/sun-oemvm.dtsi +++ b/qcom/sun-oemvm.dtsi @@ -76,7 +76,7 @@ vm-guid = "847bfe26-0b12-5728-812a-06103f6bdec0"; qcom,sensitive; - vm-attrs = "crash-fatal", "context-dump", "crash-restart"; + vm-attrs = "context-dump", "crash-restart"; memory { #address-cells = <0x2>; diff --git a/qcom/sun-v2.dtsi b/qcom/sun-v2.dtsi index ee577831..cd92a1a2 100644 --- a/qcom/sun-v2.dtsi +++ b/qcom/sun-v2.dtsi @@ -18,6 +18,10 @@ compatible = "qcom,sun-cambistmclkcc-v2", "syscon"; }; +&evacc { + compatible = "qcom,sun-evacc-v2", "syscon"; +}; + &tsens1 { #qcom,sensors = <7>; }; diff --git a/qcom/sun-vm-dma-heaps.dtsi b/qcom/sun-vm-dma-heaps.dtsi index 5fda6434..b5cc90c3 100644 --- a/qcom/sun-vm-dma-heaps.dtsi +++ b/qcom/sun-vm-dma-heaps.dtsi @@ -39,6 +39,30 @@ qcom,dynamic-heap; }; + qcom,ms4 { + qcom,dma-heap-name = "qcom,ms4"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms5 { + qcom,dma-heap-name = "qcom,ms5"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms6 { + qcom,dma-heap-name = "qcom,ms6"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms7 { + qcom,dma-heap-name = "qcom,ms7"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + qcom,tui_test { qcom,dma-heap-name = "qcom,tui_test"; qcom,dma-heap-type = ; diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index 494c5e9c..22088983 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -102,7 +102,7 @@ vm-guid = "598085da-c516-5b25-a9c1-927a02819770"; qcom,sensitive; - vm-attrs = "crash-fatal", "context-dump", "crash-restart"; + vm-attrs = "context-dump", "crash-restart"; iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0 0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0 diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index a3d28847..045ed6b9 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2566,7 +2566,7 @@ * device tree, but it is calculated in the driver. */ qcom,dll-hsr-list = <0x0007442C 0x0 0x10 - 0x090106C0 0x80040868>; + 0x294106C0 0x80040868>; iommus = <&apps_smmu 0x540 0x0>; qcom,iommu-dma = "fastmap"; diff --git a/qcom/tuna-atp-overlay.dts b/qcom/tuna-atp-overlay.dts new file mode 100644 index 00000000..f11e1579 --- /dev/null +++ b/qcom/tuna-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna ATP"; + compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", + "qcom,atp"; + + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/qcom/tuna-atp.dtsi b/qcom/tuna-atp.dtsi new file mode 100644 index 00000000..386415d7 --- /dev/null +++ b/qcom/tuna-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-mtp.dtsi" diff --git a/qcom/tuna-cdp-overlay.dts b/qcom/tuna-cdp-overlay.dts new file mode 100644 index 00000000..82f00661 --- /dev/null +++ b/qcom/tuna-cdp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna CDP"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", + "qcom,cdp"; + + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <1 0>; +}; diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi new file mode 100644 index 00000000..9df4770a --- /dev/null +++ b/qcom/tuna-cdp.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ diff --git a/qcom/tuna-dma-heaps.dtsi b/qcom/tuna-dma-heaps.dtsi index ac87057a..9e9b9381 100644 --- a/qcom/tuna-dma-heaps.dtsi +++ b/qcom/tuna-dma-heaps.dtsi @@ -15,5 +15,17 @@ qcom,dma-heap-type = ; memory-region = <&cdsp_secure_heap_cma>; }; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; }; }; diff --git a/qcom/tuna-mtp-kiwi-overlay.dts b/qcom/tuna-mtp-kiwi-overlay.dts new file mode 100644 index 00000000..9f8e2b72 --- /dev/null +++ b/qcom/tuna-mtp-kiwi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-mtp-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 2>; +}; diff --git a/qcom/tuna-mtp-kiwi.dtsi b/qcom/tuna-mtp-kiwi.dtsi new file mode 100644 index 00000000..386415d7 --- /dev/null +++ b/qcom/tuna-mtp-kiwi.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-mtp.dtsi" diff --git a/qcom/tuna-mtp-overlay.dts b/qcom/tuna-mtp-overlay.dts new file mode 100644 index 00000000..a9ea196b --- /dev/null +++ b/qcom/tuna-mtp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 0>; +}; diff --git a/qcom/tuna-mtp-qmp1000-overlay.dts b/qcom/tuna-mtp-qmp1000-overlay.dts new file mode 100644 index 00000000..f366cb86 --- /dev/null +++ b/qcom/tuna-mtp-qmp1000-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-mtp-qmp1000.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP QMP1000"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 1>; +}; diff --git a/qcom/tuna-mtp-qmp1000.dtsi b/qcom/tuna-mtp-qmp1000.dtsi new file mode 100644 index 00000000..386415d7 --- /dev/null +++ b/qcom/tuna-mtp-qmp1000.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-mtp.dtsi" diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi new file mode 100644 index 00000000..9df4770a --- /dev/null +++ b/qcom/tuna-mtp.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ diff --git a/qcom/tuna-qrd-overlay.dts b/qcom/tuna-qrd-overlay.dts new file mode 100644 index 00000000..571501ce --- /dev/null +++ b/qcom/tuna-qrd-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", + "qcom,qrd"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <11 0>; +}; diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi new file mode 100644 index 00000000..9df4770a --- /dev/null +++ b/qcom/tuna-qrd.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ diff --git a/qcom/tuna-rcm-kiwi-overlay.dts b/qcom/tuna-rcm-kiwi-overlay.dts new file mode 100644 index 00000000..878afb01 --- /dev/null +++ b/qcom/tuna-rcm-kiwi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-rcm-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna RCM + kiwi WLAN"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <21 1>; +}; diff --git a/qcom/tuna-rcm-kiwi.dtsi b/qcom/tuna-rcm-kiwi.dtsi new file mode 100644 index 00000000..eb5ff5d3 --- /dev/null +++ b/qcom/tuna-rcm-kiwi.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-cdp.dtsi" diff --git a/qcom/tuna-rcm-overlay.dts b/qcom/tuna-rcm-overlay.dts new file mode 100644 index 00000000..8ca3a067 --- /dev/null +++ b/qcom/tuna-rcm-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna RCM"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <21 0>; +}; diff --git a/qcom/tuna-rcm.dtsi b/qcom/tuna-rcm.dtsi new file mode 100644 index 00000000..eb5ff5d3 --- /dev/null +++ b/qcom/tuna-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-cdp.dtsi" diff --git a/qcom/tuna-vm-dma-heaps.dtsi b/qcom/tuna-vm-dma-heaps.dtsi new file mode 100644 index 00000000..f784d64d --- /dev/null +++ b/qcom/tuna-vm-dma-heaps.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + depends-on-supply = <&qcom_scm>; + + qcom,ms1 { + qcom,dma-heap-name = "qcom,ms1"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms2 { + qcom,dma-heap-name = "qcom,ms2"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms3 { + qcom,dma-heap-name = "qcom,ms3"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + }; +}; diff --git a/qcom/tuna-walt.dtsi b/qcom/tuna-walt.dtsi new file mode 100644 index 00000000..ace295e6 --- /dev/null +++ b/qcom/tuna-walt.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + walt { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom,cycle-cntr { + compatible = "qcom,epss"; + reg = <0x17D91000 0x1000>, + <0x17D92000 0x1000>, + <0x17D93000 0x1000>, + <0x17D94000 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2", + "freq-domain3"; + }; + }; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index a26e7263..b7a1524e 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -358,12 +358,21 @@ #include "tuna-reserved-memory.dtsi" #include "msm-arm-smmu-tuna.dtsi" #include "tuna-dma-heaps.dtsi" +#include "tuna-vm-dma-heaps.dtsi" &reserved_memory { #address-cells = <2>; #size-cells = <2>; ranges; + cdsp_eva_mem: cdsp_eva_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + /* global autoconfigured region for contiguous allocations */ system_cma: linux,cma { compatible = "shared-dma-pool"; @@ -375,6 +384,21 @@ }; }; +&firmware { + qcom_scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; @@ -442,6 +466,11 @@ interrupts = ; }; + qcom,hdcp { + compatible = "qcom,hdcp"; + qcom,use-smcinvoke = <1>; + }; + arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , @@ -510,6 +539,20 @@ }; }; + cache-controller@24800000 { + compatible = "qcom,tuna-llcc"; + reg = <0x24800000 0x200000>, <0x25800000 0x200000>, + <0x24C00000 0x200000>, <0x25C00000 0x200000>, + <0x26800000 0x200000>, <0x26C00000 0x200000>; + + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_or_base", + "llcc_broadcast_and_base"; + + interrupts = ; + cap-based-alloc-and-pwr-collapse; + }; + apps_rsc: rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; @@ -654,7 +697,7 @@ pdc: interrupt-controller@b220000 { compatible = "qcom,tuna-pdc", "qcom,pdc"; - reg = <0xb220000 0x10000>, <0x17c000f0 0x60>; + reg = <0xb220000 0x10000>, <0x174000f0 0x64>; qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>, <10 230 1>, <11 724 1>, <12 716 1>, <13 727 1>, <14 720 1>, <15 726 1>, @@ -683,6 +726,36 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; + qcom,gpios-reserved = <54>; + }; + + slimbam: bamdma@6c04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x6c04000 0x20000>, <0x6c8f000 0x1000>; + reg-names = "bam", "bam_remote_mem"; + interrupts = ; + num-channels = <31>; + #dma-cells = <1>; + qcom,controlled-remotely; + qcom,ee = <1>; + qcom,num-ees = <2>; + }; + + slim_msm: slim@6c40000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0x6c40000 0x2c000>, <0x6c8E000 0x1000>; + reg-names = "ctrl", "slimbus_remote_mem"; + interrupts = ; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; }; tcsr_mutex_block: syscon@1f40000 { @@ -743,6 +816,14 @@ #mbox-cells = <1>; }; + qcom,tmecom-qmp-client { + compatible = "qcom,tmecom-qmp-client"; + mboxes = <&qmp_tme 0>; + mbox-names = "tmecom"; + label = "tmecom"; + depends-on-supply = <&qmp_tme>; + }; + qcom,smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; @@ -867,6 +948,28 @@ }; }; + qcom,smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + qcom,smp2p-soccp { compatible = "qcom,smp2p"; qcom,smem = <617>, <616>; @@ -1250,13 +1353,17 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; - reg = <0x1d84000 0x3000>; - reg-names = "ufs_mem"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x18000>; + reg-names = "ufs_mem", "ice"; + interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; #reset-cells = <1>; + qcom,ice-use-hwkm; + lanes-per-direction = <2>; clock-names = "core_clk", @@ -1310,6 +1417,69 @@ status = "disabled"; }; + qcom_tzlog: tz-log@14680720 { + compatible = "qcom,tz-log"; + reg = <0x14680720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + tmecrashdump-address-offset = <0x81CA0000>; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x28000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,offload-ops-support; + qcom,bam-pipe-offload-cpb-hlos = <1>; + qcom,bam-pipe-offload-hlos-cpb = <3>; + qcom,bam-pipe-offload-hlos-cpb-1 = <8>; + qcom,bam-pipe-offload-hlos-hlos = <4>; + qcom,bam-pipe-offload-hlos-hlos-1 = <9>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + qcom,no-clk-gating; + interconnect-names = "data_path"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x0480 0x0>, + <&apps_smmu 0x0481 0x0>; + qcom,iommu-dma = "atomic"; + dma-coherent; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x0481 0x0>; + dma-coherent; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x0483 0x0>; + qcom,iommu-vmid = <0x9>; + qcom,secure-context-bank; + dma-noncoherent; + }; + }; + + rng: rng@10c3000 { + compatible = "qcom,trng"; + reg = <0x10c3000 0x1000>; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + spmi_bus: spmi0_bus: qcom,spmi@c42d000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc42d000 0x4000>, @@ -1477,6 +1647,14 @@ }; }; + gh-secure-vm-loader@2 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <35>; + qcom,vmid = <50>; + qcom,firmware-name = "cpusys_vm"; + memory-region = <&cpusys_vm_mem>; + }; + qcom,pmic_glink_log { compatible = "qcom,qti-pmic-glink"; qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; @@ -1628,6 +1806,16 @@ #size-cells = <2>; ranges; + gunyah_hyp_mem: gunyah_hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0xe00000>; + }; + + cpusys_vm_mem: cpusys_vm_region@80e00000 { + no-map; + reg = <0x0 0x80e00000 0x0 0x400000>; + }; + aop_cmd_db_mem: aop_cmd_db_region@81c60000 { compatible = "qcom,cmd-db"; no-map; @@ -1649,6 +1837,30 @@ alignment = <0x0 0x400000>; size = <0x0 0x4800000>; }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + size = <0x0 0xc800000>; + alignment = <0x0 0x400000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; }; #include "tuna-pinctrl.dtsi" @@ -1657,6 +1869,7 @@ #include "tuna-qupv3.dtsi" #include "msm-rdbg.dtsi" #include "tuna-pmic-overlay.dtsi" +#include "tuna-walt.dtsi" &qupv3_se7_2uart { status = "ok";