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ARM: dts: msm: add sde_rscc register offset to cesta for sun target

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Add the sde_rscc register offset to help in accessing the cesta
status registers.

Change-Id: I438002605a1bdf3ca06c92f4594a71bce70ef387
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This commit is contained in:
Veera Sundaram Sankaran
2024-06-20 15:33:11 -07:00
committed by Vaishali Gupta
parent 6c2ba9b656
commit 4b3bee8622
2 changed files with 5 additions and 3 deletions
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5
display/sun-sde.dtsi
View File

@@ -210,14 +210,15 @@
sde_cesta: qcom,sde_cesta@0x0af30000 {
cell-index = <0>;
compatible = "qcom,sde-cesta";
reg = <0xaf30000 0x60>,
reg = <0x0af20000 0x850>,
<0xaf30000 0x60>,
<0xaf31000 0x30>,
<0xaf32000 0x30>,
<0xaf33000 0x30>,
<0xaf34000 0x30>,
<0xaf35000 0x30>,
<0xaf36000 0x30>;
reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>;

3
display/trustedvm-sun-sde.dtsi
View File

@@ -37,7 +37,8 @@
qcom,sde-vm-exclude-reg-names = "sid_phys";
qcom,tvm-include-reg = <0xaf30000 0x60>,
qcom,tvm-include-reg = <0x0af20000 0x850>,
<0xaf30000 0x60>,
<0xaf31000 0x30>,
<0xaf32000 0x30>,
<0xaf33000 0x30>,