From 4b3bee8622d5c011674e7569015c7579f0da7f93 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Thu, 20 Jun 2024 15:33:11 -0700 Subject: [PATCH] ARM: dts: msm: add sde_rscc register offset to cesta for sun target Add the sde_rscc register offset to help in accessing the cesta status registers. Change-Id: I438002605a1bdf3ca06c92f4594a71bce70ef387 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde.dtsi | 5 +++-- display/trustedvm-sun-sde.dtsi | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f5413498..72fe00dc 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -210,14 +210,15 @@ sde_cesta: qcom,sde_cesta@0x0af30000 { cell-index = <0>; compatible = "qcom,sde-cesta"; - reg = <0xaf30000 0x60>, + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, <0xaf31000 0x30>, <0xaf32000 0x30>, <0xaf33000 0x30>, <0xaf34000 0x30>, <0xaf35000 0x30>, <0xaf36000 0x30>; - reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi index 93aa250c..fd827da3 100644 --- a/display/trustedvm-sun-sde.dtsi +++ b/display/trustedvm-sun-sde.dtsi @@ -37,7 +37,8 @@ qcom,sde-vm-exclude-reg-names = "sid_phys"; - qcom,tvm-include-reg = <0xaf30000 0x60>, + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, <0xaf31000 0x30>, <0xaf32000 0x30>, <0xaf33000 0x30>,