Merge "ARM: dts: msm: add support to configure hw-fence ctl reg offset"
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@@ -12,10 +12,12 @@
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compatible = "qcom,sde-kms";
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reg = <0x0ae00000 0x93800>,
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<0x0aeb0000 0x2008>,
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<0x0af80000 0x7000>;
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<0x0af80000 0x7000>,
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<0x400000 0x2000>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"regdma_phys";
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"regdma_phys",
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"ipcc_reg";
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/* interrupt config */
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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@@ -261,6 +263,11 @@
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qcom,sde-qos-cpu-dma-latency = <300>;
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qcom,sde-qos-cpu-irq-latency = <300>;
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qcom,sde-ipcc-protocol-id = <0x4>;
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qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
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qcom,sde-soccp-controller = <&soccp_pas>;
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qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-reg-dma-off = <0 0x800>;
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qcom,sde-reg-dma-id = <0 1>;
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