Merge "ARM: dts: msm: add support to configure hw-fence ctl reg offset"

This commit is contained in:
qctecmdr
2024-02-05 09:23:13 -08:00
committed by Gerrit - the friendly Code Review server
2 changed files with 15 additions and 2 deletions

View File

@@ -12,10 +12,12 @@
compatible = "qcom,sde-kms";
reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>,
<0x0af80000 0x7000>;
<0x0af80000 0x7000>,
<0x400000 0x2000>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys";
"regdma_phys",
"ipcc_reg";
/* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -261,6 +263,11 @@
qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>;
qcom,sde-ipcc-protocol-id = <0x4>;
qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
qcom,sde-soccp-controller = <&soccp_pas>;
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0 0x800>;
qcom,sde-reg-dma-id = <0 1>;