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dt-bindings: Add devicetree bindings for dcvs drivers

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Add snapshot of dcvs dt bindings as of qcom-6.1
commit 96af901712d3 ("dt-bindings: soc: qcom: Document
CRMB and CRMC regs").

Change-Id: I305f06bee1895feabec2b85b2c5ed4fa80895f83
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Signed-off-by: Gurbir Arora <quic_gurbaror@quicinc.com>
This commit is contained in:
Amir Vajid
2023-07-25 15:50:55 -07:00
committed by Gerrit - the friendly Code Review server
parent 342af7cf1c
commit 467330472c
11 changed files with 843 additions and 0 deletions
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40
bindings/perf/qcom-llcc-pmu.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom-llcc-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) LLCC PMU Bindings
maintainers:
- avajid@quicinc.com <quic_avajid@quicinc.com>
- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
description: |
This represents the miss counters located in the LLCC hardware counters.
Only one event is supported.
properties:
compatible:
enum:
- qcom,llcc-pmu-ver1
- qcom,llcc-pmu-ver2
reg:
description: base address and size of DDR_LAGG region
reg-names:
const: lagg-base
required:
- compatible
- reg
- reg-names
examples:
- |
llcc_pmu: llcc-pmu {
compatible = "qcom,qcom-llcc-pmu-ver1";
reg = < 0x090CC000 0x300 >;
reg-names = "lagg-base";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,bwmon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) BWMON Driver
maintainers:
- avajid@quicinc.com <quic_avajid@quicinc.com>
- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
description: |
The Qualcomm Technologies, Inc. BWMON Driver monitors bandwidth counters that
represent the read/write traffic through various interconnects in the system
and uses this data to vote for DCVS HW (memory) frequencies. Each device
represents a separate bandwidth monitor present on the Qualcomm Technologies,
Inc. (QTI) chipset. This driver is a refactor of the bimc-bwmon driver that
was previously developed.
properties:
compatible:
enum:
- qcom,bwmon
- qcom,bwmon2
- qcom,bwmon3
- qcom,bwmon4
- qcom,bwmon5
reg:
maxItems: 2
reg-names:
- const: base
- const: global_base
interrupts:
description: Lists the threshold IRQ.
qcom,mport:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The hardware master port that this device can monitor
qcom,target-dev:
$ref: /schemas/types.yaml#/definitions/uint32
description:
A phandle to the QTI DCVS HW device node that this
node will be using for voting in the SLOW path.
qcom,hw-timer-hz:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Hardware sampling rate in Hz. This field must be
specified for "qcom,bwmon4"
qcom,byte-mid-match:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Byte count MID match value
qcom,byte-mid-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Byte count MID mask value
qcom,count-unit:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Number of bytes monitor counts in
required:
- compatible
- reg
- reg-names
- interrupts
- qcom,target-dev
- qcom,hw-timer-hz
examples:
- |
bwmon_llcc: qcom,bwmon-llcc@90b6400 {
compatible = "qcom,bwmon4";
reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
};

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bindings/soc/qcom/qcom,c1-dcvs-v2.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,c1-dcvs-v2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) C1 DCVS V2 Driver
maintainers:
- avajid@quicinc.com <quic_avajid@quicinc.com>
- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
description: |
The QTI C1 DCVS V2 Driver provides sysfs node for user space to
communicate to CPUCP firmware about C1 DCVS algorithm based on
SCMI consolidation protocol. This driver is refactor of c1dcvs_scmi.c
and c1dcvs_vendor.c based on SCMI consolidation.
properties:
compatible:
const: qcom,c1dcvs-v2
required:
- compatible
examples:
- |
qcom_c1dcvs: qcom,c1dcvs {
compatible = "qcom,c1dcvs-v2";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,cpucp-log.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. CPUCP Logging
description: |
CPUCP logging is a device that uses mailbox to collect the logs
generated from cpucp, and dump them into a dedicated log buffer
through ipc_logging framework.
An instance of cpucp-log should have the mailbox controller phandle and
addresses of log buffer set aside for this purpose.
properties:
compatible:
const: qcom,cpucp-log
mboxes:
description:
reference to "cpucp" mailbox, as described in mailbox/mailbox.txt.
required:
- compatible
- mboxes
- reg
examples:
- |
cpucp_log: qcom,cpucp_log@fd04780 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,cpucp-log";
reg = <0x0fd04580 0x200>, <0x0fd04780 0x200>;
mboxes = <&cpucp 1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,cpucp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. CPUCP Mailbox controller driver
description: |
This mailbox controller act as interface to do doorbell between
HLOS and CPUCP subsystem.
properties:
compatible:
const: qcom,cpucp
reg:
items:
- description: tx base address
- description: rx base address
"#mbox-cells":
const: 1
required:
- compatible
- reg
- "#mbox-cells"
examples:
- |
qcom,cpucp@0f400000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,cpucp";
reg = <0x0f400000 0x10>, <0x0fd90000 0x2000>;
#mbox-cells = <1>;
status = "ok";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,cpufreq-stats-v2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) CPU Freq Stats V2 Driver
maintainers:
- avajid@quicinc.com <quic_avajid@quicinc.com>
- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
description: |
The QTI CPU freq stats V2 Driver provides sysfs node for user space to
communicate to CPUCP firmware about CPU freq stats algorithm based on
SCMI consolidation protocol. This driver is refactor of
cpufreq_stats_vendor.c and cpufreq_stats_scmi.c based on SCMI consolidation.
properties:
compatible:
const: qcom,cpufreq-stats-v2
required:
- compatible
examples:
- |
qcom_cpufreq_stats: qcom,cpufreq_stats {
compatible = "qcom,cpufreq-stats-v2";
};

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bindings/soc/qcom/qcom,dcvs-fp.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,dcvs-fp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) DCVS Fast Path Interface
maintainers:
- avajid@quicinc.com <quic_avajid@quicinc.com>
- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
description: |
The QTI DCVS Fast Path Interface utilizes the fast-path TCS hardware interface
provided by RPMH RSC. As such, this driver is a child node and client of an
RPMH RSC device that has a fast path TCS. The driver is intended to be used by
the QTI DCVS framework for DCVS_FAST_PATH voting on DDR and LLCC HW.
properties:
compatible:
const: qcom,dcvs-fp
qcom,ddr-bcm-name:
$ref: /schemas/types.yaml#/definitions/string
description: ddr fast path bcm node name
qcom,llcc-bcm-name:
$ref: /schemas/types.yaml#/definitions/string
description: llcc fast path bcm node name
required:
- compatible
- qcom,ddr-bcm-name
- qcom,llcc-bcm-name
examples:
- |
apps_rsc: rsc@18200000 {
compatible = "qcom,rpmh-rsc";
dcvs_fp: qcom,dcvs-fp {
compatible = "qcom,dcvs-fp";
qcom,ddr-bcm-name = "MC3";
qcom,llcc-bcm-name = "SH8";
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,dcvs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) DCVS Driver
maintainers:
- avajid@quicinc.com <quic_avajid@quicinc.com>
- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
description: |
The Qualcomm Technologies, Inc. (QTI) DCVS Driver manages several DCVS
hardware types (e.g. DDR) and their voting interfaces/paths (e.g. DCVS Fast
Path) that are supported on various QTI chipsets. An instance of qcom-dcvs
must be described in three levels of device nodes. The first level describes
the parent node of the system, and the second level describes a particular
DCVS HW type that is supported while the third level describes the various
paths (i.e. voting interfaces) that this particular DCVS HW type supports.
properties:
compatible:
const: qcom,dcvs
child-node:
description: Second level nodes for dcvs hw
type: object
properties:
compatible:
const: qcom,dcvs-hw
reg:
items:
- description: base address for voting registers (required for L3)
- description: base address for frequency table (required for L3)
reg-names:
- const: l3-base
- const: l3tbl-base
qcom,dcvs-hw-type:
$ref: /schemas/types.yaml#/definitions/uint32
description:
DCVS HW type which should be DCVS_DDR, DCVS_LLCC,
DCVS_L3, or DCVS_DDRQOS depending on which dcvs hw
block this node is describing.
qcom,bus-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: Bus width of hardware interface (in Bytes).
qcom,freq-tbl:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Array of frequencies or phandle to an array of frequencies in units
of kHz that this hardware device supports. A phandle must be used
in conjunction with the optional "qcom,ddr-type" property to support
multiple DDR types. Required for all devices except DCVS_L3.
qcom,ddr-type:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Specifies the DDR type supported by the corresponding
"qcom,freq-tbl" property.
qcom,ftbl-row-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Row size of the frequency table. Applicable for DCVS_L3 devices.
child-node:
description: Third level nodes for dcvs paths
type: object
properties:
compatible:
const: qcom,dcvs-path
qcom,dcvs-path-type:
$ref: /schemas/types.yaml#/definitions/uint32
description:
DCVS path type which should be DCVS_SLOW_PATH,
DCVS_FAST_PATH, or DCVS_PERCPU_PATH. The slow path
supports multiple clients and is not atomic context
friendly. The fast path is a single client lockless
path that utilizes the dcvs-fp interface. The percpu
path is a single client per-cpu lockless path that
utilizes per-cpu hardware voting registers.
qcom,shared-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Physical address offset to the base address described in
the second level hw node that is used to configure the
vote for the DCVS_SLOW_PATH. Only required for DCVS_L3
child nodes that are using the DCVS_SLOW_PATH.
qcom,percpu-offset:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Array of physical address offsets to the base address
described in the second level hw node that is used to
configure the per-cpu votes for the DCVS_PERCPU_PATH.
The number of offsets must match the number of CPUs.
Only required for DCVS_L3 child nodes that are using the
DCVS_PERCPU_PATH.
interconnects:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
Pairs of phandles and interconnect provider specificers
to denote the edge source and destination ports of the
desired interconnect path. Only required for DCVS_DDR
and DCVS_LLCC child nodes that are using the
DCVS_SLOW_PATH.
qcom,fp-voter:
$ref: /schemas/types.yaml#/definitions/phandle
description:
A phandle to the QTI DCVS FP node which is used for
"fast path" LLCC and DDR voting. Only required for
DCVS_DDR and DCVS_LLCC child nodes that are using the
DCVS_FAST_PATH.
required:
- compatible
- qcom,dcvs-path-type
required:
- compatible
- qcom,dcvs-hw-type
- qcom,bus-width
- qcom,freq-tbl
required:
- compatible
examples:
- |
apps_rsc: rsc@18200000 {
compatible = "qcom,rpmh-rsc";
dcvs_fp: qcom,dcvs-fp {
compatible = "qcom,dcvs-fp";
qcom,ddr-bcm-name = "MC3";
qcom,llcc-bcm-name = "SH8";
};
};
ddr_freq_table: ddr-freq-table {
ddr4 {
qcom,ddr-type = <7>;
qcom,freq-tbl =
< 200000 >,
< 451000 >,
< 547000 >,
< 681000 >,
< 768000 >,
< 1017000 >,
< 1555000 >,
< 1708000 >,
< 2092000 >,
};
ddr5 {
qcom,ddr-type = <8>;
qcom,freq-tbl =
< 200000 >,
< 451000 >,
< 547000 >,
< 681000 >,
< 768000 >,
< 1017000 >,
< 1555000 >,
< 1708000 >,
< 2092000 >,
< 2736000 >,
< 3196000 >;
}
};
qcom_dcvs: qcom,dcvs {
compatible = "qcom,dcvs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <DCVS_DDR>;
qcom,bus-width = <4>;
qcom,freq-tbl = <&ddr_freq_table>;
ddr_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <DCVS_SLOW_PATH>;
interconnects = <&mc_virt MASTER_LLCC
&mc_virt SLAVE_EBI1>;
};
ddr_dcvs_fp: fp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <DCVS_FAST_PATH>;
qcom,fp-voter = <&dcvs_fp>;
};
};
qcom_l3_dcvs_hw: l3 {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <DCVS_L3>;
qcom,bus-width = <32>;
reg = <0x18590000 0x4000>, <0x18590100 0xa0>;
reg-names = "l3-base", "l3tbl-base";
l3_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <DCVS_SLOW_PATH>;
qcom,shared-offset = <0x0090>;
};
l3_dcvs_percpu: percpu {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <DCVS_PERCPU_PATH>;
qcom,percpu-offsets =
< 0x1090 >,
< 0x1094 >,
< 0x1098 >,
< 0x109C >,
< 0x2090 >,
< 0x2094 >,
< 0x2098 >,
< 0x3090 >;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,memlat.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) Memlat Driver
maintainers:
- avajid@quicinc.com <quic_avajid@quicinc.com>
- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
description: |
The Qualcomm Technologies, Inc. (QTI) Memlat Driver monitors CPU performance
counters to identify memory latency bound workloads and votes for DCVS HW
(memory) frequencies based on the workload characteristics. This driver is a
refactor of the arm-memlat-mon driver that was previously developed. An
instance of qcom-memlat must be described in three levels of device nodes.
The first level describes the parent node. The second level describes a memlat
group which manages voting for a particular DCVS HW device (e.g. DDR). The
third level describes a memlat monitor ("mon") which comprises of a list of
CPUs whose configured performance counters are used to vote for a DCVS HW
frequency for the memlat group that it is part of.
properties:
compatible:
const: qcom,memlat
qcom,cyc-ev:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The cycle count event that this driver monitors. Defaults to 0x11 if not
specified.
qcom,inst-ev:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The instruction count event that this driver monitors. Defaults to 0x08
if not specified.
qcom,stall-ev:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The stall cycle event that this driver monitors. Assumes 100% stall if
not specified.
child-node:
description: Second level nodes for memlat groups
type: object
properties:
compatible:
const: qcom,memlat-grp
qcom,target-dev:
$ref: /schemas/types.yaml#/definitions/phandle
description:
A phandle to the QTI DCVS HW device node that this
node will be using for voting.
qcom,miss-ev:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The cache miss event that this memlat group uses to measure memory
latency sensitivity to this DCVS HW.
qcom,sampling-path:
$ref: /schemas/types.yaml#/definitions/phandle
description:
A phandle to the QTI DCVS PATH device node that the memlat sampling
algorithm will use for voting. This property or the
qcom,threadlat-path property is required.
qcom,threadlat-path:
$ref: /schemas/types.yaml#/definitions/phandle
description:
A phandle to the QTI DCVS PATH device node that the threadlat
algorithm will use for voting. This property or the
qcom,sampling-path property is required.
qcom,access-ev:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The cache access event that this driver optionally monitors to
calculate writeback percentage.
qcom,wb-ev:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The cache writeback event that this driver optionally monitors to
calculate writeback percentage.
child-node:
description: Third level nodes for memlat mons
type: object
properties:
compatible:
items: qcom,memlat-mon
qcom,cpulist:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: List of CPU phandles to be monitored by this mon.
qcom,cpufreq-memfreq-tbl:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
A mapping table of cpu frequency to a memory (i.e. DCVS HW)
frequency (both in units of kHz). A phandle that contains this
property may be provided instead (to share tables across nodes).
A phandle must be used in conjunction with the optional
"qcom,ddr-type" property to support multiple DDR types.
qcom,sampling-enabled:
type: boolean
description:
Used to determine if this mon should be used by the memlat sampling
algorithm. One of the qcom,sampling-enabled, qcom,threadlat-enabled,
or qcom,cpucp-enabled properties is required to be enabled.
qcom,threadlat-enabled:
type: boolean
description:
Used to determine if this mon should be used by the threadlat
algorithm. One of the qcom,sampling-enabled, qcom,threadlat-enabled,
or qcom,cpucp-enabled properties is required to be enabled.
qcom,cpucp-enabled:
type: boolean
description:
Used to determine if this mon should be used by the cpucp
algorithm. One of the qcom,sampling-enabled, qcom,threadlat-enabled,
or qcom,cpucp-enabled properties is required to be enabled.
qcom,compute-mon:
type: boolean
description:
Used to configure mon as a "compute" mon which means it monitors
compute bound workloads.
qcom,ddr-type:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Specifies the DDR type supported by the corresponding
"qcom,cpufreq-memfreq-tbl" property.
required:
- compatible
- qcom,cpulist
- qcom,cpufreq-memfreq-tbl
- qcom,sampling-enabled
required:
- compatible
- qcom,target-dev
- qcom,miss-ev
- qcom,sampling-path
required:
- compatible
examples:
- |
qcom_dcvs: qcom,dcvs {
compatible = "qcom,dcvs";
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
ddr_dcvs_fp: fp {
compatible = "qcom,dcvs-path";
};
};
};
silver_ddr_tbl: qcom,silver-ddr-tbl {
ddr4-tbl {
qcom,ddr-type = <7>;
qcom,cpufreq-memfreq-tbl =
< 300000 200000 >,
< 691200 451000 >,
< 1190400 547000 >,
< 1459200 768000 >,
< 1900800 1017000 >;
};
ddr5-tbl {
qcom,ddr-type = <8>;
qcom,cpufreq-memfreq-tbl =
< 300000 200000 >,
< 691200 451000 >,
< 1190400 547000 >,
< 1459200 768000 >,
< 1900800 1555000 >;
}
};
qcom_memlat: qcom,memlat {
compatible = "qcom,memlat";
memlat_ddr: ddr {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
qcom,sampling-path = <&ddr_dcvs_fp>;
qcom,miss-ev = <0x1000>;
silver_ddr_lat: silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cpufreq-memfreq-tbl = <&silver_ddr_tbl>;
qcom,sampling-enabled;
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,mpam.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) MPAM Driver
maintainers:
- avajid@quicinc.com <quic_avajid@quicinc.com>
- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
description: |
The Qualcomm Technologies, Inc. (QTI) MPAM Driver provides sysfs nodes for
userspace clients to communicate MPAM configuration settings with CPUCP
firmware via consolidated SCMI protocol.
properties:
compatible:
const: qcom,mpam
required:
- compatible
examples:
- |
qcom_mpam: qcom,mpam {
compatible = "qcom,mpam";
};

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bindings/soc/qcom/qcom,pmu.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) PMU Monitor Driver
maintainers:
- avajid@quicinc.com <quic_avajid@quicinc.com>
- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
description: |
The Qualcomm Technologies, Inc. PMU Driver provides an interface to request
for per-CPU performance counters that are available on some QTI chipsets.
properties:
compatible:
const: qcom,pmu
qcom,long-counter:
description:
Specify if the pmu counters are long (64 bit) counters.
type: boolean
qcom,pmu-events-tbl:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
A list of the pmu events to be configured on the cpus. The first column in
the table contains the event id and the second column contains a bit mask
(cpumask) of cpus for which the event should be configured on. The third
column contains the AMU id for events that are present as part of AMU
counters. The list of ids can be found in enum amu_counters
(include/soc/qcom/pmu_lib.h). 0xFF represents an invalid id. The fourth
column represents the index in enum cpucp_ev_idx
(include/linux/scmi_pmu.h), which is a shared enum between hlos and cpucp.
This helps maintain the sequence of events when pmu hardware ids or cached
counts are shared between hlos and cpucp. 0xFF represents an invalid
index, which means this event is not supposed to be shared between hlos
and cpucp.
required:
- compatible
- qcom,pmu-events-tbl
examples:
- |
qcom,pmu {
compatible = "qcom,pmu";
qcom,long-counter;
qcom,pmu-events-tbl =
< 0x0008 0xFF 0x02 0x02 >,
< 0x0011 0xFF 0x01 0x01 >,
< 0x0017 0xFF 0xFF 0x04 >,
< 0x002A 0xFF 0xFF 0xFF >,
< 0x1000 0xFF 0xFF 0xFF >;
};