467330472c
Add snapshot of dcvs dt bindings as of qcom-6.1
commit 96af901712d3 ("dt-bindings: soc: qcom: Document
CRMB and CRMC regs").
Change-Id: I305f06bee1895feabec2b85b2c5ed4fa80895f83
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Signed-off-by: Gurbir Arora <quic_gurbaror@quicinc.com>
40 lines
894 B
YAML
40 lines
894 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/qcom/qcom-llcc-pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. (QTI) LLCC PMU Bindings
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maintainers:
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- avajid@quicinc.com <quic_avajid@quicinc.com>
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- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
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description: |
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This represents the miss counters located in the LLCC hardware counters.
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Only one event is supported.
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properties:
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compatible:
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enum:
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- qcom,llcc-pmu-ver1
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- qcom,llcc-pmu-ver2
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reg:
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description: base address and size of DDR_LAGG region
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reg-names:
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const: lagg-base
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required:
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- compatible
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- reg
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- reg-names
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examples:
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- |
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llcc_pmu: llcc-pmu {
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compatible = "qcom,qcom-llcc-pmu-ver1";
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reg = < 0x090CC000 0x300 >;
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reg-names = "lagg-base";
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}; |