467330472c
Add snapshot of dcvs dt bindings as of qcom-6.1
commit 96af901712d3 ("dt-bindings: soc: qcom: Document
CRMB and CRMC regs").
Change-Id: I305f06bee1895feabec2b85b2c5ed4fa80895f83
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Signed-off-by: Gurbir Arora <quic_gurbaror@quicinc.com>
234 lines
7.3 KiB
YAML
234 lines
7.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/qcom/qcom,dcvs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. (QTI) DCVS Driver
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maintainers:
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- avajid@quicinc.com <quic_avajid@quicinc.com>
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- gurbaror@quicinc.com <quic_gurbaror@quicinc.com>
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description: |
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The Qualcomm Technologies, Inc. (QTI) DCVS Driver manages several DCVS
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hardware types (e.g. DDR) and their voting interfaces/paths (e.g. DCVS Fast
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Path) that are supported on various QTI chipsets. An instance of qcom-dcvs
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must be described in three levels of device nodes. The first level describes
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the parent node of the system, and the second level describes a particular
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DCVS HW type that is supported while the third level describes the various
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paths (i.e. voting interfaces) that this particular DCVS HW type supports.
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properties:
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compatible:
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const: qcom,dcvs
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child-node:
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description: Second level nodes for dcvs hw
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type: object
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properties:
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compatible:
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const: qcom,dcvs-hw
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reg:
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items:
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- description: base address for voting registers (required for L3)
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- description: base address for frequency table (required for L3)
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reg-names:
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- const: l3-base
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- const: l3tbl-base
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qcom,dcvs-hw-type:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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DCVS HW type which should be DCVS_DDR, DCVS_LLCC,
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DCVS_L3, or DCVS_DDRQOS depending on which dcvs hw
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block this node is describing.
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qcom,bus-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Bus width of hardware interface (in Bytes).
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qcom,freq-tbl:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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Array of frequencies or phandle to an array of frequencies in units
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of kHz that this hardware device supports. A phandle must be used
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in conjunction with the optional "qcom,ddr-type" property to support
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multiple DDR types. Required for all devices except DCVS_L3.
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qcom,ddr-type:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Specifies the DDR type supported by the corresponding
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"qcom,freq-tbl" property.
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qcom,ftbl-row-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Row size of the frequency table. Applicable for DCVS_L3 devices.
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child-node:
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description: Third level nodes for dcvs paths
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type: object
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properties:
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compatible:
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const: qcom,dcvs-path
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qcom,dcvs-path-type:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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DCVS path type which should be DCVS_SLOW_PATH,
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DCVS_FAST_PATH, or DCVS_PERCPU_PATH. The slow path
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supports multiple clients and is not atomic context
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friendly. The fast path is a single client lockless
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path that utilizes the dcvs-fp interface. The percpu
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path is a single client per-cpu lockless path that
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utilizes per-cpu hardware voting registers.
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qcom,shared-offset:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Physical address offset to the base address described in
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the second level hw node that is used to configure the
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vote for the DCVS_SLOW_PATH. Only required for DCVS_L3
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child nodes that are using the DCVS_SLOW_PATH.
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qcom,percpu-offset:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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Array of physical address offsets to the base address
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described in the second level hw node that is used to
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configure the per-cpu votes for the DCVS_PERCPU_PATH.
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The number of offsets must match the number of CPUs.
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Only required for DCVS_L3 child nodes that are using the
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DCVS_PERCPU_PATH.
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interconnects:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Pairs of phandles and interconnect provider specificers
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to denote the edge source and destination ports of the
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desired interconnect path. Only required for DCVS_DDR
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and DCVS_LLCC child nodes that are using the
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DCVS_SLOW_PATH.
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qcom,fp-voter:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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A phandle to the QTI DCVS FP node which is used for
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"fast path" LLCC and DDR voting. Only required for
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DCVS_DDR and DCVS_LLCC child nodes that are using the
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DCVS_FAST_PATH.
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required:
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- compatible
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- qcom,dcvs-path-type
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required:
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- compatible
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- qcom,dcvs-hw-type
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- qcom,bus-width
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- qcom,freq-tbl
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required:
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- compatible
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examples:
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- |
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apps_rsc: rsc@18200000 {
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compatible = "qcom,rpmh-rsc";
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dcvs_fp: qcom,dcvs-fp {
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compatible = "qcom,dcvs-fp";
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qcom,ddr-bcm-name = "MC3";
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qcom,llcc-bcm-name = "SH8";
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};
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};
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ddr_freq_table: ddr-freq-table {
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ddr4 {
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qcom,ddr-type = <7>;
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qcom,freq-tbl =
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< 200000 >,
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< 451000 >,
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< 547000 >,
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< 681000 >,
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< 768000 >,
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< 1017000 >,
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< 1555000 >,
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< 1708000 >,
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< 2092000 >,
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};
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ddr5 {
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qcom,ddr-type = <8>;
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qcom,freq-tbl =
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< 200000 >,
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< 451000 >,
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< 547000 >,
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< 681000 >,
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< 768000 >,
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< 1017000 >,
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< 1555000 >,
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< 1708000 >,
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< 2092000 >,
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< 2736000 >,
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< 3196000 >;
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}
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};
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qcom_dcvs: qcom,dcvs {
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compatible = "qcom,dcvs";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qcom_ddr_dcvs_hw: ddr {
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compatible = "qcom,dcvs-hw";
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qcom,dcvs-hw-type = <DCVS_DDR>;
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qcom,bus-width = <4>;
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qcom,freq-tbl = <&ddr_freq_table>;
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ddr_dcvs_sp: sp {
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compatible = "qcom,dcvs-path";
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qcom,dcvs-path-type = <DCVS_SLOW_PATH>;
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interconnects = <&mc_virt MASTER_LLCC
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&mc_virt SLAVE_EBI1>;
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};
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ddr_dcvs_fp: fp {
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compatible = "qcom,dcvs-path";
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qcom,dcvs-path-type = <DCVS_FAST_PATH>;
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qcom,fp-voter = <&dcvs_fp>;
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};
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};
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qcom_l3_dcvs_hw: l3 {
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compatible = "qcom,dcvs-hw";
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qcom,dcvs-hw-type = <DCVS_L3>;
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qcom,bus-width = <32>;
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reg = <0x18590000 0x4000>, <0x18590100 0xa0>;
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reg-names = "l3-base", "l3tbl-base";
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l3_dcvs_sp: sp {
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compatible = "qcom,dcvs-path";
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qcom,dcvs-path-type = <DCVS_SLOW_PATH>;
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qcom,shared-offset = <0x0090>;
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};
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l3_dcvs_percpu: percpu {
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compatible = "qcom,dcvs-path";
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qcom,dcvs-path-type = <DCVS_PERCPU_PATH>;
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qcom,percpu-offsets =
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< 0x1090 >,
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< 0x1094 >,
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< 0x1098 >,
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< 0x109C >,
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< 0x2090 >,
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< 0x2094 >,
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< 0x2098 >,
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< 0x3090 >;
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};
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};
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}; |