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ARM: dts: msm: Add cpucp scmi nodes for ravelin

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Add nodes to enable scmi communication to cpucp on ravelin.
Update tx and rx regname for cpucp.

Change-Id: I9674a974e58d8be1eb02063846f5e9e0d1b046c6
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
This commit is contained in:
Swetha Chikkaboraiah
2024-06-14 11:10:49 +05:30
parent 1b78f8027a
commit 33159c6103
1 changed files with 4 additions and 4 deletions
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8
qcom/ravelin.dtsi
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@@ -62,8 +62,8 @@
reg = <0x0 0x17D09100 0x0 0x200>;
ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "arm,scp-shmem";
cpu_scmi_lpri: scmi-shmem@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x0 0x0 0x200>;
};
};
@@ -746,7 +746,7 @@
compatible = "qcom,cpucp";
reg = <0x17400000 0x10>,
<0x17d90000 0x2000>;
reg-names = "rx", "tx";
reg-names = "tx", "rx";
#mbox-cells = <1>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -757,7 +757,7 @@
compatible = "arm,scmi";
mboxes = <&cpucp 0>;
mbox-names = "tx";
shmem = <&cpu_scp_lpri>;
shmem = <&cpu_scmi_lpri>;
scmi_pmu: protocol@86 {
reg = <0x86>;