From 33159c610323c391b66b4f9633520af891648991 Mon Sep 17 00:00:00 2001
From: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
Date: Fri, 14 Jun 2024 11:10:49 +0530
Subject: [PATCH] ARM: dts: msm: Add cpucp scmi nodes for ravelin

Add nodes to enable scmi communication to cpucp on ravelin.
Update tx and rx regname for cpucp.

Change-Id: I9674a974e58d8be1eb02063846f5e9e0d1b046c6
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
---
 qcom/ravelin.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi
index 03f7f28e..09b4e06d 100644
--- a/qcom/ravelin.dtsi
+++ b/qcom/ravelin.dtsi
@@ -62,8 +62,8 @@
 		reg = <0x0 0x17D09100 0x0 0x200>;
 		ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>;
 
-		cpu_scp_lpri: scp-shmem@0 {
-			compatible = "arm,scp-shmem";
+		cpu_scmi_lpri: scmi-shmem@0 {
+			compatible = "arm,scmi-shmem";
 			reg = <0x0 0x0 0x0 0x200>;
 		};
 	};
@@ -746,7 +746,7 @@
 		compatible = "qcom,cpucp";
 		reg =   <0x17400000 0x10>,
 			<0x17d90000 0x2000>;
-		reg-names = "rx", "tx";
+		reg-names = "tx", "rx";
 		#mbox-cells = <1>;
 		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 	};
@@ -757,7 +757,7 @@
 		compatible = "arm,scmi";
 		mboxes = <&cpucp 0>;
 		mbox-names = "tx";
-		shmem = <&cpu_scp_lpri>;
+		shmem = <&cpu_scmi_lpri>;
 
 		scmi_pmu: protocol@86 {
 			reg = <0x86>;