ARM: dts: msm: Add a node for cpufreq cycle counter driver
Add cpufreq cycle counter register information to devicetree in a separate node for use by associated driver. Change-Id: If1b45003a1ce4faca372db2954293493bc45bbb6 Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
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24
qcom/pineapple-walt.dtsi
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24
qcom/pineapple-walt.dtsi
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@@ -0,0 +1,24 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&soc {
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walt {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qcom,cycle-cntr {
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compatible = "qcom,epss";
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reg = <0x17D91000 0x1000>,
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<0x17D92000 0x1000>,
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<0x17D93000 0x1000>,
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<0x17D94000 0x1000>;
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reg-names = "freq-domain0",
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"freq-domain1",
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"freq-domain2",
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"freq-domain3";
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};
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};
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};
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@@ -3432,6 +3432,7 @@
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#include "pineapple-pcie.dtsi"
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#include "pineapple-pcie.dtsi"
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#include "msm-rdbg.dtsi"
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#include "msm-rdbg.dtsi"
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#include "pineapple-thermal.dtsi"
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#include "pineapple-thermal.dtsi"
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#include "pineapple-walt.dtsi"
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&qupv3_se15_2uart {
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&qupv3_se15_2uart {
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status = "ok";
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status = "ok";
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