Merge "ARM: dts: msm: dt snabpshot for Monaco SoC"
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1b7fd4cfae
@@ -54,17 +54,17 @@
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qcom,lmh-dcvs = <&lmh_dcvs0>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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/* compatible = "arm,arch-cache"; */
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compatible = "cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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};
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L1_I_0: l1-icache {
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/* compatible = "arm,arch-cache"; */
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compatible = "cache";
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};
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L1_D_0: l1-dcache {
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/* compatible = "arm,arch-cache"; */
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compatible = "cache";
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};
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};
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@@ -85,11 +85,11 @@
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qcom,lmh-dcvs = <&lmh_dcvs0>;
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L1_I_1: l1-icache {
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/* compatible = "arm,arch-cache"; */
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compatible = "cache";
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};
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L1_D_1: l1-dcache {
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/* compatible = "arm,arch-cache"; */
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compatible = "cache";
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};
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};
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@@ -110,11 +110,11 @@
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qcom,lmh-dcvs = <&lmh_dcvs0>;
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L1_I_2: l1-icache {
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/* compatible = "arm,arch-cache"; */
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compatible = "cache";
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};
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L1_D_2: l1-dcache {
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/* compatible = "arm,arch-cache"; */
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compatible = "cache";
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};
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};
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@@ -135,11 +135,11 @@
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qcom,lmh-dcvs = <&lmh_dcvs0>;
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L1_I_3: l1-icache {
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/* compatible = "arm,arch-cache"; */
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compatible = "cache";
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};
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L1_D_3: l1-dcache {
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/* compatible = "arm,arch-cache"; */
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compatible = "cache";
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};
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};
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