From 58daad1f6c0b31b4711865bfc990457f4dbcbc48 Mon Sep 17 00:00:00 2001 From: Pradnya Dahiwale Date: Wed, 5 Jun 2024 14:47:10 +0530 Subject: [PATCH] ARM: dts: msm: dt snabpshot for Monaco SoC Add dt snapshot of cpu level cache from branch msm-5.15.c2 commit 8ae5ffe89e0f ("ARM: dts: msm: Add mdsp heap for mDSP compute"). Change-Id: Id833a1f0894f29753c0ce08839bf3111b8d57a61 Signed-off-by: Pradnya Dahiwale --- qcom/monaco.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 6f631075..c7000697 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -54,17 +54,17 @@ qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_0: l2-cache { - /* compatible = "arm,arch-cache"; */ - cache-size = <0x80000>; - cache-level = <2>; + compatible = "cache"; + cache-size = <0x80000>; + cache-level = <2>; }; L1_I_0: l1-icache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; L1_D_0: l1-dcache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; }; @@ -85,11 +85,11 @@ qcom,lmh-dcvs = <&lmh_dcvs0>; L1_I_1: l1-icache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; L1_D_1: l1-dcache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; }; @@ -110,11 +110,11 @@ qcom,lmh-dcvs = <&lmh_dcvs0>; L1_I_2: l1-icache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; L1_D_2: l1-dcache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; }; @@ -135,11 +135,11 @@ qcom,lmh-dcvs = <&lmh_dcvs0>; L1_I_3: l1-icache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; L1_D_3: l1-dcache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; };