samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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Merge remote-tracking branch 'quic/display-kernel-dev.lnx.1.0' into display-kernel.lnx.11.0

Browse Source 
CRs              SHA_ID     Commit Message
----------------------------------------------------------------------
3711905           Ic9532583 ARM: dts: msm: add panel configs for MTP and QRD
3705609           I26eeaca7 ARM: dts: msm: enable partial update on sun target
3715338           I436bec07 ARM: dts: msm: add support to configure hw-fence ctl reg offset
3715338           Ife59c04e ARM: dts: msm: add soccp dtsi property to sun target
3711563           I73035019 ARM: dts: msm: Update trustedvm device tree board id for Sun MTP and CDP
3715338           I6a389626 ARM: dts: msm: add support for ipcc protocol for hw fence on sun
3711563           I5812f991 ARM: dts: msm: Add trustedvm device tree files for Sun qrd

CRs-Included: 3711563,3711905,3715338,3705609

Change-Id: Iaaad466046f84ed6f6180c789e5f398ce5dd929b
Signed-off-by: Linux Display <lnxdisplay@localhost>
This commit is contained in:
Linux Display
2024-02-09 01:44:28 +05:30
parent 23308a7e10 81d6848d3c
commit 0f51fe4934
10 changed files with 331 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Kbuild
View File

@@ -17,7 +17,8 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
display/sun-sde-display-mtp-v8-overlay.dtbo
else
dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \
display/trustedvm-sun-sde-display-mtp-overlay.dtbo
display/trustedvm-sun-sde-display-mtp-overlay.dtbo \
display/trustedvm-sun-sde-display-qrd-overlay.dtbo
endif
always-y := $(dtb-y) $(dtbo-y)

6
bindings/sde.txt
View File

@@ -569,9 +569,13 @@ Optional properties:
silver or gold or gold+.
- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec.
- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec.
- qcom,sde-soccp-controller: The phandle for the soccp controller.
This value is optional and only required for targets with SOCCP.
- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature.
- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used
for ipcc registers access.
- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg
offset.
- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline
rotation.
- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin,
@@ -911,8 +915,10 @@ Example:
qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>;
qcom,sde-soccp-controller = <&soccp_pas>;
qcom,sde-ipcc-protocol-id = <0x2>;
qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
qcom,sde-vbif-off = <0 0>;
qcom,sde-vbif-id = <0 1>;

11
display/sun-sde-common.dtsi
View File

@@ -12,10 +12,12 @@
compatible = "qcom,sde-kms";
reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>,
<0x0af80000 0x7000>;
<0x0af80000 0x7000>,
<0x400000 0x2000>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys";
"regdma_phys",
"ipcc_reg";
/* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -261,6 +263,11 @@
qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>;
qcom,sde-ipcc-protocol-id = <0x4>;
qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
qcom,sde-soccp-controller = <&soccp_pas>;
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0 0x800>;
qcom,sde-reg-dma-id = <0 1>;

86
display/sun-sde-display-mtp.dtsi
View File

@@ -1,10 +1,46 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-sde-display.dtsi"
&dsi_vtdr6130_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
};
&dsi_vtdr6130_amoled_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
};
&dsi_vtdr6130_amoled_120hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
@@ -25,6 +61,16 @@
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_120hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sim_panel_au {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
@@ -35,6 +81,44 @@
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sharp_4k_dsc_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
};
&dsi_sharp_4k_dsc_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
};
&dsi_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

134
display/sun-sde-display-qrd.dtsi
View File

@@ -5,6 +5,42 @@
#include "sun-sde-display.dtsi"
&dsi_vtdr6130_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
};
&dsi_vtdr6130_amoled_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
};
&dsi_vtdr6130_amoled_120hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
@@ -45,6 +81,104 @@
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_120hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sim_panel_au {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sharp_4k_dsc_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
};
&dsi_sharp_4k_dsc_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 98 0>;
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
};
&dsi_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_vid {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_10b_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_dual_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
};
&dsi_dual_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_sec_hd_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
};

25
display/sun-sde-display.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-sde.dtsi"
@@ -151,6 +151,29 @@
qcom,ulps-enabled;
};
&dsi_nt37801_amoled_cmd {
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 40 40 720 40>;
};
timing@1 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 40 40 540 40>;
};
};
};
&dsi_nt37801_amoled_cmd_cphy {
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 40 40 720 40>;
};
};
};
&dsi_sharp_4k_dsc_cmd {
qcom,ulps-enabled;
};

2
display/trustedvm-sun-sde-display-cdp-overlay.dts
View File

@@ -13,5 +13,5 @@
model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM";
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,board-id = <0x10001 0>;
qcom,board-id = <1 0>;
};

2
display/trustedvm-sun-sde-display-mtp-overlay.dts
View File

@@ -13,5 +13,5 @@
model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM";
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,board-id = <0x10008 0>;
qcom,board-id = <8 0>;
};

18
display/trustedvm-sun-sde-display-qrd-overlay.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "trustedvm-sun-sde.dtsi"
#include "trustedvm-sun-sde-display-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun QRD SKU1";
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
"qcom,qrd";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>;
};

51
display/trustedvm-sun-sde-display-qrd.dtsi Normal file
View File

@@ -0,0 +1,51 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "trustedvm-sun-sde-display.dtsi"
&dsi_nt37801_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_cmd_cphy {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_video_cphy {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
};