From 754cc63fca8f517ee9525b495e12ab2a834553f1 Mon Sep 17 00:00:00 2001 From: Rui Chen Date: Mon, 22 Jan 2024 10:58:20 +0800 Subject: [PATCH 1/7] ARM: dts: msm: Add trustedvm device tree files for Sun qrd Add the trusted VM devicetree nodes for Sun target. Change-Id: I5812f991777ed30e4a34f6cf4c4d291c9c850374 Signed-off-by: Rui Chen --- Kbuild | 3 +- .../trustedvm-sun-sde-display-qrd-overlay.dts | 18 +++++++ display/trustedvm-sun-sde-display-qrd.dtsi | 51 +++++++++++++++++++ 3 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 display/trustedvm-sun-sde-display-qrd-overlay.dts create mode 100644 display/trustedvm-sun-sde-display-qrd.dtsi diff --git a/Kbuild b/Kbuild index a824c4d7..93ff5622 100644 --- a/Kbuild +++ b/Kbuild @@ -17,7 +17,8 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-mtp-v8-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ - display/trustedvm-sun-sde-display-mtp-overlay.dtbo + display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ + display/trustedvm-sun-sde-display-qrd-overlay.dtbo endif always-y := $(dtb-y) $(dtbo-y) diff --git a/display/trustedvm-sun-sde-display-qrd-overlay.dts b/display/trustedvm-sun-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..8fac6d6e --- /dev/null +++ b/display/trustedvm-sun-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-sun-sde.dtsi" +#include "trustedvm-sun-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/display/trustedvm-sun-sde-display-qrd.dtsi b/display/trustedvm-sun-sde-display-qrd.dtsi new file mode 100644 index 00000000..bee9aabe --- /dev/null +++ b/display/trustedvm-sun-sde-display-qrd.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-sun-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; + From 745316e53e8d59bdffb7b2091c4b28fa2569c5ea Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Mon, 29 Jan 2024 14:19:45 -0800 Subject: [PATCH 2/7] ARM: dts: msm: add support for ipcc protocol for hw fence on sun This change adds the register address and size for ipcc base and the dpu client physical id to be used for hw fencing register access. Change-Id: I6a389626c186cc0f5a10900e890ecd33f6a606d2 Signed-off-by: Christina Oliveira --- display/sun-sde-common.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index d8fe8840..36d306c0 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -12,10 +12,12 @@ compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, - <0x0af80000 0x7000>; + <0x0af80000 0x7000>, + <0x400000 0x2000>; reg-names = "mdp_phys", "vbif_phys", - "regdma_phys"; + "regdma_phys", + "ipcc_reg"; /* interrupt config */ interrupts = ; @@ -261,6 +263,9 @@ qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>; qcom,sde-reg-dma-id = <0 1>; From f3e72ba454a2d19818c300322c603ce075df2a97 Mon Sep 17 00:00:00 2001 From: Rui Chen Date: Tue, 30 Jan 2024 13:09:59 +0800 Subject: [PATCH 3/7] ARM: dts: msm: Update trustedvm device tree board id for Sun MTP and CDP Update the trusted VM devicetree for Sun MTP and CDP. Change-Id: I730350197c25350632bf65adb9aff101685c281d Signed-off-by: Rui Chen --- display/trustedvm-sun-sde-display-cdp-overlay.dts | 2 +- display/trustedvm-sun-sde-display-mtp-overlay.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/display/trustedvm-sun-sde-display-cdp-overlay.dts b/display/trustedvm-sun-sde-display-cdp-overlay.dts index 8daf5e96..757c0dc7 100644 --- a/display/trustedvm-sun-sde-display-cdp-overlay.dts +++ b/display/trustedvm-sun-sde-display-cdp-overlay.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <0x10001 0>; + qcom,board-id = <1 0>; }; diff --git a/display/trustedvm-sun-sde-display-mtp-overlay.dts b/display/trustedvm-sun-sde-display-mtp-overlay.dts index fd2fea89..438ebe59 100644 --- a/display/trustedvm-sun-sde-display-mtp-overlay.dts +++ b/display/trustedvm-sun-sde-display-mtp-overlay.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <0x10008 0>; + qcom,board-id = <8 0>; }; From febcd23b71babca9c5f838a7abdec2f1ca6acc75 Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Wed, 24 Jan 2024 11:33:00 -0800 Subject: [PATCH 4/7] ARM: dts: msm: add soccp dtsi property to sun target This change adds the soccp phandle needed for SOCCP power vote for hw-fencing usecases. Change-Id: Ife59c04e9ba166493f7b7078e0b22848d2a444e2 Signed-off-by: Christina Oliveira --- bindings/sde.txt | 3 +++ display/sun-sde-common.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 779a3da7..b334b16d 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -569,6 +569,8 @@ Optional properties: silver or gold or gold+. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. - qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. +- qcom,sde-soccp-controller: The phandle for the soccp controller. + This value is optional and only required for targets with SOCCP. - qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. - qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used for ipcc registers access. @@ -911,6 +913,7 @@ Example: qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; + qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-ipcc-protocol-id = <0x2>; qcom,sde-ipcc-client-dpu-phys-id = <0x19>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 36d306c0..5d73da80 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -265,6 +265,7 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-soccp-controller = <&soccp_pas>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>; From 945dccd0fde70ff85699e224ced366f2767de00a Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Wed, 24 Jan 2024 15:31:57 -0800 Subject: [PATCH 5/7] ARM: dts: msm: add support to configure hw-fence ctl reg offset This change adds support for configuring mdp hw-fence ctl register offset, as this value can change from target-to-target. Change-Id: I436bec0732473c21cf4753cb292204ce618de512 Signed-off-by: Christina Oliveira --- bindings/sde.txt | 3 +++ display/sun-sde-common.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index b334b16d..6ceef390 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -574,6 +574,8 @@ Optional properties: - qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. - qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used for ipcc registers access. +- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg + offset. - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline rotation. - qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, @@ -916,6 +918,7 @@ Example: qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-ipcc-protocol-id = <0x2>; qcom,sde-ipcc-client-dpu-phys-id = <0x19>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; qcom,sde-vbif-off = <0 0>; qcom,sde-vbif-id = <0 1>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 5d73da80..3300a722 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -266,6 +266,7 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; qcom,sde-soccp-controller = <&soccp_pas>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>; From 317cfa341d2d4e75ef7d20263f6c7b36e3defdaf Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Fri, 2 Feb 2024 10:20:02 +0800 Subject: [PATCH 6/7] ARM: dts: msm: enable partial update on sun target This change enable partial update for cmd mode panel on sun target. Change-Id: I26eeaca7e8a5a59ca9155f5882c1977c66f4ff23 Signed-off-by: Jinfeng Gu --- display/sun-sde-display.dtsi | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 398e121f..1797a0be 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "sun-sde.dtsi" @@ -139,6 +139,29 @@ qcom,ulps-enabled; }; +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 540 40>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; }; From 5abba20156978e2d296f2761fbd1b00ea73166d9 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Tue, 23 Jan 2024 15:08:34 -0800 Subject: [PATCH 7/7] ARM: dts: msm: add panel configs for MTP and QRD Adds panel configuration blocks for panels that aren't physically on Pakala MTP and QRD to their respective device tree files. This enables using these panels in simulation mode on these devices. Change-Id: Ic9532583b2371f17879e69869924f86fe181ff93 Signed-off-by: Kirill Shpin --- display/sun-sde-display-mtp.dtsi | 86 +++++++++++++++++++- display/sun-sde-display-qrd.dtsi | 134 +++++++++++++++++++++++++++++++ 2 files changed, 219 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index 3154f2e3..b3ebded1 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -1,10 +1,46 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "sun-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -25,6 +61,16 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_sim_panel_au { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -35,6 +81,44 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi index 9ffcea89..38786570 100644 --- a/display/sun-sde-display-qrd.dtsi +++ b/display/sun-sde-display-qrd.dtsi @@ -5,6 +5,42 @@ #include "sun-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -45,6 +81,104 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; };