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arm64: dts: rockchip: use cs-gpios for spi1 on ringneck

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commit 53b6445ad08f07b6f4a84f1434f543196009ed89 upstream.

Hardware CS has a very slow rise time of about 6us,
causing transmission errors when CS does not reach
high between transaction.

It looks like it's not driven actively when transitioning
from low to high but switched to input, so only the CPU
pull-up pulls it high, slowly. Transitions from high to low
are fast. On the oscilloscope, CS looks like an irregular sawtooth
pattern like this:
                         _____
              ^         /     |
      ^      /|        /      |
     /|     / |       /       |
    / |    /  |      /        |
___/  |___/   |_____/         |___

With cs-gpios we have a CS rise time of about 20ns, as it should be,
and CS looks rectangular.

This fixes the data errors when running a flashcp loop against a
m25p40 spi flash.

With the Rockchip 6.1 kernel we see the same slow rise time, but
for some reason CS is always high for long enough to reach a solid
high.

The RK3399 and RK3588 SoCs use the same SPI driver, so we also
checked our "Puma" (RK3399) and "Tiger" (RK3588) boards.
They do not have this problem. Hardware CS rise time is good.

Fixes: c484cf93f6 ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard")
Cc: stable@vger.kernel.org
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de>
Link: https://lore.kernel.org/r/20250627131715.1074308-1-jakob.unterwurzacher@cherry.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jakob Unterwurzacher
2025-06-27 15:17:12 +02:00
committed by Greg Kroah-Hartman
parent 645af2f069
commit e51cf5d4aa
1 changed files with 23 additions and 0 deletions
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23
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
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@@ -344,6 +344,18 @@
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
spi1 {
spi1_csn0_gpio_pin: spi1-csn0-gpio-pin {
rockchip,pins =
<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
spi1_csn1_gpio_pin: spi1-csn1-gpio-pin {
rockchip,pins =
<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
};
};
};
&saradc {
@@ -355,6 +367,17 @@
vqmmc-supply = <&vccio_sd>;
};
&spi1 {
/*
* Hardware CS has a very slow rise time of about 6us,
* causing transmission errors.
* With cs-gpios we have a rise time of about 20ns.
*/
cs-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>, <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_csn0_gpio_pin &spi1_csn1_gpio_pin &spi1_miso &spi1_mosi>;
};
&tsadc {
status = "okay";
};