bdedd83bd9
Adds pinctrl configuration to pass esync signal through from hw block to output pin. Also adds esync and oscillator clocks, and makes the DSI PLL clock available to parse for setting clock parent. Change-Id: I09ac2d1a334546452176285712d8c953f94aecf2 Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
360 lines
10 KiB
Plaintext
360 lines
10 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
|
#include <dt-bindings/clock/qcom,dispcc-sun.h>
|
|
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
|
#include <dt-bindings/interconnect/qcom,sun.h>
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
|
|
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
|
|
#include "sun-sde-common.dtsi"
|
|
|
|
&soc {
|
|
ext_disp: qcom,msm-ext-disp {
|
|
compatible = "qcom,msm-ext-disp";
|
|
|
|
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
|
|
compatible = "qcom,msm-ext-disp-audio-codec-rx";
|
|
};
|
|
};
|
|
|
|
qcom_msmhdcp: qcom,msm_hdcp {
|
|
compatible = "qcom,msm-hdcp";
|
|
};
|
|
|
|
sde_dp_pll: qcom,dp_pll@88eb000 {
|
|
compatible = "qcom,dp-pll-3nm-v1";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sde_dp: qcom,dp_display@af54000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,dp-display";
|
|
|
|
usb-phy = <&usb_qmp_dp_phy>;
|
|
qcom,ext-disp = <&ext_disp>;
|
|
usb-controller = <&usb0>;
|
|
qcom,altmode-dev = <&altmode 0>;
|
|
qcom,dp-aux-switch = <&wcd_usbss>;
|
|
|
|
reg = <0xaf54000 0x104>,
|
|
<0xaf54200 0x0c0>,
|
|
<0xaf55000 0x770>,
|
|
<0xaf56000 0x09c>,
|
|
<0x88ebc00 0x200>,
|
|
<0x88eb400 0x200>,
|
|
<0x88eb800 0x200>,
|
|
<0x88eb000 0x200>,
|
|
<0x88e8000 0x020>,
|
|
<0xaee1000 0x034>,
|
|
<0xaf57000 0x09c>,
|
|
<0xaf09000 0x014>;
|
|
reg-names = "dp_ahb", "dp_aux", "dp_link",
|
|
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
|
|
"dp_pll", "usb3_dp_com", "hdcp_physical",
|
|
"dp_p1", "gdsc";
|
|
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <12 0>;
|
|
|
|
#clock-cells = <1>;
|
|
clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&tcsrcc TCSR_USB3_CLKREF_EN>,
|
|
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
|
<&sde_dp_pll 0>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
|
<&sde_dp_pll 1>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
|
clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src",
|
|
"core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent",
|
|
"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
|
|
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
|
|
|
|
qcom,dp-pll = <&sde_dp_pll>;
|
|
qcom,phy-version = <0x800>;
|
|
qcom,aux-cfg0-settings = [20 00];
|
|
qcom,aux-cfg1-settings = [24 13];
|
|
qcom,aux-cfg2-settings = [28 A4];
|
|
qcom,aux-cfg3-settings = [2c 00];
|
|
qcom,aux-cfg4-settings = [30 0a];
|
|
qcom,aux-cfg5-settings = [34 26];
|
|
qcom,aux-cfg6-settings = [38 0a];
|
|
qcom,aux-cfg7-settings = [3c 03];
|
|
qcom,aux-cfg8-settings = [40 b7];
|
|
qcom,aux-cfg9-settings = [44 03];
|
|
|
|
qcom,max-pclk-frequency-khz = <675000>;
|
|
|
|
qcom,widebus-enable;
|
|
qcom,mst-enable;
|
|
qcom,dsc-feature-enable;
|
|
qcom,fec-feature-enable;
|
|
qcom,dsc-continuous-pps;
|
|
|
|
qcom,qos-cpu-mask = <0xf>;
|
|
qcom,qos-cpu-latency-us = <300>;
|
|
|
|
vdda-1p2-supply = <&L3G>;
|
|
vdda-0p9-supply = <&L2D>;
|
|
vdda_usb-0p9-supply = <&L2D>;
|
|
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
|
dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
|
|
|
|
qcom,hbr-rbr-voltage-swing = <0x27 0x2f 0x36 0x3f>,
|
|
<0x31 0x3e 0x3f 0xff>,
|
|
<0x36 0x3f 0xff 0xff>,
|
|
<0x3f 0xff 0xff 0xff>;
|
|
qcom,hbr-rbr-pre-emphasis = <0x20 0x2d 0x34 0x3a>,
|
|
<0x20 0x2e 0x35 0xff>,
|
|
<0x20 0x2e 0xff 0xff>,
|
|
<0x22 0xff 0xff 0xff>;
|
|
|
|
qcom,hbr2-3-voltage-swing = <0x22 0x32 0x36 0x3a>,
|
|
<0x29 0x39 0x3f 0xff>,
|
|
<0x30 0x3f 0xff 0xff>,
|
|
<0x3f 0xff 0xff 0xff>;
|
|
qcom,hbr2-3-pre-emphasis = <0x20 0x2c 0x35 0x3b>,
|
|
<0x22 0x2e 0x36 0xff>,
|
|
<0x22 0x31 0xff 0xff>,
|
|
<0x24 0xff 0xff 0xff>;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <30000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <912000>;
|
|
qcom,supply-max-voltage = <912000>;
|
|
qcom,supply-enable-load = <114000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
|
|
qcom,phy-supply-entry@1 {
|
|
reg = <1>;
|
|
qcom,supply-name = "vdda_usb-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <2500>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,pll-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,pll-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdd_mx";
|
|
qcom,supply-min-voltage =
|
|
<RPMH_REGULATOR_LEVEL_TURBO>;
|
|
qcom,supply-max-voltage =
|
|
<RPMH_REGULATOR_LEVEL_MAX>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition {
|
|
iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>,
|
|
<&smmu_sde_unsec 0xd4e23000 0x002dd000>,
|
|
<&smmu_sde_unsec 0xd2880000 0x05780000>,
|
|
<&smmu_sde_unsec 0xa3500000 0x02c80000>,
|
|
<&smmu_sde_unsec 0xfc800000 0x02b00000>,
|
|
<&smmu_sde_sec 0x0 0x00020000>;
|
|
};
|
|
|
|
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
|
|
compatible = "qcom,smmu_sde_unsec";
|
|
iommus = <&apps_smmu 0x800 0x2>;
|
|
memory-region = <&smmu_sde_iommu_region_partition>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
qcom,iommu-earlymap; /* for cont-splash */
|
|
dma-coherent;
|
|
};
|
|
|
|
smmu_sde_sec: qcom,smmu_sde_sec_cb {
|
|
compatible = "qcom,smmu_sde_sec";
|
|
iommus = <&apps_smmu 0x801 0x0>;
|
|
memory-region = <&smmu_sde_iommu_region_partition>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
qcom,iommu-vmid = <0xa>;
|
|
};
|
|
|
|
sde_cesta: qcom,sde_cesta@0x0af30000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,sde-cesta";
|
|
reg = <0xaf30000 0x60>,
|
|
<0xaf31000 0x30>,
|
|
<0xaf32000 0x30>,
|
|
<0xaf33000 0x30>,
|
|
<0xaf34000 0x30>,
|
|
<0xaf35000 0x30>,
|
|
<0xaf36000 0x30>;
|
|
reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>;
|
|
|
|
clock-names = "branch_clk", "core_clk";
|
|
clock-rate = <575000000 575000000>;
|
|
clock-max-rate = <575000000 575000000>;
|
|
clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>;
|
|
|
|
interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0
|
|
&mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,
|
|
<&mmss_noc MASTER_MDP_DISP_CRM_HW_1
|
|
&mc_virt SLAVE_EBI1_DISP_CRM_HW_1>,
|
|
<&mmss_noc MASTER_MDP_DISP_CRM_HW_2
|
|
&mc_virt SLAVE_EBI1_DISP_CRM_HW_2>,
|
|
<&mmss_noc MASTER_MDP_DISP_CRM_HW_3
|
|
&mc_virt SLAVE_EBI1_DISP_CRM_HW_3>,
|
|
<&mmss_noc MASTER_MDP_DISP_CRM_HW_4
|
|
&mc_virt SLAVE_EBI1_DISP_CRM_HW_4>,
|
|
<&mmss_noc MASTER_MDP_DISP_CRM_HW_5
|
|
&mc_virt SLAVE_EBI1_DISP_CRM_HW_5>,
|
|
<&mmss_noc MASTER_MDP_DISP_CRM_SW_0
|
|
&mc_virt SLAVE_EBI1_DISP_CRM_SW_0>;
|
|
interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1",
|
|
"qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3",
|
|
"qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5",
|
|
"qcom,sde-data-bus-sw-0";
|
|
|
|
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
|
|
};
|
|
};
|
|
|
|
&mdss_mdp {
|
|
clocks =
|
|
<&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
|
|
|
|
clock-names = "gcc_bus", "iface_clk", "vsync_clk", "lut_clk";
|
|
clock-rate = <0 0 19200000 575000000>;
|
|
clock-max-rate = <0 0 19200000 575000000>;
|
|
|
|
qcom,hw-fence-sw-version = <0x1>;
|
|
|
|
mmcx-supply = <&VDD_MMCX_LEVEL>;
|
|
|
|
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
|
|
|
|
qcom,sde-soccp-controller = <&soccp_pas>;
|
|
|
|
qcom,sde-vm-exclude-reg-names = "ipcc_reg";
|
|
|
|
/* data and reg bus scale settings */
|
|
interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
|
|
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
|
<&gem_noc MASTER_APPSS_PROC
|
|
&config_noc SLAVE_DISPLAY_CFG>;
|
|
interconnect-names = "qcom,sde-data-bus0",
|
|
"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
|
|
|
|
qcom,sde-has-idle-pc;
|
|
|
|
qcom,sde-ib-bw-vote = <2500000 0 800000>;
|
|
qcom,sde-dspp-ltm-version = <0x00010003>;
|
|
/* offsets are based off dspp 0, 1, 2, and 3 */
|
|
qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>;
|
|
|
|
nvmem-cells = <&ssip_config>;
|
|
nvmem-cell-names = "ssip_config";
|
|
|
|
qcom,platform-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,platform-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "mmcx";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&mdss_dsi0 {
|
|
vdda-1p2-supply = <&L3G>;
|
|
qcom,split-link-supported;
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
|
<&mdss_dsi_phy0 1>,
|
|
<&dispcc DISP_CC_ESYNC0_CLK>,
|
|
<&dispcc DISP_CC_ESYNC0_CLK_SRC>,
|
|
<&dispcc DISP_CC_OSC_CLK>,
|
|
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
|
"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk",
|
|
"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo";
|
|
};
|
|
|
|
&mdss_dsi1 {
|
|
vdda-1p2-supply = <&L3G>;
|
|
qcom,split-link-supported;
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
|
<&mdss_dsi_phy1 1>,
|
|
<&dispcc DISP_CC_ESYNC1_CLK>,
|
|
<&dispcc DISP_CC_ESYNC1_CLK_SRC>,
|
|
<&dispcc DISP_CC_OSC_CLK>,
|
|
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
|
"pixel_clk", "pixel_clk_rcg", "pll_dsi_clk",
|
|
"esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo";
|
|
};
|
|
|
|
&mdss_dsi_phy0 {
|
|
vdda-0p9-supply = <&L3I>;
|
|
qcom,panel-allow-phy-poweroff;
|
|
qcom,dsi-pll-ssc-en;
|
|
qcom,dsi-pll-ssc-mode = "down-spread";
|
|
pll_codes_region = <&dsi_pll_codes_data>;
|
|
|
|
};
|
|
|
|
&mdss_dsi_phy1 {
|
|
vdda-0p9-supply = <&L3I>;
|
|
qcom,panel-allow-phy-poweroff;
|
|
qcom,dsi-pll-ssc-en;
|
|
qcom,dsi-pll-ssc-mode = "down-spread";
|
|
};
|