bdedd83bd9
Adds pinctrl configuration to pass esync signal through from hw block to output pin. Also adds esync and oscillator clocks, and makes the DSI PLL clock available to parse for setting clock parent. Change-Id: I09ac2d1a334546452176285712d8c953f94aecf2 Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
169 lines
2.9 KiB
Plaintext
169 lines
2.9 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
&tlmm {
|
|
pmx_sde: pmx_sde {
|
|
sde_dsi_active: sde_dsi_active {
|
|
mux {
|
|
pins = "gpio98";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio98";
|
|
drive-strength = <8>; /* 8 mA */
|
|
bias-disable = <0>; /* no pull */
|
|
};
|
|
};
|
|
|
|
sde_dsi_suspend: sde_dsi_suspend {
|
|
mux {
|
|
pins = "gpio98";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio98";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
|
|
sde_dsi1_active: sde_dsi1_active {
|
|
mux {
|
|
pins = "gpio97";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio97";
|
|
drive-strength = <8>; /* 8 mA */
|
|
bias-disable = <0>; /* no pull */
|
|
};
|
|
};
|
|
|
|
sde_dsi1_suspend: sde_dsi1_suspend {
|
|
mux {
|
|
pins = "gpio97";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio97";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_sde_te: pmx_sde_te {
|
|
sde_te_active: sde_te_active {
|
|
mux {
|
|
pins = "gpio86";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio86";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
|
|
sde_te_suspend: sde_te_suspend {
|
|
mux {
|
|
pins = "gpio86";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio86";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
|
|
sde_te1_active: sde_te1_active {
|
|
mux {
|
|
pins = "gpio87";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio87";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
|
|
sde_te1_suspend: sde_te1_suspend {
|
|
mux {
|
|
pins = "gpio87";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio87";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_sde_esync: pmx_sde_esync {
|
|
sde_esync0_active: sde_esync0_active {
|
|
mux {
|
|
pins = "gpio88";
|
|
function = "mdp_esync0_out";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio88";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
|
|
sde_esync0_suspend: sde_esync0_suspend {
|
|
mux {
|
|
pins = "gpio88";
|
|
function = "mdp_esync0_out";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio88";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
|
|
sde_esync1_active: sde_esync1_active {
|
|
mux {
|
|
pins = "gpio100";
|
|
function = "mdp_esync1_out";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio100";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
|
|
sde_esync1_suspend: sde_esync1_suspend {
|
|
mux {
|
|
pins = "gpio100";
|
|
function = "mdp_esync1_out";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio100";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down; /* PULL DOWN */
|
|
};
|
|
};
|
|
};
|
|
};
|