6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
78 lines
1.8 KiB
YAML
78 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Aspeed SGPIO controller
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maintainers:
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- Andrew Jeffery <andrew@aj.id.au>
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description:
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This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
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AST2600 have two sgpio master one with 128 pins another one with 80 pins,
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AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
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GPIO pins can be programmed to support the following options
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- Support interrupt option for each input port and various interrupt
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sensitivity option (level-high, level-low, edge-high, edge-low)
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- Support reset tolerance option for each output port
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- Directly connected to APB bus and its shift clock is from APB bus clock
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divided by a programmable value.
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- Co-work with external signal-chained TTL components (74LV165/74LV595)
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properties:
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compatible:
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enum:
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- aspeed,ast2400-sgpio
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- aspeed,ast2500-sgpio
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- aspeed,ast2600-sgpiom
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reg:
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maxItems: 1
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gpio-controller: true
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'#gpio-cells':
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const: 2
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interrupts:
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maxItems: 1
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interrupt-controller: true
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clocks:
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maxItems: 1
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ngpios: true
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bus-frequency: true
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required:
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- compatible
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- reg
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- gpio-controller
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- '#gpio-cells'
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- interrupts
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- interrupt-controller
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- ngpios
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- clocks
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- bus-frequency
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/aspeed-clock.h>
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sgpio: sgpio@1e780200 {
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#gpio-cells = <2>;
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compatible = "aspeed,ast2500-sgpio";
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gpio-controller;
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interrupts = <40>;
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reg = <0x1e780200 0x0100>;
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clocks = <&syscon ASPEED_CLK_APB>;
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interrupt-controller;
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ngpios = <80>;
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bus-frequency = <12000000>;
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};
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