Lokesh Kumar Aakulu 29e9e7351f ARM: dts: msm: Reduce SE8 CLK to operate in lowSVS ...

To handle power regression at SE8 end reduce
SCL clock, which makes the QUP clock domain to
run in LowSVS instead of SVS. And the theoritical
latency calculated for this change is minimal, around
0.3 msec for 200 xfers.

CRs-Fixed: 3859750
Change-Id: I256e745a6edbdb356b297cf4d8909ca214840120
Signed-off-by: Lokesh Kumar Aakulu <quic_lkumar@quicinc.com>

2024-07-18 09:37:08 -07:00

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