Manish Pandey 7ba4fef4ec ARM: dts: msm: Update Reference Clock to clk8_a4 for Kera UFS 2.x ...

The Kera UFS 2.x requires a reference clock of 19.2MHz. Currently,
the reference clock provided by the DTSI node RPMH_LN_BB_CLK3
returns clk_get_rate() as 38.4MHz.

To address this, the handler is updated to use clk8_a4, ensuring the
clock rate is set to 19.2MHz.

Change-Id: I92ad772c7b86652c0dc5bdc3af18a9db900d74e5
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Signed-off-by: Vishvanath Singh <quic_vishvana@quicinc.com>

2025-01-20 15:13:53 +05:30

bindings

Merge "dt-bindings: power: Add bindings for schgm-flash driver"

2025-01-03 11:58:38 -08:00

qcom

ARM: dts: msm: Update Reference Clock to clk8_a4 for Kera UFS 2.x

2025-01-20 15:13:53 +05:30

BUILD.bazel

ARM: dts: msm: Add initial device trees for Sun SoC

2023-04-03 11:54:34 -07:00

Makefile

ARM: dts: msm: Add initial device trees for Sun SoC

2023-04-03 11:54:34 -07:00

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