Manish Pandey 67fdf207c7 ARM: dts: msm: Update Reference Clock to clk8_a4 for Kera UFS 2.x ...

The Kera UFS 2.x requires a reference clock of 19.2MHz. Currently,
the reference clock provided by the DTSI node RPMH_LN_BB_CLK3
returns clk_get_rate() as 38.4MHz.

To address this, the handler is updated to use clk8_a4, ensuring the
clock rate is set to 19.2MHz.

Change-Id: I92ad772c7b86652c0dc5bdc3af18a9db900d74e5
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>

2025-01-10 12:08:24 +05:30

2.2 KiB

Raw Blame History

View Raw