3087b9c59a
Add DT bindings for SPI which provides the resource management details for the Q2SPI geni msm driver. Change-Id: I1142c87b437177ec7587f8c0f1a823fbdb1c7fbb Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
109 lines
2.8 KiB
YAML
109 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/qcom,q2spi-msm-geni.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: GENI based Qualcomm Universal Peripheral (QUP) Qualcomm Host-Client 2-Way Transport (Q2SPI)
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maintainers:
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- Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
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- Visweswara Tanuku <quic_vtanuku@quicinc.com>
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- Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
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description:
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GENI based Qualcomm Technologies Inc Universal Peripheral version 5 (QUPv3)
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Serial Peripheral Interface (SPI)
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The QUP v3 core is a GENI based AHB slave that provides a common data path
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(an output FIFO and an input FIFO) for serial peripheral interface (SPI) mini-core.
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SPI in master mode supports up to 100MHz, chipselect less mode and up to four chip selects,
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programmable data path from 4 bits to 32 bits and numerous protocol variants.
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properties:
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compatible:
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const: qcom,q2spi-geni
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clocks:
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maxItems: 1
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clock-names:
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const: se-clk
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pinctrl-0: true
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pinctrl-1: true
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: sleep
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: tx
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- const: rx
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interconnects:
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minItems: 2
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maxItems: 3
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interconnect-names:
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minItems: 2
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items:
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- const: qup-core
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- const: qup-config
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- const: qup-memory
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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q2spi-max-frequency:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- pinctrl-names
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- q2spi-max-frequency
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examples:
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- |
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qupv3_se13_q2spi: q2spi@894000 {
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compatible = "qcom,q2spi-msm-geni";
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reg = <0x894000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
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<&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se13_q2spi_mosi_active>, <&qupv3_se13_q2spi_miso_active>,
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<&qupv3_se13_q2spi_clk_active>, <&qupv3_se13_q2spi_doorbell_active>;
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pinctrl-1 = <&qupv3_se13_q2spi_sleep>, <&qupv3_se13_q2spi_miso_sleep>;
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dmas = <&gpi_dma2 0 5 14 64 0>,
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<&gpi_dma2 1 5 14 64 0>;
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dma-names = "tx", "rx";
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q2spi-max-frequency = <10000000>;
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status = "ok";
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};
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...
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