29e9e7351f
To handle power regression at SE8 end reduce SCL clock, which makes the QUP clock domain to run in LowSVS instead of SVS. And the theoritical latency calculated for this change is minimal, around 0.3 msec for 200 xfers. CRs-Fixed: 3859750 Change-Id: I256e745a6edbdb356b297cf4d8909ca214840120 Signed-off-by: Lokesh Kumar Aakulu <quic_lkumar@quicinc.com>