37824f4ca3
Add pcie phy settings sequence in sun. Change-Id: I58dfb2ecb586ac4ce4f2e06bbc02a6cb1e803960 Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
297 lines
7.7 KiB
Plaintext
297 lines
7.7 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
&soc {
|
|
pcie0: pcie@1c00000 {
|
|
compatible = "qcom,pci-msm";
|
|
device_type = "pci";
|
|
|
|
reg = <0x01c00000 0x3000>,
|
|
<0x01c06000 0x2000>,
|
|
<0x40000000 0xf1d>,
|
|
<0x40000f20 0xa8>,
|
|
<0x40001000 0x1000>,
|
|
<0x40100000 0x100000>;
|
|
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
|
|
|
|
cell-index = <0>;
|
|
linux,pci-domain = <0>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
|
|
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
|
|
"int_d";
|
|
|
|
msi-map = <0x0 &gic_its 0x1400 0x1>,
|
|
<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */
|
|
|
|
perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
|
|
wake-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pcie0_perst_default
|
|
&pcie0_clkreq_default
|
|
&pcie0_wake_default>;
|
|
pinctrl-1 = <&pcie0_perst_default
|
|
&pcie0_clkreq_sleep
|
|
&pcie0_wake_default>;
|
|
|
|
gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
|
|
gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
|
|
vreg-1p2-supply = <&pm_v8g_l3>;
|
|
vreg-0p9-supply = <&pm_v6f_l1>;
|
|
vreg-cx-supply = <&VDD_CX_LEVEL>;
|
|
vreg-mx-supply = <&VDD_MXA_LEVEL>;
|
|
qcom,vreg-1p2-voltage-level = <1200000 1200000 18200>;
|
|
qcom,vreg-0p9-voltage-level = <912000 880000 80900>;
|
|
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
|
RPMH_REGULATOR_LEVEL_NOM 0>;
|
|
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
|
RPMH_REGULATOR_LEVEL_NOM 0>;
|
|
qcom,bw-scale = /* Gen1 */
|
|
<RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
19200000
|
|
/* Gen2 */
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
19200000
|
|
/* Gen3 */
|
|
RPMH_REGULATOR_LEVEL_NOM
|
|
RPMH_REGULATOR_LEVEL_NOM
|
|
100000000>;
|
|
|
|
interconnect-names = "icc_path";
|
|
interconnects = <&pcie_noc MASTER_PCIE_3 &mc_virt SLAVE_EBI1>;
|
|
|
|
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
|
<&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
|
|
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
|
|
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
|
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
|
|
<&pcie_0_pipe_clk>;
|
|
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
|
|
"pcie_aux_clk", "pcie_cfg_ahb_clk",
|
|
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
|
|
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
|
|
"pcie_rate_change_clk",
|
|
"gcc_ddrss_pcie_sf_qtb_clk",
|
|
"pcie_aggre_noc_axi_clk",
|
|
"gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux",
|
|
"pcie_pipe_clk_ext_src";
|
|
qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
|
|
<100000000>, <0>, <0>, <0>, <0>, <0>;
|
|
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
|
|
<0>, <0>, <0>, <1>, <0>, <0>;
|
|
|
|
resets = <&gcc GCC_PCIE_0_BCR>,
|
|
<&gcc GCC_PCIE_0_PHY_BCR>;
|
|
reset-names = "pcie_0_core_reset",
|
|
"pcie_0_phy_reset";
|
|
|
|
dma-coherent;
|
|
qcom,smmu-sid-base = <0x1400>;
|
|
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
|
|
<0x100 &apps_smmu 0x1401 0x1>;
|
|
|
|
qcom,boot-option = <0x1>;
|
|
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
|
qcom,l1-2-th-scale = <2>;
|
|
qcom,l1-2-th-value = <150>;
|
|
qcom,slv-addr-space-size = <0x4000000>;
|
|
qcom,ep-latency = <10>;
|
|
qcom,num-parf-testbus-sel = <0xb9>;
|
|
|
|
qcom,pcie-phy-ver = <93>;
|
|
qcom,phy-status-offset = <0x414>;
|
|
qcom,phy-status-bit = <6>;
|
|
qcom,phy-power-down-offset = <0x440>;
|
|
|
|
qcom,phy-sequence = <0x0440 0x03 0x0
|
|
0x00c0 0x01 0x0
|
|
0x00cc 0x62 0x0
|
|
0x00d0 0x02 0x0
|
|
0x0060 0xf8 0x0
|
|
0x0064 0x01 0x0
|
|
0x0000 0x93 0x0
|
|
0x0004 0x01 0x0
|
|
0x00e0 0x90 0x0
|
|
0x00e4 0x82 0x0
|
|
0x00f4 0x07 0x0
|
|
0x0070 0x02 0x0
|
|
0x0010 0x02 0x0
|
|
0x0074 0x16 0x0
|
|
0x0014 0x16 0x0
|
|
0x0078 0x36 0x0
|
|
0x0018 0x36 0x0
|
|
0x0110 0x08 0x0
|
|
0x00bc 0x0a 0x0
|
|
0x0120 0x42 0x0
|
|
0x0080 0x04 0x0
|
|
0x0084 0x0d 0x0
|
|
0x0020 0x0a 0x0
|
|
0x0024 0x1a 0x0
|
|
0x0088 0x41 0x0
|
|
0x0028 0x34 0x0
|
|
0x0090 0xab 0x0
|
|
0x0094 0xaa 0x0
|
|
0x0098 0x01 0x0
|
|
0x0030 0x55 0x0
|
|
0x0034 0x55 0x0
|
|
0x0038 0x01 0x0
|
|
0x0140 0x14 0x0
|
|
0x0164 0x34 0x0
|
|
0x003c 0x01 0x0
|
|
0x001c 0x04 0x0
|
|
0x0174 0x16 0x0
|
|
0x01bc 0x0f 0x0
|
|
0x0170 0xa0 0x0
|
|
0x13a4 0x38 0x0
|
|
0x12dc 0x11 0x0
|
|
0x1360 0x12 0x0
|
|
0x1364 0xda 0x0
|
|
0x1368 0x1b 0x0
|
|
0x136c 0xda 0x0
|
|
0x135c 0x19 0x0
|
|
0x1374 0x09 0x0
|
|
0x1378 0x49 0x0
|
|
0x137c 0x1b 0x0
|
|
0x1380 0x9c 0x0
|
|
0x1370 0xd1 0x0
|
|
0x1388 0x09 0x0
|
|
0x138c 0x49 0x0
|
|
0x1390 0x1b 0x0
|
|
0x1394 0x9c 0x0
|
|
0x1384 0xd1 0x0
|
|
0x12cc 0x00 0x0
|
|
0x1208 0x09 0x0
|
|
0x1214 0x05 0x0
|
|
0x124c 0x08 0x0
|
|
0x1250 0x08 0x0
|
|
0x12d8 0x09 0x0
|
|
0x1318 0x1c 0x0
|
|
0x12f8 0x07 0x0
|
|
0x13f8 0x08 0x0
|
|
0x1800 0x00 0x0
|
|
0x1084 0x35 0x0
|
|
0x108c 0x10 0x0
|
|
0x1090 0x31 0x0
|
|
0x1094 0x7f 0x0
|
|
0x10e4 0x02 0x0
|
|
0x1040 0x06 0x0
|
|
0x103c 0x18 0x0
|
|
0x1ba4 0x38 0x0
|
|
0x1adc 0x11 0x0
|
|
0x1b60 0x12 0x0
|
|
0x1b64 0xda 0x0
|
|
0x1b68 0x1b 0x0
|
|
0x1b6c 0xda 0x0
|
|
0x1b5c 0x19 0x0
|
|
0x1b74 0x09 0x0
|
|
0x1b78 0x49 0x0
|
|
0x1b7c 0x1b 0x0
|
|
0x1b80 0x9c 0x0
|
|
0x1b70 0xd1 0x0
|
|
0x1b88 0x09 0x0
|
|
0x1b8c 0x49 0x0
|
|
0x1b90 0x1b 0x0
|
|
0x1b94 0x9c 0x0
|
|
0x1b84 0xd1 0x0
|
|
0x1acc 0x00 0x0
|
|
0x1a08 0x09 0x0
|
|
0x1a14 0x05 0x0
|
|
0x1a4c 0x08 0x0
|
|
0x1a50 0x08 0x0
|
|
0x1ad8 0x09 0x0
|
|
0x1b18 0x1c 0x0
|
|
0x1af8 0x07 0x0
|
|
0x1bf8 0x08 0x0
|
|
0x1884 0x35 0x0
|
|
0x188c 0x10 0x0
|
|
0x1890 0x31 0x0
|
|
0x1894 0x7f 0x0
|
|
0x18e4 0x02 0x0
|
|
0x1840 0x06 0x0
|
|
0x183c 0x18 0x0
|
|
0x04dc 0x05 0x0
|
|
0x0588 0x77 0x0
|
|
0x0598 0x0b 0x0
|
|
0x08a4 0x1e 0x0
|
|
0x08f4 0x27 0x0
|
|
0x05e4 0x0f 0x0
|
|
0x080c 0x1d 0x0
|
|
0x0814 0x07 0x0
|
|
0x0820 0xc1 0x0
|
|
0x0894 0x00 0x0
|
|
0x05d0 0x8c 0x0
|
|
0x0568 0x17 0x0
|
|
0x0400 0x00 0x0
|
|
0x0444 0x03 0x0>;
|
|
|
|
pcie0_rp: pcie0_rp {
|
|
reg = <0 0 0 0 0>;
|
|
};
|
|
};
|
|
|
|
pcie0_msi: qcom,pcie0_msi@16110040 {
|
|
compatible = "qcom,pci-msi";
|
|
msi-controller;
|
|
reg = <0x17110040 0x0>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
|
|
status = "disabled";
|
|
};
|
|
};
|