Change the pcie devicetree node names to be in line with the
pci-bus.yaml format.
Change-Id: I46b56b7aee492c746554ac2a3575cd11c2108efb
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Disable software DRV (L1SS sleep) with PCIe instance
on sun platform as ADSP subsystem (software DRV component)
doesn't support this functionality.
Only CESTA based hardware DRV is supported.
Change-Id: I75368fab37e8bcaaa3c65320b6fdd37e023d3297
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add the missing phy gdsc node in the pcie dt node for sun.
Change-Id: I0257c6123d4d3e8fe2740569bd4def68fa3c92a8
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add device_type property for the pcie devicetree nodes
in sun.
This is needed to make sure that the pcie devicetree node
is associated with the pci bus when ranges property gets
parsed by the of/address.c driver.
And this change is mandatory for pci devicetree nodes with
the introduction of the following change in of/address.c
upstream commit <3d5089c4263d> "of/address: Add support
for 3 address cell bus".
Without this change, BAR address allocation failure will
happen as error logs below as the flags cell in ranges
property in devicetree will be read wrong.
pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000.
pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000.
pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required.
pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit].
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit].
Change-Id: I8b1591ea83784ffc19c928e1af73117657ac7f15
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add initial devicetree nodes and entries to support
PCIe RC0 port configuration on sun.
Change-Id: I3b7419bfd376a51388785cc4e2f9702ddaabe397
Signed-off-by: Lazarus Motha <quic_lmotha@quicinc.com>
