6e6d4bacc1
Add initial devicetree nodes and entries to support PCIe RC0 port configuration on sun. Change-Id: I3b7419bfd376a51388785cc4e2f9702ddaabe397 Signed-off-by: Lazarus Motha <quic_lmotha@quicinc.com>
175 lines
5.3 KiB
Plaintext
175 lines
5.3 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/gpio/gpio.h>
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&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c00000 0x3000>,
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<0x01c06000 0x2000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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msi-map = <0x0 &gic_its 0x1400 0x1>,
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<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */
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perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
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wake-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_perst_default
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&pcie0_clkreq_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_perst_default
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&pcie0_clkreq_sleep
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&pcie0_wake_default>;
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gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
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vreg-1p2-supply = <&pm_v8g_l3>;
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vreg-0p9-supply = <&pm_v6f_l1>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p2-voltage-level = <1200000 1200000 18200>;
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qcom,vreg-0p9-voltage-level = <912000 880000 80900>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_NOM
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&pcie_noc MASTER_PCIE_3 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
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<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
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<&pcie_0_pipe_clk>;
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clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
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"pcie_aux_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
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"pcie_rate_change_clk",
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"gcc_ddrss_pcie_sf_qtb_clk",
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"pcie_aggre_noc_axi_clk",
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"gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux",
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"pcie_pipe_clk_ext_src";
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qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
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<100000000>, <0>, <0>, <0>, <0>, <0>;
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clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
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<0>, <0>, <0>, <1>, <0>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x1400>;
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iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
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<0x100 &apps_smmu 0x1401 0x1>;
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qcom,boot-option = <0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,drv-name = "lpass";
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qcom,drv-l1ss-timeout-us = <5000>;
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qcom,l1-2-th-scale = <2>;
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qcom,l1-2-th-value = <150>;
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qcom,slv-addr-space-size = <0x4000000>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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qcom,phy-status-offset = <0x414>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x440>;
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@16110040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17110040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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};
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