1d4a80d339
git-subtree-dir: qcom/display git-subtree-mainline:5c1b2eea72git-subtree-split:8c12068d4d
580 lines
20 KiB
YAML
580 lines
20 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sde-dp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SDE DP
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description: |
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sde-dp is the master Display Port device which supports DP host controllers that are compatible
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with VESA Display Port interface specification.
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msm_ext_disp is a device which manages the interaction between external
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display interfaces, e.g. Display Port, and the audio subsystem.
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[Optional child nodes]: These nodes are for devices which are
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dependent on msm_ext_disp. If msm_ext_disp is disabled then
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these devices will be disabled as well. Ex. Audio Codec device.
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maintainers:
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- Rajkumar Subbiah <quic_rsubbia@quicinc.com>
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- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
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properties:
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compatible:
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const: qcom,dp-display
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reg:
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description: |
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Base address and length of DP hardware's memory mapped regions.
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reg-names:
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description: |
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A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region.
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"dp_ahb" - AHB memory region.
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"dp_aux" - AUX memory region.
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"dp_link" - LINK memory region.
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"dp_p0" - PCLK0 memory region.
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"dp_phy" - PHY memory region.
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"dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region.
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"dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region.
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"dp_mmss_cc" - Display Clock Control memory region.
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"dp_pll" - USB3 DP combo PLL memory region.
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"usb3_dp_com" - USB3 DP PHY combo memory region.
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"hdcp_physical" - DP HDCP memory region.
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"dp_p1" - DP PCLK1 memory region.
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"gdsc" - DISPCC GDSC memory region.
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cell-index:
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description: Specifies the controller instance.
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'#clock-cells':
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description: Denotes the DP driver as a clock producer (has one or more clock outputs)
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clocks:
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description: Clocks required for Display Port operation.
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clock-names:
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items:
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- const: core_aux_clk
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- const: core_usb_ref_clk_src
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- const: core_usb_pipe_clk
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- const: link_clk
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- const: link_clk_src
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- const: link_iface_clk
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- const: pixel_clk_rcg
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- const: pixel_parent
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- const: pixel1_clk_rcg
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- const: strm0_pixel_clk
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- const: strm1_pixel_clk
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vdda-1p2-supply:
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description: phandle to vdda 1.2V regulator node.
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$ref: /schemas/types.yaml#/definitions/phandle
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vdda-0p9-supply:
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description: phandle to vdda 0.9V regulator node.
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$ref: /schemas/types.yaml#/definitions/phandle
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interrupt-parent:
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description: phandle to the interrupt parent device node.
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$ref: /schemas/types.yaml#/definitions/phandle
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interrupts:
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description: The interrupt signal from the DSI block.
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qcom,aux-cfg0-settings:
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description: |
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Specifies the DP AUX configuration 0 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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qcom,aux-cfg1-settings:
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description: |
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Specifies the DP AUX configuration 1 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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qcom,aux-cfg2-settings:
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description: |
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Specifies the DP AUX configuration 2 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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qcom,aux-cfg3-settings:
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description: |
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Specifies the DP AUX configuration 3 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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qcom,aux-cfg4-settings:
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description: |
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Specifies the DP AUX configuration 4 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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qcom,aux-cfg5-settings:
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description: |
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Specifies the DP AUX configuration 5 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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qcom,aux-cfg6-settings:
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description: |
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Specifies the DP AUX configuration 6 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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qcom,aux-cfg7-settings:
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description: |
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Specifies the DP AUX configuration 7 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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qcom,aux-cfg8-settings:
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description: |
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Specifies the DP AUX configuration 8 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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qcom,aux-cfg9-settings:
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description: |
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Specifies the DP AUX configuration 9 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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programmable values.
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qcom,max-pclk-frequency-khz:
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description: An integer specifying the max. pixel clock in KHz supported by Display Port.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,mst-enable:
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description: MST feature enable control node.
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qcom,dsc-feature-enable:
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description: DSC feature enable control node.
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qcom,fec-feature-enable:
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description: FEC feature enable control node.
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qcom,qos-cpu-mask:
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description: A u32 value indicating desired PM QoS CPU affine mask
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,qos-cpu-latency-us:
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description: A u32 value indicating desired PM QoS CPU latency in usec
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,altmode-dev:
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description: Phandle for the AltMode GLink driver.
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$ref: /schemas/types.yaml#/definitions/phandle
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usb-controller:
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description: Phandle for the USB controller.
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$ref: /schemas/types.yaml#/definitions/phandle
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qcom,pll-revision:
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description: PLL hardware revision.
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usb-phy:
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description: Phandle for USB PHY driver. This is used to register for USB cable events.
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$ref: /schemas/types.yaml#/definitions/phandle
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qcom,dsc-continuous-pps:
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description: |
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Control node for sending PPS every frame in hardware for DSC over DP.
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This is needed by certain bridge chips where there is such a requirement to do so.
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qcom,dp-aux-switch:
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description: Phandle for the driver used to program the AUX switch for Display Port orientation.
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$ref: /schemas/types.yaml#/definitions/phandle
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qcom,dp-hpd-gpio:
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description: HPD gpio for direct DP connector without USB PHY or AUX switch.
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qcom,dp-gpio-aux-switch:
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description: Gpio DP AUX switch chipset support.
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clock-mmrm:
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description: |
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List of the clocks that enable setting the clk rate through MMRM driver.
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The order of the list must match the 'clocks' and 'clock-names'
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properties. The 'DISP_CC' ID of the clock must be used to enable
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the property for the respective clock, whereas a value of zero
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disables the property.
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vdd_mx-supply:
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description: phandle to vdda MX regulator node
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$ref: /schemas/types.yaml#/definitions/phandle
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qcom,aux-en-gpio:
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description: Specifies the aux-channel enable gpio.
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qcom,aux-sel-gpio:
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description: Specifies the aux-channel select gpio.
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qcom,usbplug-cc-gpio:
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description: Specifies the usbplug orientation gpio.
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qcom,ext-disp:
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description: phandle for msm-ext-display module
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$ref: /schemas/types.yaml#/definitions/phandle
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compatible:
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const: qcom,msm-ext-disp
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qcom,dp-low-power-hw-hpd:
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description: Low power hardware HPD feature enable control node
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qcom,phy-version:
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description: Phy version
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pinctrl-names:
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description: |
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List of names to assign mdss pin states defined in pinctrl device node
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Refer to pinctrl-bindings.txt
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pinctrl-<0..n>:
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description: |
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Lists phandles each pointing to the pin configuration node within a pin
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controller. These pin configurations are installed in the pinctrl
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device node. Refer to pinctrl-bindings.txt
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qcom,max-lclk-frequency-khz:
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description: An integer specifying the max. link clock in KHz supported by Display Port.
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qcom,mst-fixed-topology-ports:
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description: u32 values of which MST output port to reserve, start from one
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,hbr-rbr-voltage-swing:
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description: Specifies the voltage swing levels for HBR and RBR rates.
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qcom,hbr-rbr-pre-emphasis:
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description: Specifies the pre-emphasis levels for HBR and RBR rates.
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qcom,hbr2-3-voltage-swing:
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description: Specifies the voltage swing levels for HBR2 and HBR3 rates.
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qcom,hbr2-3-pre-emphasis:
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description: Specifies the pre-emphasis levels for HBR2 and HBR3 rates.
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compatible:
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const: qcom,msm-ext-disp-audio-codec-rx
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ext_disp_audio_codec:
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description: Node for Audio Codec.
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pattern properties:
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"qcom,+\w+\-supply\-entries":
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description: |
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A node that lists the elements of the supply used by the
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a particular "type" of DSI module. The module "types"
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can be "core", "ctrl", and "phy". Within the same type,
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there can be more than one instance of this binding,
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in which case the entry would be appended with the
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supply entry index.
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e.g. qcom,ctrl-supply-entry@0
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type: object
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patternProperties:
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"qcom,ctrl\-supply\-entry\@+\w":
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properties:
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reg:
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description: offset and length of the register set for the device.
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qcom,supply-name:
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description: name of the supply (vdd/vdda/vddio)
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$ref: /schemas/types.yaml#/definitions/string-array
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qcom,supply-min-voltage:
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description: minimum voltage level (uV)
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-max-voltage:
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description: maximum voltage level (uV)
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-enable-load:
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description: load drawn (uA) from enabled supply
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-disable-load:
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description: load drawn (uA) from disabled supply
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-pre-on-sleep:
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description: time to sleep (ms) before turning on
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-post-on-sleep:
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description: time to sleep (ms) after turning on
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-pre-off-sleep:
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description: time to sleep (ms) before turning off
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-post-off-sleep:
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description: time to sleep (ms) after turning off
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$ref: /schemas/types.yaml#/definitions/uint32
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"qcom,core\-supply\-entry\@+\w":
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properties:
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reg:
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description: offset and length of the register set for the device.
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qcom,supply-name:
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description: name of the supply (vdd/vdda/vddio)
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$ref: /schemas/types.yaml#/definitions/string-array
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qcom,supply-min-voltage:
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description: minimum voltage level (uV)
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-max-voltage:
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description: maximum voltage level (uV)
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-enable-load:
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description: load drawn (uA) from enabled supply
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-disable-load:
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description: load drawn (uA) from disabled supply
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-pre-on-sleep:
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description: time to sleep (ms) before turning on
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-post-on-sleep:
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description: time to sleep (ms) after turning on
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-pre-off-sleep:
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description: time to sleep (ms) before turning off
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-post-off-sleep:
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description: time to sleep (ms) after turning off
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$ref: /schemas/types.yaml#/definitions/uint32
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"qcom,phy\-supply\-entry\@+\w":
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properties:
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reg:
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description: offset and length of the register set for the device.
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qcom,supply-name:
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description: name of the supply (vdd/vdda/vddio)
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$ref: /schemas/types.yaml#/definitions/string-array
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qcom,supply-min-voltage:
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description: minimum voltage level (uV)
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-max-voltage:
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description: maximum voltage level (uV)
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-enable-load:
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description: load drawn (uA) from enabled supply
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-disable-load:
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description: load drawn (uA) from disabled supply
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-pre-on-sleep:
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description: time to sleep (ms) before turning on
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-post-on-sleep:
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description: time to sleep (ms) after turning on
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-pre-off-sleep:
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description: time to sleep (ms) before turning off
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,supply-post-off-sleep:
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description: time to sleep (ms) after turning off
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$ref: /schemas/types.yaml#/definitions/uint32
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required:
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- compatible
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- reg
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- reg-names
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- cell-index
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- '#clock-cells'
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- clocks
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- clock-names
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- vdda-1p2-supply
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- vdda-0p9-supply
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- interrupt-parent
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- interrupts
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- qcom,aux-cfg0-settings
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- qcom,aux-cfg1-settings
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- qcom,aux-cfg2-settings
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- qcom,aux-cfg3-settings
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- qcom,aux-cfg4-settings
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- qcom,aux-cfg5-settings
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- qcom,aux-cfg6-settings
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- qcom,aux-cfg7-settings
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- qcom,aux-cfg8-settings
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- qcom,aux-cfg9-settings
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- qcom,max-pclk-frequency-khz
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- qcom,mst-enable
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- qcom,dsc-feature-enable
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- qcom,fec-feature-enable
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- qcom,qos-cpu-mask
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- qcom,qos-cpu-latency-us
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- qcom,altmode-dev
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- usb-controller
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- qcom,pll-revision
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- usb-phy
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- qcom,dp-aux-switch
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- qcom,dp-hpd-gpio
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- qcom,dp-gpio-aux-switch
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- qcom,<type>-supply-entries
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examples:
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- |
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ext_disp: qcom,msm-ext-disp {
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compatible = "qcom,msm-ext-disp";
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ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
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compatible = "qcom,msm-ext-disp-audio-codec-rx";
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};
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};
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- |
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sde_dp: qcom,dp_display@0 {
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cell-index = <0>;
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compatible = "qcom,dp-display";
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qcom,dp-aux-switch = <&fsa4480>;
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qcom,ext-disp = <&ext_disp>;
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qcom,altmode-dev = <&altmode 0>;
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usb-controller = <&usb0>;
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reg = <0xae90000 0x0dc>,
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<0xae90200 0x0c0>,
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<0xae90400 0x508>,
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<0xae91000 0x094>,
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<0x88eaa00 0x200>,
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<0x88ea200 0x200>,
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<0x88ea600 0x200>,
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<0xaf02000 0x1a0>,
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<0x88ea000 0x200>,
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<0x88e8000 0x20>,
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<0x0aee1000 0x034>,
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<0xae91400 0x094>,
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<0xaf03000 0x8>;
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reg-names = "dp_ahb", "dp_aux", "dp_link",
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"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
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"dp_mmss_cc", "dp_pll", "usb3_dp_com",
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"hdcp_physical", "dp_p1", "gdsc";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <12 0>;
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#clock-cells = <1>;
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clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
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<&sde_dp DP_PHY_PLL_VCO_DIV_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
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clock-names = "core_aux_clk", "core_usb_ref_clk_src",
|
|
"core_usb_pipe_clk", "link_clk", "link_clk_src",
|
|
"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
|
|
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
|
|
clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>;
|
|
|
|
qcom,pll-revision = "5nm-v1";
|
|
qcom,phy-version = <0x420>;
|
|
qcom,dp-aux-switch = <&fsa4480>;
|
|
|
|
qcom,aux-cfg0-settings = [1c 00];
|
|
qcom,aux-cfg1-settings = [20 13 23 1d];
|
|
qcom,aux-cfg2-settings = [24 00];
|
|
qcom,aux-cfg3-settings = [28 00];
|
|
qcom,aux-cfg4-settings = [2c 0a];
|
|
qcom,aux-cfg5-settings = [30 26];
|
|
qcom,aux-cfg6-settings = [34 0a];
|
|
qcom,aux-cfg7-settings = [38 03];
|
|
qcom,aux-cfg8-settings = [3c bb];
|
|
qcom,aux-cfg9-settings = [40 03];
|
|
qcom,max-pclk-frequency-khz = <593470>;
|
|
qcom,mst-enable;
|
|
qcom,dsc-feature-enable;
|
|
qcom,fec-feature-enable;
|
|
qcom,dsc-continuous-pps;
|
|
qcom,qos-cpu-mask = <0xf>;
|
|
qcom,qos-cpu-latency-us = <300>;
|
|
vdda-1p2-supply = <&L6B>;
|
|
vdda-0p9-supply = <&L1B>;
|
|
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
|
|
|
qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>,
|
|
<0x11 0x1e 0x1f 0xff>,
|
|
<0x16 0x1f 0xff 0xff>,
|
|
<0x1f 0xff 0xff 0xff>;
|
|
qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>,
|
|
<0x00 0x0e 0x15 0xff>,
|
|
<0x00 0x0e 0xff 0xff>,
|
|
<0x02 0xff 0xff 0xff>;
|
|
|
|
qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>,
|
|
<0x09 0x19 0x1f 0xff>,
|
|
<0x10 0x1f 0xff 0xff>,
|
|
<0x1f 0xff 0xff 0xff>;
|
|
qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>,
|
|
<0x02 0x0e 0x16 0xff>,
|
|
<0x02 0x11 0xff 0xff>,
|
|
<0x04 0xff 0xff 0xff>;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <21700>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <912000>;
|
|
qcom,supply-max-voltage = <912000>;
|
|
qcom,supply-enable-load = <115000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,pll-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,pll-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdd_mx";
|
|
qcom,supply-min-voltage =
|
|
<RPMH_REGULATOR_LEVEL_TURBO>;
|
|
qcom,supply-max-voltage =
|
|
<RPMH_REGULATOR_LEVEL_MAX>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
...
|