1d4a80d339
git-subtree-dir: qcom/display git-subtree-mainline:5c1b2eea72git-subtree-split:8c12068d4d
162 lines
5.5 KiB
YAML
162 lines
5.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dsi_phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies Inc. Snapdragon DSI PHY output
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description: >
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/graph.txt
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[3] Documentation/devicetree/bindings/media/video-interfaces.txt
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[4] Documentation/devicetree/bindings/display/panel/
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maintainers:
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- Vara Reddy <quic_varar@quicinc.com>
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- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
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properties:
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compatible:
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enum:
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- qcom,dsi-phy-28nm-hpm
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- qcom,dsi-phy-28nm-lp
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- qcom,dsi-phy-20nm
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- qcom,dsi-phy-28nm-8960
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- qcom,dsi-phy-14nm
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- qcom,dsi-phy-10nm
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reg:
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description: >
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Physical base address and length of the registers of PLL, PHY. Some
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revisions require the PHY regulator base address, whereas others require the
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PHY lane base address. See below for each PHY revision.
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reg-names:
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description: >
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The names of register regions. For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY "dsi_phy_regulator"
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is needed and for DSI 14nm and 10nm PHYs "dsi_phy_lane" is needed.
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required:
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- "dsi_pll"
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- "dsi_phy"
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clock-cells:
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description: >
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Must be 1. The DSI PHY block acts as a clock provider, creating
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2 clocks: A byte clock (index 0), and a pixel clock (index 1).
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const: 1
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power-domains:
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const: <&mmcc MDSS_GDSC>
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clocks:
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description: Phandles to device clocks. See [1] for details on clock bindings.
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$ref: /schemas/types.yaml#/definitions/phandle
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clock-names:
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const: iface
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$ref: /schemas/types.yaml#/definitions/string-array
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vddio-supply:
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description: >
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For 28nm HPM/LP, 28nm 8960 PHYs and 20nm PHY, this is phandle to vdd-io regulator
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device node
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$ref: /schemas/types.yaml#/definitions/phandle
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vcca-supply:
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description: For 14nm PHY and 20nm PHY this is phandle to vcca regulator device node
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$ref: /schemas/types.yaml#/definitions/phandle
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vdds-supply:
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description: For 10nm PHY , phandle to vdds regulator device node
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$ref: /schemas/types.yaml#/definitions/phandle
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qcom,dsi-phy-regulator-ldo-mode:
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description: Boolean value indicating if the LDO mode PHY regulator is wanted.
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qcom,mdss-mdp-transfer-time-us:
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description: >
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Specifies the dsi transfer time for command mode
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panels in microseconds. Driver uses this number to adjust
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the clock rate according to the expected transfer time.
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Increasing this value would slow down the mdp processing
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and can result in slower performance.
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Decreasing this value can speed up the mdp processing,
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but this can also impact power consumption.
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As a rule this time should not be higher than the time
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that would be expected with the processing at the
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dsi link rate since anyways this would be the maximum
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transfer time that could be achieved.
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If ping pong split is enabled, this time should not be higher
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than two times the dsi link rate time.
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If the property is not specified, then the default value is 14000 us.
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$ref: /schemas/types.yaml#/definitions/uint32
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frame-threshold-time-us:
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description: >
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For command mode panels, this specifies the idle
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time for dsi controller where no active data is
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send to the panel, as controller is done sending
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active pixels. If there is no desired DSI clocks
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specified, then clocks will be derived from this
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threshold time, which has a default value in chipset
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based on the CPU processing power.
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$ref: /schemas/types.yaml#/definitions/uint32
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dsi_pll_codes:
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description: Contain an u32 array data to store dsi pll codes which were passed from UEFI.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qcom,dsi-phy-shared:
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description: Boolean value indicating if the DSI phy is shared between dual displays.
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required:
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- compatible
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- reg
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- reg-names
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- clock-cells
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- power-domains
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- clocks
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- clock-names
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- vddio-supply
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- vcca-supply
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- vdds-supply
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examples:
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- |
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dsi_phy0: dsi-phy@fd922a00 {
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compatible = "qcom,dsi-phy-28nm-hpm";
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qcom,dsi-phy-index = <0>;
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reg-names =
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"dsi_pll",
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"dsi_phy",
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"dsi_phy_regulator";
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reg = <0xfd922a00 0xd4>,
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<0xfd922b00 0x2b0>,
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<0xfd922d80 0x7b>;
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clock-names = "iface";
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clocks = <&mmcc MDSS_AHB_CLK>;
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#clock-cells = <1>;
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vddio-supply = <&pma8084_l12>;
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qcom,dsi-phy-regulator-ldo-mode;
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qcom,panel-allow-phy-poweroff;
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qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>;
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qcom,panel-force-clock-lane-hs;
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pll_codes_region = <&dsi_pll_codes_data>;
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qcom,dsi-phy-shared;
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};
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dsi_pll_codes_data:dsi_pll_codes {
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reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
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label = "dsi_pll_codes";
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};
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...
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