# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dsi_phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies Inc. Snapdragon DSI PHY output

description: >
  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  [2] Documentation/devicetree/bindings/graph.txt
  [3] Documentation/devicetree/bindings/media/video-interfaces.txt
  [4] Documentation/devicetree/bindings/display/panel/

maintainers:
  - Vara Reddy <quic_varar@quicinc.com>
  - Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>

properties:
  compatible:
    enum:
      - qcom,dsi-phy-28nm-hpm
      - qcom,dsi-phy-28nm-lp
      - qcom,dsi-phy-20nm
      - qcom,dsi-phy-28nm-8960
      - qcom,dsi-phy-14nm
      - qcom,dsi-phy-10nm

  reg:
    description: >
      Physical base address and length of the registers of PLL, PHY. Some
      revisions require the PHY regulator base address, whereas others require the
      PHY lane base address. See below for each PHY revision.

  reg-names:
    description: >
      The names of register regions. For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY "dsi_phy_regulator"
      is needed and for DSI 14nm and 10nm PHYs "dsi_phy_lane" is needed.
    required:
      - "dsi_pll"
      - "dsi_phy"

  clock-cells:
    description: >
      Must be 1. The DSI PHY block acts as a clock provider, creating
      2 clocks: A byte clock (index 0), and a pixel clock (index 1).
    const: 1

  power-domains:
    const: <&mmcc MDSS_GDSC>

  clocks:
    description: Phandles to device clocks. See [1] for details on clock bindings.
    $ref: /schemas/types.yaml#/definitions/phandle

  clock-names:
    const: iface
    $ref: /schemas/types.yaml#/definitions/string-array

  vddio-supply:
    description: >
      For 28nm HPM/LP, 28nm 8960 PHYs and 20nm PHY, this is phandle to vdd-io regulator
      device node
    $ref: /schemas/types.yaml#/definitions/phandle

  vcca-supply:
    description: For 14nm PHY and 20nm PHY this is phandle to vcca regulator device node
    $ref: /schemas/types.yaml#/definitions/phandle

  vdds-supply:
    description: For 10nm PHY , phandle to vdds regulator device node
    $ref: /schemas/types.yaml#/definitions/phandle

  qcom,dsi-phy-regulator-ldo-mode:
    description: Boolean value indicating if the LDO mode PHY regulator is wanted.

  qcom,mdss-mdp-transfer-time-us:
    description: >
      Specifies the dsi transfer time for command mode
      panels in microseconds. Driver uses this number to adjust
      the clock rate according to the expected transfer time.
      Increasing this value would slow down the mdp processing
      and can result in slower performance.
      Decreasing this value can speed up the mdp processing,
      but this can also impact power consumption.
      As a rule this time should not be higher than the time
      that would be expected with the processing at the
      dsi link rate since anyways this would be the maximum
      transfer time that could be achieved.
      If ping pong split is enabled, this time should not be higher
      than two times the dsi link rate time.
      If the property is not specified, then the default value is 14000 us.
    $ref: /schemas/types.yaml#/definitions/uint32

  frame-threshold-time-us:
    description: >
      For command mode panels, this specifies the idle
      time for dsi controller where no active data is
      send to the panel, as controller is done sending
      active pixels. If there is no desired DSI clocks
      specified, then clocks will be derived from this
      threshold time, which has a default value in chipset
      based on the CPU processing power.
    $ref: /schemas/types.yaml#/definitions/uint32

  dsi_pll_codes:
    description: Contain an u32 array data to store dsi pll codes which were passed from UEFI.
    $ref: /schemas/types.yaml#/definitions/uint32-array

  qcom,dsi-phy-shared:
    description: Boolean value indicating if the DSI phy is shared between dual displays.

required:
  - compatible
  - reg
  - reg-names
  - clock-cells
  - power-domains
  - clocks
  - clock-names
  - vddio-supply
  - vcca-supply
  - vdds-supply

examples:
  - |
    dsi_phy0: dsi-phy@fd922a00 {
      compatible = "qcom,dsi-phy-28nm-hpm";
      qcom,dsi-phy-index = <0>;
      reg-names =
        "dsi_pll",
        "dsi_phy",
        "dsi_phy_regulator";
      reg =   <0xfd922a00 0xd4>,
        <0xfd922b00 0x2b0>,
        <0xfd922d80 0x7b>;
      clock-names = "iface";
      clocks = <&mmcc MDSS_AHB_CLK>;
      #clock-cells = <1>;
      vddio-supply = <&pma8084_l12>;

      qcom,dsi-phy-regulator-ldo-mode;
      qcom,panel-allow-phy-poweroff;
      qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>;
      qcom,panel-force-clock-lane-hs;
      pll_codes_region = <&dsi_pll_codes_data>;
      qcom,dsi-phy-shared;
    };

    dsi_pll_codes_data:dsi_pll_codes {
      reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
            0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
            0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
            0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
            0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
            0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
            0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
            0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
      label = "dsi_pll_codes";
    };
...