e5d54ea8bd
Describe the register, interrupts, and settings of the arm-smmu device. Change-Id: I7a2be4e5b344a40c42657e5d03f2bc88696f29c1 Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
63 lines
1.2 KiB
Plaintext
63 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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vm-config {
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vdevices {
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vsmmu@15000000 {
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vdevice-type = "vsmmu-v2";
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smmu-handle = <0x15000000>;
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num-cbs = <0x7>;
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num-smrs = <0xe>;
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patch = "/soc/apps-smmu@15000000";
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};
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};
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};
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};
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&soc {
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apps_smmu: apps-smmu@15000000 {
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/*
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* reg, #global-interrupts & interrupts properties will
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* be added dynamically by bootloader.
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*/
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compatible = "qcom,qsmmu-v500", "qcom,virt-smmu";
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#iommu-cells = <2>;
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qcom,use-3-lvl-tables;
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dma-coherent;
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qcom,actlr =
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/* CAM_HF:Camera */
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<0x1c08 0x0000 0x00000001>,
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/* Mnoc_HF_23:Display */
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<0x0804 0x0002 0x00000001>,
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/* NSP:Compute */
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<0x0c0b 0x0000 0x00000303>,
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/* SF:Camera IPE*/
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<0x1808 0x0020 0x00000001>,
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/* SF:Camera CDM IPE/IFE/OFE*/
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<0x1841 0x0000 0x00000001>,
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<0x1861 0x0000 0x00000001>,
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<0x1881 0x0000 0x00000001>,
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/* SF:Camera ICP*/
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<0x18c2 0x0000 0x00000001>,
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<0x1982 0x0000 0x00000001>,
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/* SF:Camera CRE*/
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<0x18e8 0x0000 0x00000103>,
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/* SF:EVA */
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<0x1901 0x0020 0x00000103>,
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<0x1925 0x0000 0x00000103>;
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};
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};
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