ARM: dts: msm: Add arm-smmu device on kera-vm

Describe the register, interrupts, and settings of the arm-smmu device.

Change-Id: I7a2be4e5b344a40c42657e5d03f2bc88696f29c1
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>

qcom/kera-vm.dtsi

@@ -244,3 +244,5 @@
 		qcom,support-hypervisor;
 	};
 };
+
+#include "msm-arm-smmu-kera-vm.dtsi"

qcom/msm-arm-smmu-kera-vm.dtsi

@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	vm-config {
+		vdevices {
+			vsmmu@15000000 {
+				vdevice-type = "vsmmu-v2";
+				smmu-handle = <0x15000000>;
+				num-cbs = <0x7>;
+				num-smrs = <0xe>;
+				patch = "/soc/apps-smmu@15000000";
+			};
+		};
+	};
+};
+
+&soc {
+	apps_smmu: apps-smmu@15000000 {
+		/*
+		 * reg, #global-interrupts & interrupts  properties will
+		 * be added dynamically by bootloader.
+		 */
+		compatible = "qcom,qsmmu-v500", "qcom,virt-smmu";
+		#iommu-cells = <2>;
+		qcom,use-3-lvl-tables;
+		dma-coherent;
+
+		qcom,actlr =
+			/* CAM_HF:Camera */
+			<0x1c08 0x0000 0x00000001>,
+
+			/* Mnoc_HF_23:Display */
+			<0x0804 0x0002 0x00000001>,
+
+			/* NSP:Compute */
+			<0x0c0b 0x0000 0x00000303>,
+
+			/* SF:Camera IPE*/
+			<0x1808 0x0020 0x00000001>,
+
+			/* SF:Camera CDM IPE/IFE/OFE*/
+			<0x1841 0x0000 0x00000001>,
+			<0x1861 0x0000 0x00000001>,
+			<0x1881 0x0000 0x00000001>,
+
+			/* SF:Camera ICP*/
+			<0x18c2 0x0000 0x00000001>,
+			<0x1982 0x0000 0x00000001>,
+
+			/* SF:Camera CRE*/
+			<0x18e8 0x0000 0x00000103>,
+
+			/* SF:EVA */
+			<0x1901 0x0020 0x00000103>,
+			<0x1925 0x0000 0x00000103>;
+	};
+};