f6a2bfe1ee
Add qcom geni serial binding for Sun device. Change-Id: I48d0d75fc39d04e87ef053f468e638860f66329f Signed-off-by: Prasanna S <quic_prass@quicinc.com>
91 lines
2.0 KiB
YAML
91 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm Geni based QUP UART interface
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maintainers:
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- Andy Gross <agross@kernel.org>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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allOf:
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- $ref: /schemas/serial/serial.yaml#
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properties:
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compatible:
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enum:
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- qcom,geni-uart
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- qcom,geni-debug-uart
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clocks:
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maxItems: 1
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clock-names:
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const: se-clk
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interconnects:
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maxItems: 3
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interconnect-names:
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items:
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- const: qup-core
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- const: qup-config
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- const: qup-memory
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interrupts:
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minItems: 1
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items:
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- description: UART core irq
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operating-points-v2: true
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pinctrl-0: true
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pinctrl-1: true
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: sleep
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/interconnect/qcom,sun.h>
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qupv3_se0_2uart: qcom,qup_uart@a88000 {
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compatible = "qcom,geni-uart";
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reg = <0xa88000 0x7000>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-0 = <&qup_uart0_default>;
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pinctrl-names = "default", "sleep";
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
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<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_2uart_tx_active>, <&qupv3_se0_2uart_rx_active>;
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pinctrl-1 = <&qupv3_se0_2uart_sleep>;
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};
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...
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