# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Geni based QUP UART interface

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>

allOf:
  - $ref: /schemas/serial/serial.yaml#

properties:
  compatible:
    enum:
      - qcom,geni-uart
      - qcom,geni-debug-uart

  clocks:
    maxItems: 1

  clock-names:
    const: se-clk

  interconnects:
    maxItems: 3

  interconnect-names:
    items:
      - const: qup-core
      - const: qup-config
      - const: qup-memory

  interrupts:
    minItems: 1
    items:
      - description: UART core irq

  operating-points-v2: true

  pinctrl-0: true
  pinctrl-1: true

  pinctrl-names:
    minItems: 1
    items:
      - const: default
      - const: sleep

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,gcc-sun.h>
    #include <dt-bindings/interconnect/qcom,sun.h>

    qupv3_se0_2uart: qcom,qup_uart@a88000 {
        compatible = "qcom,geni-uart";
        reg = <0xa88000 0x7000>;
        interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
        clock-names = "se-clk";
        clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
        pinctrl-0 = <&qup_uart0_default>;
        pinctrl-names = "default", "sleep";
        interconnect-names = "qup-core", "qup-config", "qup-memory";
        interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
                        <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
                        <&aggre1_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI0>;
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&qupv3_se0_2uart_tx_active>, <&qupv3_se0_2uart_rx_active>;
        pinctrl-1 = <&qupv3_se0_2uart_sleep>;
    };
...