Add interconnect device bindings for Parrot SoC. These devices
can be used to describe any RPMH and NoC based interconnect devices.
Change-Id: I6c07467e58283ec88abe054c3e68b6f1af050065
Signed-off-by: Chetan C R <quic_cchinnad@quicinc.com>
Add bazel and dts support for monaco target.
Change-Id: Ife045d71b94102f54c25852cdde5e911c1ad7ba4
Signed-off-by: Naresh Kumar Lingagalla <quic_nlingaga@quicinc.com>
The tui_demura heap will be used by display on sun-vm.
Change-Id: Ic99e7cfef111e3e289ad2d056b0eea463d6af1fe
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Change the minimum mode allowed for L2J from low power mode (LPM) to
retention mode. This can be used to ensure that power is saved once
the secure processor is out of reset.
Change-Id: I2b6b7c88b3ea9cc1f2105ff4999d44b96e0b7aeb
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Adding a 4-byte register entry for tcsr_dyn-en-dis to enable/disable USB
dynamically from dwc3-msm-core.
Change-Id: If9c2aa8f91c4067483e0e917ca7e84d4a6894cd5
Signed-off-by: Ronak Vijay Raheja <quic_rraheja@quicinc.com>
SOCCP uses mx and cx power rails and not the island rails.
Change-Id: I52f3f28f9206e62b4b7dc99dd4c7c9f19d6f92cf
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
SOCCP requires only LOWSVS power level for the regulators.
Change-Id: I940304eacd9d4e039d65b42866daf69aaae75b85
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Mark gpucc clock node as GenPD provider and disable the
graphics GDSC regulator nodes. While at it, update gxclkctl
node to add support for gx_clkctl_gx_gdsc power domain.
Change-Id: I0d4c84da2e3aadd7e1a901d6a9e26c7d4ad1a3c1
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Add minidump vdevice to enable minidump support for OEMVM.
Change-Id: I2e4b371cabd8ac1fc2362011e55bd4eb556da70e
Signed-off-by: Cong Zhang <quic_congzhan@quicinc.com>
This reverts commit 5f034afc81.
Reason for revert: We are facing compilation failures when making
a full sun Android build.
Change-Id: Iacbc3022889045357cb2cc0a68047732a80cbbd2
Signed-off-by: Bruce Levy <quic_blevy@quicinc.com>
Signed-off-by: Vivekanand Tryambake <quic_vtryamba@quicinc.com>
Currently, the mechanism to send AOP cmd to offline memblocks is
disabled. Enable the mechanism to achieve desired power savings.
Change-Id: I68a25c34801d020c901ddc7d3e27099a22e88f01
Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
The default MTP's board-id doesn't mention major version no.
since it's the first version, so follow the same for QMP1000's
board-id and keep only the minor version.
Change-Id: Ifc09d5121e5b262a9bf1b66573c883aa17040f1d
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Since system health monitor has been moved to user space, this commit
removes its node from device tree.
Change-Id: I87f180c01d0e0a594b924f01722156c2a08ca086
Signed-off-by: Huang Yiwei <quic_hyiwei@quicinc.com>
Update the base device tree as the SunP HDK using V8 Power Grid.
Change-Id: I6859f0595a3b010b5a7015dc2ed3bb3078108fc4
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
As Frame 2 was assigned to TZ for secure world timer, moving
IRQ lend test qtimer from frame 2 view 1 to frame 5.
Change-Id: I855b881f12b970c56bf595fffcc57ffadf184a58
Signed-off-by: Po-Jung Lai <quic_pojulai@quicinc.com>
Add properties to the PM8550VE_F spmi-temp-alarm device to specify
it's die temperature ADC channel on Sun power grid V8 boards. This
ensures that software is able to read it's precise die temperature
instead of estimating it based on the TEMP_ALARM peripheral
over-temperature stage.
Change-Id: I726e2ca236db94ef8aa7f6c19b3f4c74f745c763
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add clock controller bindings for RPMHCC/GCC/CAMCC/VIDEOCC/DISPCC/GPUCC
on Parrot Platform.
Change-Id: Iaa50f7bf3758ea5fba1fe4249b7b16173320521d
Signed-off-by: Chetan C R <quic_cchinnad@quicinc.com>
